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riscv-gcc-1
Commit db5db9d2 by Srinath Parvathaneni Committed by Kyrylo Tkachov
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[ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. 

This patch supports following MVE ACLE intrinsics with quaternary operands.

vsriq_m_n_s8, vsubq_m_s8, vsubq_x_s8, vcvtq_m_n_f16_u16, vcvtq_x_n_f16_u16,
vqshluq_m_n_s8, vabavq_p_s8, vsriq_m_n_u8, vshlq_m_u8, vshlq_x_u8, vsubq_m_u8,
vsubq_x_u8, vabavq_p_u8, vshlq_m_s8, vshlq_x_s8, vcvtq_m_n_f16_s16,
vcvtq_x_n_f16_s16, vsriq_m_n_s16, vsubq_m_s16, vsubq_x_s16, vcvtq_m_n_f32_u32,
vcvtq_x_n_f32_u32, vqshluq_m_n_s16, vabavq_p_s16, vsriq_m_n_u16,
vshlq_m_u16, vshlq_x_u16, vsubq_m_u16, vsubq_x_u16, vabavq_p_u16, vshlq_m_s16,
vshlq_x_s16, vcvtq_m_n_f32_s32, vcvtq_x_n_f32_s32, vsriq_m_n_s32, vsubq_m_s32,
vsubq_x_s32, vqshluq_m_n_s32, vabavq_p_s32, vsriq_m_n_u32, vshlq_m_u32,
vshlq_x_u32, vsubq_m_u32, vsubq_x_u32, vabavq_p_u32, vshlq_m_s32, vshlq_x_s32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
	Define builtin qualifier.
	(QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
	(vsubq_m_s8): Likewise.
	(vcvtq_m_n_f16_u16): Likewise.
	(vqshluq_m_n_s8): Likewise.
	(vabavq_p_s8): Likewise.
	(vsriq_m_n_u8): Likewise.
	(vshlq_m_u8): Likewise.
	(vsubq_m_u8): Likewise.
	(vabavq_p_u8): Likewise.
	(vshlq_m_s8): Likewise.
	(vcvtq_m_n_f16_s16): Likewise.
	(vsriq_m_n_s16): Likewise.
	(vsubq_m_s16): Likewise.
	(vcvtq_m_n_f32_u32): Likewise.
	(vqshluq_m_n_s16): Likewise.
	(vabavq_p_s16): Likewise.
	(vsriq_m_n_u16): Likewise.
	(vshlq_m_u16): Likewise.
	(vsubq_m_u16): Likewise.
	(vabavq_p_u16): Likewise.
	(vshlq_m_s16): Likewise.
	(vcvtq_m_n_f32_s32): Likewise.
	(vsriq_m_n_s32): Likewise.
	(vsubq_m_s32): Likewise.
	(vqshluq_m_n_s32): Likewise.
	(vabavq_p_s32): Likewise.
	(vsriq_m_n_u32): Likewise.
	(vshlq_m_u32): Likewise.
	(vsubq_m_u32): Likewise.
	(vabavq_p_u32): Likewise.
	(vshlq_m_s32): Likewise.
	(__arm_vsriq_m_n_s8): Define intrinsic.
	(__arm_vsubq_m_s8): Likewise.
	(__arm_vqshluq_m_n_s8): Likewise.
	(__arm_vabavq_p_s8): Likewise.
	(__arm_vsriq_m_n_u8): Likewise.
	(__arm_vshlq_m_u8): Likewise.
	(__arm_vsubq_m_u8): Likewise.
	(__arm_vabavq_p_u8): Likewise.
	(__arm_vshlq_m_s8): Likewise.
	(__arm_vsriq_m_n_s16): Likewise.
	(__arm_vsubq_m_s16): Likewise.
	(__arm_vqshluq_m_n_s16): Likewise.
	(__arm_vabavq_p_s16): Likewise.
	(__arm_vsriq_m_n_u16): Likewise.
	(__arm_vshlq_m_u16): Likewise.
	(__arm_vsubq_m_u16): Likewise.
	(__arm_vabavq_p_u16): Likewise.
	(__arm_vshlq_m_s16): Likewise.
	(__arm_vsriq_m_n_s32): Likewise.
	(__arm_vsubq_m_s32): Likewise.
	(__arm_vqshluq_m_n_s32): Likewise.
	(__arm_vabavq_p_s32): Likewise.
	(__arm_vsriq_m_n_u32): Likewise.
	(__arm_vshlq_m_u32): Likewise.
	(__arm_vsubq_m_u32): Likewise.
	(__arm_vabavq_p_u32): Likewise.
	(__arm_vshlq_m_s32): Likewise.
	(__arm_vcvtq_m_n_f16_u16): Likewise.
	(__arm_vcvtq_m_n_f16_s16): Likewise.
	(__arm_vcvtq_m_n_f32_u32): Likewise.
	(__arm_vcvtq_m_n_f32_s32): Likewise.
	(vcvtq_m_n): Define polymorphic variant.
	(vqshluq_m_n): Likewise.
	(vshlq_m): Likewise.
	(vsriq_m_n): Likewise.
	(vsubq_m): Likewise.
	(vabavq_p): Likewise.
	* config/arm/arm_mve_builtins.def
	(QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
	(QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
	* config/arm/mve.md (VABAVQ_P): Define iterator.
	(VSHLQ_M): Likewise.
	(VSRIQ_M_N): Likewise.
	(VSUBQ_M): Likewise.
	(VCVTQ_M_N_TO_F): Likewise.
	(mve_vabavq_p_<supf><mode>): Define RTL pattern.
	(mve_vqshluq_m_n_s<mode>): Likewise.
	(mve_vshlq_m_<supf><mode>): Likewise.
	(mve_vsriq_m_n_<supf><mode>): Likewise.
	(mve_vsubq_m_<supf><mode>): Likewise.
	(mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
parent e3678b44
Showing with 1034 additions and 8 deletions
gcc/ChangeLog
......@@ -2,6 +2,108 @@
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
Define builtin qualifier.
(QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
(QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
(vsubq_m_s8): Likewise.
(vcvtq_m_n_f16_u16): Likewise.
(vqshluq_m_n_s8): Likewise.
(vabavq_p_s8): Likewise.
(vsriq_m_n_u8): Likewise.
(vshlq_m_u8): Likewise.
(vsubq_m_u8): Likewise.
(vabavq_p_u8): Likewise.
(vshlq_m_s8): Likewise.
(vcvtq_m_n_f16_s16): Likewise.
(vsriq_m_n_s16): Likewise.
(vsubq_m_s16): Likewise.
(vcvtq_m_n_f32_u32): Likewise.
(vqshluq_m_n_s16): Likewise.
(vabavq_p_s16): Likewise.
(vsriq_m_n_u16): Likewise.
(vshlq_m_u16): Likewise.
(vsubq_m_u16): Likewise.
(vabavq_p_u16): Likewise.
(vshlq_m_s16): Likewise.
(vcvtq_m_n_f32_s32): Likewise.
(vsriq_m_n_s32): Likewise.
(vsubq_m_s32): Likewise.
(vqshluq_m_n_s32): Likewise.
(vabavq_p_s32): Likewise.
(vsriq_m_n_u32): Likewise.
(vshlq_m_u32): Likewise.
(vsubq_m_u32): Likewise.
(vabavq_p_u32): Likewise.
(vshlq_m_s32): Likewise.
(__arm_vsriq_m_n_s8): Define intrinsic.
(__arm_vsubq_m_s8): Likewise.
(__arm_vqshluq_m_n_s8): Likewise.
(__arm_vabavq_p_s8): Likewise.
(__arm_vsriq_m_n_u8): Likewise.
(__arm_vshlq_m_u8): Likewise.
(__arm_vsubq_m_u8): Likewise.
(__arm_vabavq_p_u8): Likewise.
(__arm_vshlq_m_s8): Likewise.
(__arm_vsriq_m_n_s16): Likewise.
(__arm_vsubq_m_s16): Likewise.
(__arm_vqshluq_m_n_s16): Likewise.
(__arm_vabavq_p_s16): Likewise.
(__arm_vsriq_m_n_u16): Likewise.
(__arm_vshlq_m_u16): Likewise.
(__arm_vsubq_m_u16): Likewise.
(__arm_vabavq_p_u16): Likewise.
(__arm_vshlq_m_s16): Likewise.
(__arm_vsriq_m_n_s32): Likewise.
(__arm_vsubq_m_s32): Likewise.
(__arm_vqshluq_m_n_s32): Likewise.
(__arm_vabavq_p_s32): Likewise.
(__arm_vsriq_m_n_u32): Likewise.
(__arm_vshlq_m_u32): Likewise.
(__arm_vsubq_m_u32): Likewise.
(__arm_vabavq_p_u32): Likewise.
(__arm_vshlq_m_s32): Likewise.
(__arm_vcvtq_m_n_f16_u16): Likewise.
(__arm_vcvtq_m_n_f16_s16): Likewise.
(__arm_vcvtq_m_n_f32_u32): Likewise.
(__arm_vcvtq_m_n_f32_s32): Likewise.
(vcvtq_m_n): Define polymorphic variant.
(vqshluq_m_n): Likewise.
(vshlq_m): Likewise.
(vsriq_m_n): Likewise.
(vsubq_m): Likewise.
(vabavq_p): Likewise.
* config/arm/arm_mve_builtins.def
(QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
(QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
(QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
(QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
* config/arm/mve.md (VABAVQ_P): Define iterator.
(VSHLQ_M): Likewise.
(VSRIQ_M_N): Likewise.
(VSUBQ_M): Likewise.
(VCVTQ_M_N_TO_F): Likewise.
(mve_vabavq_p_<supf><mode>): Define RTL pattern.
(mve_vqshluq_m_n_s<mode>): Likewise.
(mve_vshlq_m_<supf><mode>): Likewise.
(mve_vsriq_m_n_<supf><mode>): Likewise.
(mve_vsubq_m_<supf><mode>): Likewise.
(mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
(vrmlsldavhaq_s32): Likewise.
(vrmlsldavhaxq_s32): Likewise.
......
gcc/config/arm/arm-builtins.c
......@@ -523,6 +523,62 @@ arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS \
(arm_ternop_none_none_none_none_qualifiers)
static enum arm_type_qualifiers
arm_quadop_unone_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_none,
qualifier_unsigned };
#define QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS \
(arm_quadop_unone_unone_none_none_unone_qualifiers)
static enum arm_type_qualifiers
arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_none,
qualifier_unsigned };
#define QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS \
(arm_quadop_none_none_none_none_unone_qualifiers)
static enum arm_type_qualifiers
arm_quadop_none_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate,
qualifier_unsigned };
#define QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS \
(arm_quadop_none_none_none_imm_unone_qualifiers)
static enum arm_type_qualifiers
arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
qualifier_unsigned, qualifier_unsigned };
#define QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \
(arm_quadop_unone_unone_unone_unone_unone_qualifiers)
static enum arm_type_qualifiers
arm_quadop_unone_unone_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_none,
qualifier_immediate, qualifier_unsigned };
#define QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS \
(arm_quadop_unone_unone_none_imm_unone_qualifiers)
static enum arm_type_qualifiers
arm_quadop_none_none_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate,
qualifier_unsigned };
#define QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS \
(arm_quadop_none_none_unone_imm_unone_qualifiers)
static enum arm_type_qualifiers
arm_quadop_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
qualifier_immediate, qualifier_unsigned };
#define QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \
(arm_quadop_unone_unone_unone_imm_unone_qualifiers)
static enum arm_type_qualifiers
arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
qualifier_none, qualifier_unsigned };
#define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \
(arm_quadop_unone_unone_unone_none_unone_qualifiers)
/* End of Qualifier for MVE builtins. */
/* void ([T element type] *, T, immediate). */
......
gcc/config/arm/arm_mve_builtins.def
......@@ -502,3 +502,14 @@ VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si)
VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si)
VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si)
VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsriq_m_n_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsriq_m_n_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_u, v16qi, v8hi, v4si)
VAR2 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vcvtq_m_n_to_f_u, v8hf, v4sf)
VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_to_f_s, v8hf, v4sf)
VAR3 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshluq_m_n_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE, vabavq_p_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabavq_p_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vshlq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vshlq_m_s, v16qi, v8hi, v4si)
gcc/config/arm/mve.md
......@@ -140,7 +140,10 @@
VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
VCVTQ_M_N_FROM_F_U])
VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
VCVTQ_M_N_TO_F_S])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
(V8HF "V8HI") (V4SF "V4SI")])
......@@ -244,7 +247,11 @@
(VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
(VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
(VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
(VCVTQ_M_N_FROM_F_S "s")])
(VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
(VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
(VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
(VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
(VCVTQ_M_N_TO_F_U "u")])
(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
......@@ -407,6 +414,11 @@
(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
......@@ -5551,7 +5563,7 @@
VSHRNTQ_N))
]
"TARGET_HAVE_MVE"
"vshrnt.i%#<V_sz_elem> %q0, %q2, %3"
"vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
])
......@@ -5567,7 +5579,7 @@
VCVTMQ_M))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q2"
"vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
......@@ -5583,7 +5595,7 @@
VCVTPQ_M))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q2"
"vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
......@@ -5599,7 +5611,7 @@
VCVTNQ_M))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q2"
"vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
......@@ -5616,7 +5628,7 @@
VCVTQ_M_N_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q2, %3"
"vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
......@@ -5648,7 +5660,7 @@
VCVTQ_M_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q2"
"vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
......@@ -5683,3 +5695,101 @@
"vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
;;
;; [vabavq_p_s, vabavq_p_u])
;;
(define_insn "mve_vabavq_p_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VABAVQ_P))
]
"TARGET_HAVE_MVE"
"vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
[(set_attr "type" "mve_move")
])
;;
;; [vqshluq_m_n_s])
;;
(define_insn "mve_vqshluq_m_n_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_7" "Ra")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VQSHLUQ_M_N_S))
]
"TARGET_HAVE_MVE"
"vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")])
;;
;; [vshlq_m_s, vshlq_m_u])
;;
(define_insn "mve_vshlq_m_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VSHLQ_M))
]
"TARGET_HAVE_MVE"
"vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")])
;;
;; [vsriq_m_n_s, vsriq_m_n_u])
;;
(define_insn "mve_vsriq_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VSRIQ_M_N))
]
"TARGET_HAVE_MVE"
"vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")])
;;
;; [vsubq_m_u, vsubq_m_s])
;;
(define_insn "mve_vsubq_m_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VSUBQ_M))
]
"TARGET_HAVE_MVE"
"vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")])
;;
;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
;;
(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_16" "Rd")
(match_operand:HI 4 "vpr_register_operand" "Up")]
VCVTQ_M_N_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
gcc/testsuite/ChangeLog
......@@ -2,6 +2,42 @@
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: New test.
* gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise.
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vabavq_p_s16 (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.s16" } } */
uint32_t
foo1 (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vabavq_p (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vabavq_p_s32 (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.s32" } } */
uint32_t
foo1 (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vabavq_p (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vabavq_p_s8 (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.s8" } } */
uint32_t
foo1 (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vabavq_p (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
{
return vabavq_p_u16 (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.u16" } } */
uint32_t
foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
{
return vabavq_p (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.u16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
{
return vabavq_p_u32 (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.u32" } } */
uint32_t
foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
{
return vabavq_p (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
{
return vabavq_p_u8 (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.u8" } } */
uint32_t
foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
{
return vabavq_p (a, b, c, p);
}
/* { dg-final { scan-assembler "vabavt.u8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_f16_s16 (inactive, a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
float16x8_t
foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_f16_u16 (inactive, a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
float16x8_t
foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_f32_s32 (inactive, a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
float32x4_t
foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_f32_u32 (inactive, a, 16, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
float32x4_t
foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 16, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vqshluq_m_n_s16 (inactive, a, 7, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vqshlut.s16" } } */
uint16x8_t
foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vqshluq_m (inactive, a, 7, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vqshluq_m_n_s32 (inactive, a, 7, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vqshlut.s32" } } */
uint32x4_t
foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vqshluq_m (inactive, a, 7, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vqshluq_m_n_s8 (inactive, a, 7, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vqshlut.s8" } } */
uint8x16_t
foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vqshluq_m (inactive, a, 7, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m_s16 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vshlt.s16" } } */
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m_s32 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vshlt.s32" } } */
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m_s8 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vshlt.s8" } } */
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m_u16 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vshlt.u16" } } */
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m_u32 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vshlt.u32" } } */
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m_u8 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vshlt.u8" } } */
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vsriq_m_n_s16 (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsrit.16" } } */
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vsriq_m (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vsriq_m_n_s32 (a, b, 2, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsrit.32" } } */
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vsriq_m (a, b, 2, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vsriq_m_n_s8 (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsrit.8" } } */
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vsriq_m (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vsriq_m_n_u16 (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsrit.16" } } */
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vsriq_m (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vsriq_m_n_u32 (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsrit.32" } } */
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vsriq_m (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vsriq_m_n_u8 (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsrit.8" } } */
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vsriq_m (a, b, 4, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vsubq_m_s16 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsubt.i16" } } */
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vsubq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vsubq_m_s32 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsubt.i32" } } */
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vsubq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vsubq_m_s8 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsubt.i8" } } */
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vsubq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vsubq_m_u16 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsubt.i16" } } */
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vsubq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vsubq_m_u32 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsubt.i32" } } */
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vsubq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vsubq_m_u8 (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vsubt.i8" } } */
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vsubq_m (inactive, a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
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