[ARM][GCC][3/3x]: MVE intrinsics with ternary operands.

This patch supports following MVE ACLE intrinsics with ternary operands.

vrmlaldavhaxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vaddlvaq_p_s32, vcvtbq_m_f16_f32, vcvtbq_m_f32_f16, vcvttq_m_f16_f32, vcvttq_m_f32_f16, vrev16q_m_s8, vrev32q_m_f16, vrmlaldavhq_p_s32, vrmlaldavhxq_p_s32, vrmlsldavhq_p_s32, vrmlsldavhxq_p_s32, vaddlvaq_p_u32, vrev16q_m_u8, vrmlaldavhq_p_u32, vmvnq_m_n_s16, vorrq_m_n_s16, vqrshrntq_n_s16, vqshrnbq_n_s16, vqshrntq_n_s16, vrshrnbq_n_s16, vrshrntq_n_s16, vshrnbq_n_s16, vshrntq_n_s16, vcmlaq_f16, vcmlaq_rot180_f16, vcmlaq_rot270_f16, vcmlaq_rot90_f16, vfmaq_f16, vfmaq_n_f16, vfmasq_n_f16, vfmsq_f16, vmlaldavaq_s16, vmlaldavaxq_s16, vmlsldavaq_s16, vmlsldavaxq_s16, vabsq_m_f16, vcvtmq_m_s16_f16, vcvtnq_m_s16_f16, vcvtpq_m_s16_f16, vcvtq_m_s16_f16, vdupq_m_n_f16, vmaxnmaq_m_f16, vmaxnmavq_p_f16, vmaxnmvq_p_f16, vminnmaq_m_f16, vminnmavq_p_f16, vminnmvq_p_f16, vmlaldavq_p_s16, vmlaldavxq_p_s16, vmlsldavq_p_s16, vmlsldavxq_p_s16, vmovlbq_m_s8, vmovltq_m_s8, vmovnbq_m_s16, vmovntq_m_s16, vnegq_m_f16, vpselq_f16, vqmovnbq_m_s16, vqmovntq_m_s16, vrev32q_m_s8, vrev64q_m_f16, vrndaq_m_f16, vrndmq_m_f16, vrndnq_m_f16, vrndpq_m_f16, vrndq_m_f16, vrndxq_m_f16, vcmpeqq_m_n_f16, vcmpgeq_m_f16, vcmpgeq_m_n_f16, vcmpgtq_m_f16, vcmpgtq_m_n_f16, vcmpleq_m_f16, vcmpleq_m_n_f16, vcmpltq_m_f16, vcmpltq_m_n_f16, vcmpneq_m_f16, vcmpneq_m_n_f16, vmvnq_m_n_u16, vorrq_m_n_u16, vqrshruntq_n_s16, vqshrunbq_n_s16, vqshruntq_n_s16, vcvtmq_m_u16_f16, vcvtnq_m_u16_f16, vcvtpq_m_u16_f16, vcvtq_m_u16_f16, vqmovunbq_m_s16, vqmovuntq_m_s16, vqrshrntq_n_u16, vqshrnbq_n_u16, vqshrntq_n_u16, vrshrnbq_n_u16, vrshrntq_n_u16, vshrnbq_n_u16, vshrntq_n_u16, vmlaldavaq_u16, vmlaldavaxq_u16, vmlaldavq_p_u16, vmlaldavxq_p_u16, vmovlbq_m_u8, vmovltq_m_u8, vmovnbq_m_u16, vmovntq_m_u16, vqmovnbq_m_u16, vqmovntq_m_u16, vrev32q_m_u8, vmvnq_m_n_s32, vorrq_m_n_s32, vqrshrntq_n_s32, vqshrnbq_n_s32, vqshrntq_n_s32, vrshrnbq_n_s32, vrshrntq_n_s32, vshrnbq_n_s32, vshrntq_n_s32, vcmlaq_f32, vcmlaq_rot180_f32, vcmlaq_rot270_f32, vcmlaq_rot90_f32, vfmaq_f32, vfmaq_n_f32, vfmasq_n_f32, vfmsq_f32, vmlaldavaq_s32, vmlaldavaxq_s32, vmlsldavaq_s32, vmlsldavaxq_s32, vabsq_m_f32, vcvtmq_m_s32_f32, vcvtnq_m_s32_f32, vcvtpq_m_s32_f32, vcvtq_m_s32_f32, vdupq_m_n_f32, vmaxnmaq_m_f32, vmaxnmavq_p_f32, vmaxnmvq_p_f32, vminnmaq_m_f32, vminnmavq_p_f32, vminnmvq_p_f32, vmlaldavq_p_s32, vmlaldavxq_p_s32, vmlsldavq_p_s32, vmlsldavxq_p_s32, vmovlbq_m_s16, vmovltq_m_s16, vmovnbq_m_s32, vmovntq_m_s32, vnegq_m_f32, vpselq_f32, vqmovnbq_m_s32, vqmovntq_m_s32, vrev32q_m_s16, vrev64q_m_f32, vrndaq_m_f32, vrndmq_m_f32, vrndnq_m_f32, vrndpq_m_f32, vrndq_m_f32, vrndxq_m_f32, vcmpeqq_m_n_f32, vcmpgeq_m_f32, vcmpgeq_m_n_f32, vcmpgtq_m_f32, vcmpgtq_m_n_f32, vcmpleq_m_f32, vcmpleq_m_n_f32, vcmpltq_m_f32, vcmpltq_m_n_f32, vcmpneq_m_f32, vcmpneq_m_n_f32, vmvnq_m_n_u32, vorrq_m_n_u32, vqrshruntq_n_s32, vqshrunbq_n_s32, vqshruntq_n_s32, vcvtmq_m_u32_f32, vcvtnq_m_u32_f32, vcvtpq_m_u32_f32, vcvtq_m_u32_f32, vqmovunbq_m_s32, vqmovuntq_m_s32, vqrshrntq_n_u32, vqshrnbq_n_u32, vqshrntq_n_u32, vrshrnbq_n_u32, vrshrntq_n_u32, vshrnbq_n_u32, vshrntq_n_u32, vmlaldavaq_u32, vmlaldavaxq_u32, vmlaldavq_p_u32, vmlaldavxq_p_u32, vmovlbq_m_u16, vmovltq_m_u16, vmovnbq_m_u32, vmovntq_m_u32, vqmovnbq_m_u32, vqmovntq_m_u32, vrev32q_m_u16.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
	(vrmlsldavhaq_s32): Likewise.
	(vrmlsldavhaxq_s32): Likewise.
	(vaddlvaq_p_s32): Likewise.
	(vcvtbq_m_f16_f32): Likewise.
	(vcvtbq_m_f32_f16): Likewise.
	(vcvttq_m_f16_f32): Likewise.
	(vcvttq_m_f32_f16): Likewise.
	(vrev16q_m_s8): Likewise.
	(vrev32q_m_f16): Likewise.
	(vrmlaldavhq_p_s32): Likewise.
	(vrmlaldavhxq_p_s32): Likewise.
	(vrmlsldavhq_p_s32): Likewise.
	(vrmlsldavhxq_p_s32): Likewise.
	(vaddlvaq_p_u32): Likewise.
	(vrev16q_m_u8): Likewise.
	(vrmlaldavhq_p_u32): Likewise.
	(vmvnq_m_n_s16): Likewise.
	(vorrq_m_n_s16): Likewise.
	(vqrshrntq_n_s16): Likewise.
	(vqshrnbq_n_s16): Likewise.
	(vqshrntq_n_s16): Likewise.
	(vrshrnbq_n_s16): Likewise.
	(vrshrntq_n_s16): Likewise.
	(vshrnbq_n_s16): Likewise.
	(vshrntq_n_s16): Likewise.
	(vcmlaq_f16): Likewise.
	(vcmlaq_rot180_f16): Likewise.
	(vcmlaq_rot270_f16): Likewise.
	(vcmlaq_rot90_f16): Likewise.
	(vfmaq_f16): Likewise.
	(vfmaq_n_f16): Likewise.
	(vfmasq_n_f16): Likewise.
	(vfmsq_f16): Likewise.
	(vmlaldavaq_s16): Likewise.
	(vmlaldavaxq_s16): Likewise.
	(vmlsldavaq_s16): Likewise.
	(vmlsldavaxq_s16): Likewise.
	(vabsq_m_f16): Likewise.
	(vcvtmq_m_s16_f16): Likewise.
	(vcvtnq_m_s16_f16): Likewise.
	(vcvtpq_m_s16_f16): Likewise.
	(vcvtq_m_s16_f16): Likewise.
	(vdupq_m_n_f16): Likewise.
	(vmaxnmaq_m_f16): Likewise.
	(vmaxnmavq_p_f16): Likewise.
	(vmaxnmvq_p_f16): Likewise.
	(vminnmaq_m_f16): Likewise.
	(vminnmavq_p_f16): Likewise.
	(vminnmvq_p_f16): Likewise.
	(vmlaldavq_p_s16): Likewise.
	(vmlaldavxq_p_s16): Likewise.
	(vmlsldavq_p_s16): Likewise.
	(vmlsldavxq_p_s16): Likewise.
	(vmovlbq_m_s8): Likewise.
	(vmovltq_m_s8): Likewise.
	(vmovnbq_m_s16): Likewise.
	(vmovntq_m_s16): Likewise.
	(vnegq_m_f16): Likewise.
	(vpselq_f16): Likewise.
	(vqmovnbq_m_s16): Likewise.
	(vqmovntq_m_s16): Likewise.
	(vrev32q_m_s8): Likewise.
	(vrev64q_m_f16): Likewise.
	(vrndaq_m_f16): Likewise.
	(vrndmq_m_f16): Likewise.
	(vrndnq_m_f16): Likewise.
	(vrndpq_m_f16): Likewise.
	(vrndq_m_f16): Likewise.
	(vrndxq_m_f16): Likewise.
	(vcmpeqq_m_n_f16): Likewise.
	(vcmpgeq_m_f16): Likewise.
	(vcmpgeq_m_n_f16): Likewise.
	(vcmpgtq_m_f16): Likewise.
	(vcmpgtq_m_n_f16): Likewise.
	(vcmpleq_m_f16): Likewise.
	(vcmpleq_m_n_f16): Likewise.
	(vcmpltq_m_f16): Likewise.
	(vcmpltq_m_n_f16): Likewise.
	(vcmpneq_m_f16): Likewise.
	(vcmpneq_m_n_f16): Likewise.
	(vmvnq_m_n_u16): Likewise.
	(vorrq_m_n_u16): Likewise.
	(vqrshruntq_n_s16): Likewise.
	(vqshrunbq_n_s16): Likewise.
	(vqshruntq_n_s16): Likewise.
	(vcvtmq_m_u16_f16): Likewise.
	(vcvtnq_m_u16_f16): Likewise.
	(vcvtpq_m_u16_f16): Likewise.
	(vcvtq_m_u16_f16): Likewise.
	(vqmovunbq_m_s16): Likewise.
	(vqmovuntq_m_s16): Likewise.
	(vqrshrntq_n_u16): Likewise.
	(vqshrnbq_n_u16): Likewise.
	(vqshrntq_n_u16): Likewise.
	(vrshrnbq_n_u16): Likewise.
	(vrshrntq_n_u16): Likewise.
	(vshrnbq_n_u16): Likewise.
	(vshrntq_n_u16): Likewise.
	(vmlaldavaq_u16): Likewise.
	(vmlaldavaxq_u16): Likewise.
	(vmlaldavq_p_u16): Likewise.
	(vmlaldavxq_p_u16): Likewise.
	(vmovlbq_m_u8): Likewise.
	(vmovltq_m_u8): Likewise.
	(vmovnbq_m_u16): Likewise.
	(vmovntq_m_u16): Likewise.
	(vqmovnbq_m_u16): Likewise.
	(vqmovntq_m_u16): Likewise.
	(vrev32q_m_u8): Likewise.
	(vmvnq_m_n_s32): Likewise.
	(vorrq_m_n_s32): Likewise.
	(vqrshrntq_n_s32): Likewise.
	(vqshrnbq_n_s32): Likewise.
	(vqshrntq_n_s32): Likewise.
	(vrshrnbq_n_s32): Likewise.
	(vrshrntq_n_s32): Likewise.
	(vshrnbq_n_s32): Likewise.
	(vshrntq_n_s32): Likewise.
	(vcmlaq_f32): Likewise.
	(vcmlaq_rot180_f32): Likewise.
	(vcmlaq_rot270_f32): Likewise.
	(vcmlaq_rot90_f32): Likewise.
	(vfmaq_f32): Likewise.
	(vfmaq_n_f32): Likewise.
	(vfmasq_n_f32): Likewise.
	(vfmsq_f32): Likewise.
	(vmlaldavaq_s32): Likewise.
	(vmlaldavaxq_s32): Likewise.
	(vmlsldavaq_s32): Likewise.
	(vmlsldavaxq_s32): Likewise.
	(vabsq_m_f32): Likewise.
	(vcvtmq_m_s32_f32): Likewise.
	(vcvtnq_m_s32_f32): Likewise.
	(vcvtpq_m_s32_f32): Likewise.
	(vcvtq_m_s32_f32): Likewise.
	(vdupq_m_n_f32): Likewise.
	(vmaxnmaq_m_f32): Likewise.
	(vmaxnmavq_p_f32): Likewise.
	(vmaxnmvq_p_f32): Likewise.
	(vminnmaq_m_f32): Likewise.
	(vminnmavq_p_f32): Likewise.
	(vminnmvq_p_f32): Likewise.
	(vmlaldavq_p_s32): Likewise.
	(vmlaldavxq_p_s32): Likewise.
	(vmlsldavq_p_s32): Likewise.
	(vmlsldavxq_p_s32): Likewise.
	(vmovlbq_m_s16): Likewise.
	(vmovltq_m_s16): Likewise.
	(vmovnbq_m_s32): Likewise.
	(vmovntq_m_s32): Likewise.
	(vnegq_m_f32): Likewise.
	(vpselq_f32): Likewise.
	(vqmovnbq_m_s32): Likewise.
	(vqmovntq_m_s32): Likewise.
	(vrev32q_m_s16): Likewise.
	(vrev64q_m_f32): Likewise.
	(vrndaq_m_f32): Likewise.
	(vrndmq_m_f32): Likewise.
	(vrndnq_m_f32): Likewise.
	(vrndpq_m_f32): Likewise.
	(vrndq_m_f32): Likewise.
	(vrndxq_m_f32): Likewise.
	(vcmpeqq_m_n_f32): Likewise.
	(vcmpgeq_m_f32): Likewise.
	(vcmpgeq_m_n_f32): Likewise.
	(vcmpgtq_m_f32): Likewise.
	(vcmpgtq_m_n_f32): Likewise.
	(vcmpleq_m_f32): Likewise.
	(vcmpleq_m_n_f32): Likewise.
	(vcmpltq_m_f32): Likewise.
	(vcmpltq_m_n_f32): Likewise.
	(vcmpneq_m_f32): Likewise.
	(vcmpneq_m_n_f32): Likewise.
	(vmvnq_m_n_u32): Likewise.
	(vorrq_m_n_u32): Likewise.
	(vqrshruntq_n_s32): Likewise.
	(vqshrunbq_n_s32): Likewise.
	(vqshruntq_n_s32): Likewise.
	(vcvtmq_m_u32_f32): Likewise.
	(vcvtnq_m_u32_f32): Likewise.
	(vcvtpq_m_u32_f32): Likewise.
	(vcvtq_m_u32_f32): Likewise.
	(vqmovunbq_m_s32): Likewise.
	(vqmovuntq_m_s32): Likewise.
	(vqrshrntq_n_u32): Likewise.
	(vqshrnbq_n_u32): Likewise.
	(vqshrntq_n_u32): Likewise.
	(vrshrnbq_n_u32): Likewise.
	(vrshrntq_n_u32): Likewise.
	(vshrnbq_n_u32): Likewise.
	(vshrntq_n_u32): Likewise.
	(vmlaldavaq_u32): Likewise.
	(vmlaldavaxq_u32): Likewise.
	(vmlaldavq_p_u32): Likewise.
	(vmlaldavxq_p_u32): Likewise.
	(vmovlbq_m_u16): Likewise.
	(vmovltq_m_u16): Likewise.
	(vmovnbq_m_u32): Likewise.
	(vmovntq_m_u32): Likewise.
	(vqmovnbq_m_u32): Likewise.
	(vqmovntq_m_u32): Likewise.
	(vrev32q_m_u16): Likewise.
	(__arm_vrmlaldavhaxq_s32): Define intrinsic.
	(__arm_vrmlsldavhaq_s32): Likewise.
	(__arm_vrmlsldavhaxq_s32): Likewise.
	(__arm_vaddlvaq_p_s32): Likewise.
	(__arm_vrev16q_m_s8): Likewise.
	(__arm_vrmlaldavhq_p_s32): Likewise.
	(__arm_vrmlaldavhxq_p_s32): Likewise.
	(__arm_vrmlsldavhq_p_s32): Likewise.
	(__arm_vrmlsldavhxq_p_s32): Likewise.
	(__arm_vaddlvaq_p_u32): Likewise.
	(__arm_vrev16q_m_u8): Likewise.
	(__arm_vrmlaldavhq_p_u32): Likewise.
	(__arm_vmvnq_m_n_s16): Likewise.
	(__arm_vorrq_m_n_s16): Likewise.
	(__arm_vqrshrntq_n_s16): Likewise.
	(__arm_vqshrnbq_n_s16): Likewise.
	(__arm_vqshrntq_n_s16): Likewise.
	(__arm_vrshrnbq_n_s16): Likewise.
	(__arm_vrshrntq_n_s16): Likewise.
	(__arm_vshrnbq_n_s16): Likewise.
	(__arm_vshrntq_n_s16): Likewise.
	(__arm_vmlaldavaq_s16): Likewise.
	(__arm_vmlaldavaxq_s16): Likewise.
	(__arm_vmlsldavaq_s16): Likewise.
	(__arm_vmlsldavaxq_s16): Likewise.
	(__arm_vmlaldavq_p_s16): Likewise.
	(__arm_vmlaldavxq_p_s16): Likewise.
	(__arm_vmlsldavq_p_s16): Likewise.
	(__arm_vmlsldavxq_p_s16): Likewise.
	(__arm_vmovlbq_m_s8): Likewise.
	(__arm_vmovltq_m_s8): Likewise.
	(__arm_vmovnbq_m_s16): Likewise.
	(__arm_vmovntq_m_s16): Likewise.
	(__arm_vqmovnbq_m_s16): Likewise.
	(__arm_vqmovntq_m_s16): Likewise.
	(__arm_vrev32q_m_s8): Likewise.
	(__arm_vmvnq_m_n_u16): Likewise.
	(__arm_vorrq_m_n_u16): Likewise.
	(__arm_vqrshruntq_n_s16): Likewise.
	(__arm_vqshrunbq_n_s16): Likewise.
	(__arm_vqshruntq_n_s16): Likewise.
	(__arm_vqmovunbq_m_s16): Likewise.
	(__arm_vqmovuntq_m_s16): Likewise.
	(__arm_vqrshrntq_n_u16): Likewise.
	(__arm_vqshrnbq_n_u16): Likewise.
	(__arm_vqshrntq_n_u16): Likewise.
	(__arm_vrshrnbq_n_u16): Likewise.
	(__arm_vrshrntq_n_u16): Likewise.
	(__arm_vshrnbq_n_u16): Likewise.
	(__arm_vshrntq_n_u16): Likewise.
	(__arm_vmlaldavaq_u16): Likewise.
	(__arm_vmlaldavaxq_u16): Likewise.
	(__arm_vmlaldavq_p_u16): Likewise.
	(__arm_vmlaldavxq_p_u16): Likewise.
	(__arm_vmovlbq_m_u8): Likewise.
	(__arm_vmovltq_m_u8): Likewise.
	(__arm_vmovnbq_m_u16): Likewise.
	(__arm_vmovntq_m_u16): Likewise.
	(__arm_vqmovnbq_m_u16): Likewise.
	(__arm_vqmovntq_m_u16): Likewise.
	(__arm_vrev32q_m_u8): Likewise.
	(__arm_vmvnq_m_n_s32): Likewise.
	(__arm_vorrq_m_n_s32): Likewise.
	(__arm_vqrshrntq_n_s32): Likewise.
	(__arm_vqshrnbq_n_s32): Likewise.
	(__arm_vqshrntq_n_s32): Likewise.
	(__arm_vrshrnbq_n_s32): Likewise.
	(__arm_vrshrntq_n_s32): Likewise.
	(__arm_vshrnbq_n_s32): Likewise.
	(__arm_vshrntq_n_s32): Likewise.
	(__arm_vmlaldavaq_s32): Likewise.
	(__arm_vmlaldavaxq_s32): Likewise.
	(__arm_vmlsldavaq_s32): Likewise.
	(__arm_vmlsldavaxq_s32): Likewise.
	(__arm_vmlaldavq_p_s32): Likewise.
	(__arm_vmlaldavxq_p_s32): Likewise.
	(__arm_vmlsldavq_p_s32): Likewise.
	(__arm_vmlsldavxq_p_s32): Likewise.
	(__arm_vmovlbq_m_s16): Likewise.
	(__arm_vmovltq_m_s16): Likewise.
	(__arm_vmovnbq_m_s32): Likewise.
	(__arm_vmovntq_m_s32): Likewise.
	(__arm_vqmovnbq_m_s32): Likewise.
	(__arm_vqmovntq_m_s32): Likewise.
	(__arm_vrev32q_m_s16): Likewise.
	(__arm_vmvnq_m_n_u32): Likewise.
	(__arm_vorrq_m_n_u32): Likewise.
	(__arm_vqrshruntq_n_s32): Likewise.
	(__arm_vqshrunbq_n_s32): Likewise.
	(__arm_vqshruntq_n_s32): Likewise.
	(__arm_vqmovunbq_m_s32): Likewise.
	(__arm_vqmovuntq_m_s32): Likewise.
	(__arm_vqrshrntq_n_u32): Likewise.
	(__arm_vqshrnbq_n_u32): Likewise.
	(__arm_vqshrntq_n_u32): Likewise.
	(__arm_vrshrnbq_n_u32): Likewise.
	(__arm_vrshrntq_n_u32): Likewise.
	(__arm_vshrnbq_n_u32): Likewise.
	(__arm_vshrntq_n_u32): Likewise.
	(__arm_vmlaldavaq_u32): Likewise.
	(__arm_vmlaldavaxq_u32): Likewise.
	(__arm_vmlaldavq_p_u32): Likewise.
	(__arm_vmlaldavxq_p_u32): Likewise.
	(__arm_vmovlbq_m_u16): Likewise.
	(__arm_vmovltq_m_u16): Likewise.
	(__arm_vmovnbq_m_u32): Likewise.
	(__arm_vmovntq_m_u32): Likewise.
	(__arm_vqmovnbq_m_u32): Likewise.
	(__arm_vqmovntq_m_u32): Likewise.
	(__arm_vrev32q_m_u16): Likewise.
	(__arm_vcvtbq_m_f16_f32): Likewise.
	(__arm_vcvtbq_m_f32_f16): Likewise.
	(__arm_vcvttq_m_f16_f32): Likewise.
	(__arm_vcvttq_m_f32_f16): Likewise.
	(__arm_vrev32q_m_f16): Likewise.
	(__arm_vcmlaq_f16): Likewise.
	(__arm_vcmlaq_rot180_f16): Likewise.
	(__arm_vcmlaq_rot270_f16): Likewise.
	(__arm_vcmlaq_rot90_f16): Likewise.
	(__arm_vfmaq_f16): Likewise.
	(__arm_vfmaq_n_f16): Likewise.
	(__arm_vfmasq_n_f16): Likewise.
	(__arm_vfmsq_f16): Likewise.
	(__arm_vabsq_m_f16): Likewise.
	(__arm_vcvtmq_m_s16_f16): Likewise.
	(__arm_vcvtnq_m_s16_f16): Likewise.
	(__arm_vcvtpq_m_s16_f16): Likewise.
	(__arm_vcvtq_m_s16_f16): Likewise.
	(__arm_vdupq_m_n_f16): Likewise.
	(__arm_vmaxnmaq_m_f16): Likewise.
	(__arm_vmaxnmavq_p_f16): Likewise.
	(__arm_vmaxnmvq_p_f16): Likewise.
	(__arm_vminnmaq_m_f16): Likewise.
	(__arm_vminnmavq_p_f16): Likewise.
	(__arm_vminnmvq_p_f16): Likewise.
	(__arm_vnegq_m_f16): Likewise.
	(__arm_vpselq_f16): Likewise.
	(__arm_vrev64q_m_f16): Likewise.
	(__arm_vrndaq_m_f16): Likewise.
	(__arm_vrndmq_m_f16): Likewise.
	(__arm_vrndnq_m_f16): Likewise.
	(__arm_vrndpq_m_f16): Likewise.
	(__arm_vrndq_m_f16): Likewise.
	(__arm_vrndxq_m_f16): Likewise.
	(__arm_vcmpeqq_m_n_f16): Likewise.
	(__arm_vcmpgeq_m_f16): Likewise.
	(__arm_vcmpgeq_m_n_f16): Likewise.
	(__arm_vcmpgtq_m_f16): Likewise.
	(__arm_vcmpgtq_m_n_f16): Likewise.
	(__arm_vcmpleq_m_f16): Likewise.
	(__arm_vcmpleq_m_n_f16): Likewise.
	(__arm_vcmpltq_m_f16): Likewise.
	(__arm_vcmpltq_m_n_f16): Likewise.
	(__arm_vcmpneq_m_f16): Likewise.
	(__arm_vcmpneq_m_n_f16): Likewise.
	(__arm_vcvtmq_m_u16_f16): Likewise.
	(__arm_vcvtnq_m_u16_f16): Likewise.
	(__arm_vcvtpq_m_u16_f16): Likewise.
	(__arm_vcvtq_m_u16_f16): Likewise.
	(__arm_vcmlaq_f32): Likewise.
	(__arm_vcmlaq_rot180_f32): Likewise.
	(__arm_vcmlaq_rot270_f32): Likewise.
	(__arm_vcmlaq_rot90_f32): Likewise.
	(__arm_vfmaq_f32): Likewise.
	(__arm_vfmaq_n_f32): Likewise.
	(__arm_vfmasq_n_f32): Likewise.
	(__arm_vfmsq_f32): Likewise.
	(__arm_vabsq_m_f32): Likewise.
	(__arm_vcvtmq_m_s32_f32): Likewise.
	(__arm_vcvtnq_m_s32_f32): Likewise.
	(__arm_vcvtpq_m_s32_f32): Likewise.
	(__arm_vcvtq_m_s32_f32): Likewise.
	(__arm_vdupq_m_n_f32): Likewise.
	(__arm_vmaxnmaq_m_f32): Likewise.
	(__arm_vmaxnmavq_p_f32): Likewise.
	(__arm_vmaxnmvq_p_f32): Likewise.
	(__arm_vminnmaq_m_f32): Likewise.
	(__arm_vminnmavq_p_f32): Likewise.
	(__arm_vminnmvq_p_f32): Likewise.
	(__arm_vnegq_m_f32): Likewise.
	(__arm_vpselq_f32): Likewise.
	(__arm_vrev64q_m_f32): Likewise.
	(__arm_vrndaq_m_f32): Likewise.
	(__arm_vrndmq_m_f32): Likewise.
	(__arm_vrndnq_m_f32): Likewise.
	(__arm_vrndpq_m_f32): Likewise.
	(__arm_vrndq_m_f32): Likewise.
	(__arm_vrndxq_m_f32): Likewise.
	(__arm_vcmpeqq_m_n_f32): Likewise.
	(__arm_vcmpgeq_m_f32): Likewise.
	(__arm_vcmpgeq_m_n_f32): Likewise.
	(__arm_vcmpgtq_m_f32): Likewise.
	(__arm_vcmpgtq_m_n_f32): Likewise.
	(__arm_vcmpleq_m_f32): Likewise.
	(__arm_vcmpleq_m_n_f32): Likewise.
	(__arm_vcmpltq_m_f32): Likewise.
	(__arm_vcmpltq_m_n_f32): Likewise.
	(__arm_vcmpneq_m_f32): Likewise.
	(__arm_vcmpneq_m_n_f32): Likewise.
	(__arm_vcvtmq_m_u32_f32): Likewise.
	(__arm_vcvtnq_m_u32_f32): Likewise.
	(__arm_vcvtpq_m_u32_f32): Likewise.
	(__arm_vcvtq_m_u32_f32): Likewise.
	(vcvtq_m): Define polymorphic variant.
	(vabsq_m): Likewise.
	(vcmlaq): Likewise.
	(vcmlaq_rot180): Likewise.
	(vcmlaq_rot270): Likewise.
	(vcmlaq_rot90): Likewise.
	(vcmpeqq_m_n): Likewise.
	(vcmpgeq_m_n): Likewise.
	(vrndxq_m): Likewise.
	(vrndq_m): Likewise.
	(vrndpq_m): Likewise.
	(vcmpgtq_m_n): Likewise.
	(vcmpgtq_m): Likewise.
	(vcmpleq_m): Likewise.
	(vcmpleq_m_n): Likewise.
	(vcmpltq_m_n): Likewise.
	(vcmpltq_m): Likewise.
	(vcmpneq_m): Likewise.
	(vcmpneq_m_n): Likewise.
	(vcvtbq_m): Likewise.
	(vcvttq_m): Likewise.
	(vcvtmq_m): Likewise.
	(vcvtnq_m): Likewise.
	(vcvtpq_m): Likewise.
	(vdupq_m_n): Likewise.
	(vfmaq_n): Likewise.
	(vfmaq): Likewise.
	(vfmasq_n): Likewise.
	(vfmsq): Likewise.
	(vmaxnmaq_m): Likewise.
	(vmaxnmavq_m): Likewise.
	(vmaxnmvq_m): Likewise.
	(vmaxnmavq_p): Likewise.
	(vmaxnmvq_p): Likewise.
	(vminnmaq_m): Likewise.
	(vminnmavq_p): Likewise.
	(vminnmvq_p): Likewise.
	(vrndnq_m): Likewise.
	(vrndaq_m): Likewise.
	(vrndmq_m): Likewise.
	(vrev64q_m): Likewise.
	(vrev32q_m): Likewise.
	(vpselq): Likewise.
	(vnegq_m): Likewise.
	(vcmpgeq_m): Likewise.
	(vshrntq_n): Likewise.
	(vrshrntq_n): Likewise.
	(vmovlbq_m): Likewise.
	(vmovnbq_m): Likewise.
	(vmovntq_m): Likewise.
	(vmvnq_m_n): Likewise.
	(vmvnq_m): Likewise.
	(vshrnbq_n): Likewise.
	(vrshrnbq_n): Likewise.
	(vqshruntq_n): Likewise.
	(vrev16q_m): Likewise.
	(vqshrunbq_n): Likewise.
	(vqshrntq_n): Likewise.
	(vqrshruntq_n): Likewise.
	(vqrshrntq_n): Likewise.
	(vqshrnbq_n): Likewise.
	(vqmovuntq_m): Likewise.
	(vqmovntq_m): Likewise.
	(vqmovnbq_m): Likewise.
	(vorrq_m_n): Likewise.
	(vmovltq_m): Likewise.
	(vqmovunbq_m): Likewise.
	(vaddlvaq_p): Likewise.
	(vmlaldavaq): Likewise.
	(vmlaldavaxq): Likewise.
	(vmlaldavq_p): Likewise.
	(vmlaldavxq_p): Likewise.
	(vmlsldavaq): Likewise.
	(vmlsldavaxq): Likewise.
	(vmlsldavq_p): Likewise.
	(vmlsldavxq_p): Likewise.
	(vrmlaldavhaxq): Likewise.
	(vrmlaldavhq_p): Likewise.
	(vrmlaldavhxq_p): Likewise.
	(vrmlsldavhaq): Likewise.
	(vrmlsldavhaxq): Likewise.
	(vrmlsldavhq_p): Likewise.
	(vrmlsldavhxq_p): Likewise.
	* config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
	builtin qualifier.
	(TERNOP_NONE_NONE_NONE_IMM): Likewise.
	(TERNOP_NONE_NONE_NONE_NONE): Likewise.
	(TERNOP_NONE_NONE_NONE_UNONE): Likewise.
	(TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
	(TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
	(TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
	(TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
	* config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
	(MVE_pred3): Likewise.
	(MVE_constraint1): Likewise.
	(MVE_pred1): Likewise.
	(VMLALDAVQ_P): Define iterator.
	(VQMOVNBQ_M): Likewise.
	(VMOVLTQ_M): Likewise.
	(VMOVNBQ_M): Likewise.
	(VRSHRNTQ_N): Likewise.
	(VORRQ_M_N): Likewise.
	(VREV32Q_M): Likewise.
	(VREV16Q_M): Likewise.
	(VQRSHRNTQ_N): Likewise.
	(VMOVNTQ_M): Likewise.
	(VMOVLBQ_M): Likewise.
	(VMLALDAVAQ): Likewise.
	(VQSHRNBQ_N): Likewise.
	(VSHRNBQ_N): Likewise.
	(VRSHRNBQ_N): Likewise.
	(VMLALDAVXQ_P): Likewise.
	(VQMOVNTQ_M): Likewise.
	(VMVNQ_M_N): Likewise.
	(VQSHRNTQ_N): Likewise.
	(VMLALDAVAXQ): Likewise.
	(VSHRNTQ_N): Likewise.
	(VCVTMQ_M): Likewise.
	(VCVTNQ_M): Likewise.
	(VCVTPQ_M): Likewise.
	(VCVTQ_M_N_FROM_F): Likewise.
	(VCVTQ_M_FROM_F): Likewise.
	(VRMLALDAVHQ_P): Likewise.
	(VADDLVAQ_P): Likewise.
	(mve_vrndq_m_f<mode>): Define RTL pattern.
	(mve_vabsq_m_f<mode>): Likewise.
	(mve_vaddlvaq_p_<supf>v4si): Likewise.
	(mve_vcmlaq_f<mode>): Likewise.
	(mve_vcmlaq_rot180_f<mode>): Likewise.
	(mve_vcmlaq_rot270_f<mode>): Likewise.
	(mve_vcmlaq_rot90_f<mode>): Likewise.
	(mve_vcmpeqq_m_n_f<mode>): Likewise.
	(mve_vcmpgeq_m_f<mode>): Likewise.
	(mve_vcmpgeq_m_n_f<mode>): Likewise.
	(mve_vcmpgtq_m_f<mode>): Likewise.
	(mve_vcmpgtq_m_n_f<mode>): Likewise.
	(mve_vcmpleq_m_f<mode>): Likewise.
	(mve_vcmpleq_m_n_f<mode>): Likewise.
	(mve_vcmpltq_m_f<mode>): Likewise.
	(mve_vcmpltq_m_n_f<mode>): Likewise.
	(mve_vcmpneq_m_f<mode>): Likewise.
	(mve_vcmpneq_m_n_f<mode>): Likewise.
	(mve_vcvtbq_m_f16_f32v8hf): Likewise.
	(mve_vcvtbq_m_f32_f16v4sf): Likewise.
	(mve_vcvttq_m_f16_f32v8hf): Likewise.
	(mve_vcvttq_m_f32_f16v4sf): Likewise.
	(mve_vdupq_m_n_f<mode>): Likewise.
	(mve_vfmaq_f<mode>): Likewise.
	(mve_vfmaq_n_f<mode>): Likewise.
	(mve_vfmasq_n_f<mode>): Likewise.
	(mve_vfmsq_f<mode>): Likewise.
	(mve_vmaxnmaq_m_f<mode>): Likewise.
	(mve_vmaxnmavq_p_f<mode>): Likewise.
	(mve_vmaxnmvq_p_f<mode>): Likewise.
	(mve_vminnmaq_m_f<mode>): Likewise.
	(mve_vminnmavq_p_f<mode>): Likewise.
	(mve_vminnmvq_p_f<mode>): Likewise.
	(mve_vmlaldavaq_<supf><mode>): Likewise.
	(mve_vmlaldavaxq_<supf><mode>): Likewise.
	(mve_vmlaldavq_p_<supf><mode>): Likewise.
	(mve_vmlaldavxq_p_<supf><mode>): Likewise.
	(mve_vmlsldavaq_s<mode>): Likewise.
	(mve_vmlsldavaxq_s<mode>): Likewise.
	(mve_vmlsldavq_p_s<mode>): Likewise.
	(mve_vmlsldavxq_p_s<mode>): Likewise.
	(mve_vmovlbq_m_<supf><mode>): Likewise.
	(mve_vmovltq_m_<supf><mode>): Likewise.
	(mve_vmovnbq_m_<supf><mode>): Likewise.
	(mve_vmovntq_m_<supf><mode>): Likewise.
	(mve_vmvnq_m_n_<supf><mode>): Likewise.
	(mve_vnegq_m_f<mode>): Likewise.
	(mve_vorrq_m_n_<supf><mode>): Likewise.
	(mve_vpselq_f<mode>): Likewise.
	(mve_vqmovnbq_m_<supf><mode>): Likewise.
	(mve_vqmovntq_m_<supf><mode>): Likewise.
	(mve_vqmovunbq_m_s<mode>): Likewise.
	(mve_vqmovuntq_m_s<mode>): Likewise.
	(mve_vqrshrntq_n_<supf><mode>): Likewise.
	(mve_vqrshruntq_n_s<mode>): Likewise.
	(mve_vqshrnbq_n_<supf><mode>): Likewise.
	(mve_vqshrntq_n_<supf><mode>): Likewise.
	(mve_vqshrunbq_n_s<mode>): Likewise.
	(mve_vqshruntq_n_s<mode>): Likewise.
	(mve_vrev32q_m_fv8hf): Likewise.
	(mve_vrev32q_m_<supf><mode>): Likewise.
	(mve_vrev64q_m_f<mode>): Likewise.
	(mve_vrmlaldavhaxq_sv4si): Likewise.
	(mve_vrmlaldavhxq_p_sv4si): Likewise.
	(mve_vrmlsldavhaxq_sv4si): Likewise.
	(mve_vrmlsldavhq_p_sv4si): Likewise.
	(mve_vrmlsldavhxq_p_sv4si): Likewise.
	(mve_vrndaq_m_f<mode>): Likewise.
	(mve_vrndmq_m_f<mode>): Likewise.
	(mve_vrndnq_m_f<mode>): Likewise.
	(mve_vrndpq_m_f<mode>): Likewise.
	(mve_vrndxq_m_f<mode>): Likewise.
	(mve_vrshrnbq_n_<supf><mode>): Likewise.
	(mve_vrshrntq_n_<supf><mode>): Likewise.
	(mve_vshrnbq_n_<supf><mode>): Likewise.
	(mve_vshrntq_n_<supf><mode>): Likewise.
	(mve_vcvtmq_m_<supf><mode>): Likewise.
	(mve_vcvtpq_m_<supf><mode>): Likewise.
	(mve_vcvtnq_m_<supf><mode>): Likewise.
	(mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
	(mve_vrev16q_m_<supf>v16qi): Likewise.
	(mve_vcvtq_m_from_f_<supf><mode>): Likewise.
	(mve_vrmlaldavhq_p_<supf>v4si): Likewise.
	(mve_vrmlsldavhaq_sv4si): Likewise.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise.

gcc/config/arm/arm_mve_builtins.def

@@ -394,3 +394,111 @@ VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaxq_s, v16qi, v8hi, v4si)
 VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaq_s, v16qi, v8hi, v4si)
 VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsriq_n_s, v16qi, v8hi, v4si)
 VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsliq_n_s, v16qi, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev32q_m_u, v16qi, v8hi)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovntq_m_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovnbq_m_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovntq_m_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovnbq_m_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovltq_m_u, v16qi, v8hi)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovlbq_m_u, v16qi, v8hi)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavq_p_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrntq_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrnbq_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vrshrntq_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vrshrnbq_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrntq_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrnbq_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqrshrntq_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovuntq_m_s, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovunbq_m_s, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtq_m_from_f_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtpq_m_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtnq_m_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtmq_m_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshruntq_n_s, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndnq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndmq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndaq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_s, v16qi, v8hi)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovntq_m_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovnbq_m_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vpselq_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovntq_m_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovnbq_m_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovltq_m_s, v16qi, v8hi)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovlbq_m_s, v16qi, v8hi)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavxq_p_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavq_p_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavxq_p_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavq_p_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmvq_p_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmavq_p_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmaq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmvq_p_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmavq_p_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmaq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vdupq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_from_f_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtpq_m_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtnq_m_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtmq_m_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vabsq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaxq_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaq_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlaldavaxq_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlaldavaq_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmsq_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmasq_n_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmaq_n_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmaq_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_IMM, vshrntq_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_IMM, vshrnbq_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_IMM, vrshrntq_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_IMM, vrshrnbq_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrntq_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vorrq_m_n_s, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vmvnq_m_n_s, v8hi, v4si)
+VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si)
+VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi)
+VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhxq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhxq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_f, v8hf)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev16q_m_s, v16qi)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f32_f16, v4sf)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f16_f32, v8hf)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f32_f16, v4sf)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f16_f32, v8hf)
+VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si)

gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vabsq_m_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabst.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vabsq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vabsq_m_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabst.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vabsq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vaddlvaq_p_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vaddlvat.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vaddlvaq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vaddlvat.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vaddlvaq_p_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vaddlvat.u32"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vaddlvaq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vaddlvat.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq_rot180_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq_rot180 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq_rot180_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq_rot180 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq_rot270_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq_rot270 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq_rot270_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq_rot270 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq_rot90_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vcmlaq_rot90 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq_rot90_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vcmlaq_rot90 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vcmla.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpeqq_m_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpeqq_m_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpgtq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpleq_m_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpleq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpleq_m_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpleq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpleq_m_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpleq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpleq_m_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpleq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpltq_m_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpltq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpltq_m_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpltq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpltq_m_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpltq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpltq_m_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpltq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpneq_m_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmpneq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpneq_m_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmpneq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpneq_m_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
+
+mve_pred16_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vcmpneq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpneq_m_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
+
+mve_pred16_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vcmpneq_m_n (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcvtbq_m_f16_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtbt.f16.f32"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcvtbq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtbq_m_f32_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtbt.f32.f16"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtbq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtmq_m_s16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.s16.f16"  }  } */
+
+int16x8_t
+foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtmq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtmq_m_s32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.s32.f32"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtmq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtmq_m_u16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.u16.f16"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtmq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtmq_m_u32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.u32.f32"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtmq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtnq_m_s16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.s16.f16"  }  } */
+
+int16x8_t
+foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtnq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtnq_m_s32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.s32.f32"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtnq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtnq_m_u16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.u16.f16"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtnq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtnq_m_u32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.u32.f32"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtnq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtpq_m_s16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.s16.f16"  }  } */
+
+int16x8_t
+foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtpq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtpq_m_s32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.s32.f32"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtpq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtpq_m_u16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.u16.f16"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtpq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtpq_m_u32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.u32.f32"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtpq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m_s16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+
+int16x8_t
+foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m_s32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m_u16_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m_u32_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcvttq_m_f16_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvttt.f16.f32"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcvttq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvttq_m_f32_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvttt.f32.f16"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvttq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16_t a, mve_pred16_t p)
+{
+  return vdupq_m_n_f16 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vdupt.16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16_t a, mve_pred16_t p)
+{
+  return vdupq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32_t a, mve_pred16_t p)
+{
+  return vdupq_m_n_f32 (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vdupt.32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32_t a, mve_pred16_t p)
+{
+  return vdupq_m (inactive, a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vfmaq_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vfmaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vfmaq_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vfmaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16_t c)
+{
+  return vfmaq_n_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16_t c)
+{
+  return vfmaq_n (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32_t c)
+{
+  return vfmaq_n_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32_t c)
+{
+  return vfmaq_n (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfma.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16_t c)
+{
+  return vfmasq_n_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfmas.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16_t c)
+{
+  return vfmasq_n (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfmas.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32_t c)
+{
+  return vfmasq_n_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfmas.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32_t c)
+{
+  return vfmasq_n (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfmas.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vfmsq_f16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfms.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+{
+  return vfmsq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfms.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vfmsq_f32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfms.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vfmsq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vfms.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmaq_m_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxnmat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmaq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmaq_m_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxnmat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmaq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16_t
+foo (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmavq_p_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmavt.f16"  }  } */
+
+float16_t
+foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmavt.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32_t
+foo (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmavq_p_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmavt.f32"  }  } */
+
+float32_t
+foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmavt.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16_t
+foo (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmvq_p_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmvt.f16"  }  } */
+
+float16_t
+foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmvq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmvt.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32_t
+foo (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmvq_p_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmvt.f32"  }  } */
+
+float32_t
+foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmvq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmaxnmvt.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmaq_m_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vminnmat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmaq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmaq_m_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vminnmat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmaq_m (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16_t
+foo (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmavq_p_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmavt.f16"  }  } */
+
+float16_t
+foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmavt.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32_t
+foo (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmavq_p_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmavt.f32"  }  } */
+
+float32_t
+foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmavt.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16_t
+foo (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmvq_p_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmvt.f16"  }  } */
+
+float16_t
+foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmvq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmvt.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32_t
+foo (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmvq_p_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmvt.f32"  }  } */
+
+float32_t
+foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmvq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vminnmvt.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlaldavaq_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlaldavaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlaldavaq_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlaldavaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint16x8_t b, uint16x8_t c)
+{
+  return vmlaldavaq_u16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.u16"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint16x8_t b, uint16x8_t c)
+{
+  return vmlaldavaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint32x4_t b, uint32x4_t c)
+{
+  return vmlaldavaq_u32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.u32"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
+{
+  return vmlaldavaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldava.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlaldavaxq_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldavax.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlaldavaxq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldavax.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlaldavaxq_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldavax.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlaldavaxq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlaldavax.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.s16"  }  } */
+
+int64_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.s32"  }  } */
+
+int64_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.u16"  }  } */
+
+uint64_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.u32"  }  } */
+
+uint64_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vmlaldavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavt.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlaldavxq_p_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavxt.s16"  }  } */
+
+int64_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlaldavxq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavxt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vmlaldavxq_p_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavxt.s32"  }  } */
+
+int64_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vmlaldavxq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavxt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlsldavaq_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldava.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlsldavaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldava.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlsldavaq_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldava.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlsldavaq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldava.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlsldavaxq_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldavax.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c)
+{
+  return vmlsldavaxq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldavax.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlsldavaxq_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldavax.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c)
+{
+  return vmlsldavaxq (a, b, c);
+}
+
+/* { dg-final { scan-assembler "vmlsldavax.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlsldavq_p_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavt.s16"  }  } */
+
+int64_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlsldavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vmlsldavq_p_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavt.s32"  }  } */
+
+int64_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vmlsldavq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlsldavxq_p_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavxt.s16"  }  } */
+
+int64_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vmlsldavxq_p (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavxt.s16"  }  } */