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riscv-gcc-1
Commit d8f52b02 by Dwarakanath Rajagopal Committed by Dwarakanath Rajagopal
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invoke.texi: Fix typo, 'AMD Family 10h core' instead of 'AMD Family 10 core'. 

2007-05-01  Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>

        * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
	'AMD Family 10 core'.

From-SVN: r124341
parent 9369ed95
Showing with 6 additions and 1 deletions
gcc/ChangeLog
2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
'AMD Family 10 core'.
2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
and athlon64-sse3 as improved versions of k8, opteron and athlon64
with SSE3 instruction set support.
......
gcc/doc/invoke.texi
......@@ -9894,7 +9894,7 @@ MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
@item k8-sse3, opteron-sse3, athlon64-sse3
Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
@item amdfam10, barcelona
AMD Family 10 core based CPUs with x86-64 instruction set support. (This
AMD Family 10h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit
instruction set extensions.)
@item winchip-c6
......
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