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Commit d839f53b by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: New attributes for load/store: "sign_extend", "update" and "indexed" 

The new attributes replace the instruction types *_ext*, *_u, *_ux.

This simplifies all code that does not care about the addressing modes,
putting the burden on the code that does care (mostly the scheduling
descriptions for certain CPUs).

It fixes a few minor bugs in the process.

The "update" and "indexed" attributes are automatic for any insn that
has a MEM as operand 0 or 1.  Other insns have to set it manually, if
they do not like the default (which is "no").  Insns that are type
load/store/fpload/fpstore but have fewer than two operands need to set
it too, or the compiler will crash.  There are very few of those.

This tries not to change semantics anywhere; in particular, the string
and multiple instructions set both "update" and "indexed" (although
they are neither).

From-SVN: r210190
parent d3b4df0b
Showing with 456 additions and 249 deletions
gcc/ChangeLog
2014-05-07 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md (indexed_address_mem): New.
* config/rs6000/rs6000.md (type): Remove load_ext, load_ext_u,
load_ext_ux, load_ux, load_u, store_ux, store_u, fpload_ux, fpload_u,
fpstore_ux, fpstore_u.
(sign_extend, indexed, update): New.
(cell_micro): Adjust.
(*zero_extend<mode>di2_internal1, *zero_extendsidi2_lfiwzx,
*extendsidi2_lfiwax, *extendsidi2_nocell, *extendsfdf2_fpr,
*movsi_internal1, *movsi_internal1_single, *movhi_internal,
*movqi_internal, *movcc_internal1, mov<mode>_hardfloat,
*mov<mode>_softfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
*mov<mode>_softfloat64, *movdi_internal32, *movdi_internal64,
*mov<mode>_string, *ldmsi8, *ldmsi7, *ldmsi6, *ldmsi5, *ldmsi4,
*ldmsi3, *stmsi8, *stmsi7, *stmsi6, *stmsi5, *stmsi4, *stmsi3,
*movdi_update1, movdi_<mode>_update, movdi_<mode>_update_stack,
*movsi_update1, *movsi_update2, movsi_update, movsi_update_stack,
*movhi_update1, *movhi_update2, *movhi_update3, *movhi_update4,
*movqi_update1, *movqi_update2, *movqi_update3, *movsf_update1,
*movsf_update2, *movsf_update3, *movsf_update4, *movdf_update1,
*movdf_update2, load_toc_aix_si, load_toc_aix_di, probe_stack_<mode>,
*stmw, *lmw, as well as 10 anonymous patterns): Adjust.
* config/rs6000/dfp.md (movsd_store, movsd_load): Adjust.
* config/rs6000/vsx.md (*vsx_movti_32bit, *vsx_extract_<mode>_load,
*vsx_extract_<mode>_store): Adjust.
* config/rs6000/rs6000.c (rs6000_adjust_cost, is_microcoded_insn,
is_cracked_insn, insn_must_be_first_in_group,
insn_must_be_last_in_group): Adjust.
* config/rs6000/40x.md (ppc403-load, ppc403-store, ppc405-float):
Adjust.
* config/rs6000/440.md (ppc440-load, ppc440-store, ppc440-fpload,
ppc440-fpstore): Adjust.
* config/rs6000/476.md (ppc476-load, ppc476-store, ppc476-fpload,
ppc476-fpstore): Adjust.
* config/rs6000/601.md (ppc601-load, ppc601-store, ppc601-fpload,
ppc601-fpstore): Adjust.
* config/rs6000/603.md (ppc603-load, ppc603-store, ppc603-fpload):
Adjust.
* config/rs6000/6xx.md (ppc604-load, ppc604-store, ppc604-fpload):
Adjust.
* config/rs6000/7450.md (ppc7450-load, ppc7450-store, ppc7450-fpload,
ppc7450-fpstore): Adjust.
* config/rs6000/7xx.md (ppc750-load, ppc750-store): Adjust.
* config/rs6000/8540.md (ppc8540_load, ppc8540_store): Adjust.
* config/rs6000/a2.md (ppca2-load, ppca2-fp-load, ppca2-fp-store):
Adjust.
* config/rs6000/cell.md (cell-load, cell-load-ux, cell-load-ext,
cell-fpload, cell-fpload-update, cell-store, cell-store-update,
cell-fpstore, cell-fpstore-update): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_load, ppce300c3_fpload,
ppce300c3_store, ppce300c3_fpstore): Adjust.
* config/rs6000/e500mc.md (e500mc_load, e500mc_fpload, e500mc_store,
e500mc_fpstore): Adjust.
* config/rs6000/e500mc64.md (e500mc64_load, e500mc64_fpload,
e500mc64_store, e500mc64_fpstore): Adjust.
* config/rs6000/e5500.md (e5500_load, e5500_fpload, e5500_store,
e5500_fpstore): Adjust.
* config/rs6000/e6500.md (e6500_load, e6500_fpload, e6500_store,
e6500_fpstore): Adjust.
* config/rs6000/mpc.md (mpccore-load, mpccore-store, mpccore-fpload):
Adjust.
* config/rs6000/power4.md (power4-load, power4-load-ext,
power4-load-ext-update, power4-load-ext-update-indexed,
power4-load-update-indexed, power4-load-update, power4-fpload,
power4-fpload-update, power4-store, power4-store-update,
power4-store-update-indexed, power4-fpstore, power4-fpstore-update):
Adjust.
* config/rs6000/power5.md (power5-load, power5-load-ext,
power5-load-ext-update, power5-load-ext-update-indexed,
power5-load-update-indexed, power5-load-update, power5-fpload,
power5-fpload-update, power5-store, power5-store-update,
power5-store-update-indexed, power5-fpstore, power5-fpstore-update):
Adjust.
* config/rs6000/power6.md (power6-load, power6-load-ext,
power6-load-update, power6-load-update-indexed,
power6-load-ext-update, power6-load-ext-update-indexed, power6-fpload,
power6-fpload-update, power6-store, power6-store-update,
power6-store-update-indexed, power6-fpstore, power6-fpstore-update):
Adjust.
* config/rs6000/power7.md (power7-load, power7-load-ext,
power7-load-update, power7-load-update-indexed,
power7-load-ext-update, power7-load-ext-update-indexed, power7-fpload,
power7-fpload-update, power7-store, power7-store-update,
power7-store-update-indexed, power7-fpstore, power7-fpstore-update):
Adjust.
* config/rs6000/power8.md (power8-load, power8-load-update,
power8-load-ext, power8-load-ext-update, power8-fpload,
power8-fpload-update, power8-store, power8-store-update-indexed,
power8-fpstore, power8-fpstore-update): Adjust.
* config/rs6000/rs64.md (rs64a-load, rs64a-store, rs64a-fpload):
Adjust.
* config/rs6000/titan.md (titan_lsu_load, titan_lsu_fpload,
titan_lsu_store, titan_lsu_fpstore): Adjust.
* config/rs6000/xfpu.md (fp-load, fp-store): Adjust.
2014-05-07 Oleg Endo <olegendo@gcc.gnu.org> 2014-05-07 Oleg Endo <olegendo@gcc.gnu.org>
PR target/60884 PR target/60884
......
gcc/config/rs6000/40x.md
...@@ -26,13 +26,12 @@ ...@@ -26,13 +26,12 @@
;; In-order execution ;; In-order execution
;; Max issue two insns/cycle (includes one branch) ;; Max issue two insns/cycle (includes one branch)
(define_insn_reservation "ppc403-load" 2 (define_insn_reservation "ppc403-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc403,ppc405")) (eq_attr "cpu" "ppc403,ppc405"))
"iu_40x") "iu_40x")
(define_insn_reservation "ppc403-store" 2 (define_insn_reservation "ppc403-store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc403,ppc405")) (eq_attr "cpu" "ppc403,ppc405"))
"iu_40x") "iu_40x")
...@@ -114,7 +113,6 @@ ...@@ -114,7 +113,6 @@
"bpu_40x") "bpu_40x")
(define_insn_reservation "ppc405-float" 11 (define_insn_reservation "ppc405-float" 11
(and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,\ (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv")
fpcompare,fp,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405")) (eq_attr "cpu" "ppc405"))
"fpu_405*10") "fpu_405*10")
gcc/config/rs6000/440.md
...@@ -33,23 +33,22 @@ ...@@ -33,23 +33,22 @@
(define_insn_reservation "ppc440-load" 3 (define_insn_reservation "ppc440-load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-store" 3 (define_insn_reservation "ppc440-store" 3
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpload" 4 (define_insn_reservation "ppc440-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpstore" 3 (define_insn_reservation "ppc440-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
......
gcc/config/rs6000/476.md
...@@ -39,26 +39,25 @@ ...@@ -39,26 +39,25 @@
(define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2") (define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2")
(define_insn_reservation "ppc476-load" 4 (define_insn_reservation "ppc476-load" 4
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
(define_insn_reservation "ppc476-store" 4 (define_insn_reservation "ppc476-store" 4
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpload" 4 (define_insn_reservation "ppc476-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpstore" 4 (define_insn_reservation "ppc476-fpstore" 4
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
......
gcc/config/rs6000/601.md
...@@ -25,23 +25,22 @@ ...@@ -25,23 +25,22 @@
;; PPC601 32-bit IU, FPU, BPU ;; PPC601 32-bit IU, FPU, BPU
(define_insn_reservation "ppc601-load" 2 (define_insn_reservation "ppc601-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601") "iu_ppc601")
(define_insn_reservation "ppc601-store" 2 (define_insn_reservation "ppc601-store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601") "iu_ppc601")
(define_insn_reservation "ppc601-fpload" 3 (define_insn_reservation "ppc601-fpload" 3
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601") "iu_ppc601")
(define_insn_reservation "ppc601-fpstore" 3 (define_insn_reservation "ppc601-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601+fpu_ppc601") "iu_ppc601+fpu_ppc601")
......
gcc/config/rs6000/603.md
...@@ -38,17 +38,17 @@ ...@@ -38,17 +38,17 @@
;; CR insns get executed in the SRU. Not modelled. ;; CR insns get executed in the SRU. Not modelled.
(define_insn_reservation "ppc603-load" 2 (define_insn_reservation "ppc603-load" 2
(and (eq_attr "type" "load,load_ext,load_ux,load_u,load_l") (and (eq_attr "type" "load,load_l")
(eq_attr "cpu" "ppc603")) (eq_attr "cpu" "ppc603"))
"lsu_603") "lsu_603")
(define_insn_reservation "ppc603-store" 2 (define_insn_reservation "ppc603-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc603")) (eq_attr "cpu" "ppc603"))
"lsu_603*2") "lsu_603*2")
(define_insn_reservation "ppc603-fpload" 2 (define_insn_reservation "ppc603-fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc603")) (eq_attr "cpu" "ppc603"))
"lsu_603") "lsu_603")
......
gcc/config/rs6000/6xx.md
...@@ -48,17 +48,17 @@ ...@@ -48,17 +48,17 @@
;; Four insns can be dispatched per cycle. ;; Four insns can be dispatched per cycle.
(define_insn_reservation "ppc604-load" 2 (define_insn_reservation "ppc604-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
(define_insn_reservation "ppc604-fpload" 3 (define_insn_reservation "ppc604-fpload" 3
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
(define_insn_reservation "ppc604-store" 3 (define_insn_reservation "ppc604-store" 3
(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
......
gcc/config/rs6000/7450.md
...@@ -43,23 +43,22 @@ ...@@ -43,23 +43,22 @@
(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450") (define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
(define_insn_reservation "ppc7450-load" 3 (define_insn_reservation "ppc7450-load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\ (and (eq_attr "type" "load,vecload")
load_ux,load_u,vecload")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450") "ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-store" 3 (define_insn_reservation "ppc7450-store" 3
(and (eq_attr "type" "store,store_ux,store_u,vecstore") (and (eq_attr "type" "store,vecstore")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450") "ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpload" 4 (define_insn_reservation "ppc7450-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450") "ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpstore" 3 (define_insn_reservation "ppc7450-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450*3") "ppc7450_du,lsu_7450*3")
......
gcc/config/rs6000/7xx.md
...@@ -46,15 +46,12 @@ ...@@ -46,15 +46,12 @@
(define_reservation "ppc7400_vec_du" "vdu_7xx") (define_reservation "ppc7400_vec_du" "vdu_7xx")
(define_insn_reservation "ppc750-load" 2 (define_insn_reservation "ppc750-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\ (and (eq_attr "type" "load,fpload,vecload,load_l")
load_ux,load_u,fpload,fpload_ux,fpload_u,\
vecload,load_l")
(eq_attr "cpu" "ppc750,ppc7400")) (eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx") "ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-store" 2 (define_insn_reservation "ppc750-store" 2
(and (eq_attr "type" "store,store_ux,store_u,\ (and (eq_attr "type" "store,fpstore,vecstore")
fpstore,fpstore_ux,fpstore_u,vecstore")
(eq_attr "cpu" "ppc750,ppc7400")) (eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx") "ppc750_du,lsu_7xx")
......
gcc/config/rs6000/8540.md
...@@ -152,14 +152,13 @@ ...@@ -152,14 +152,13 @@
;; Loads ;; Loads
(define_insn_reservation "ppc8540_load" 3 (define_insn_reservation "ppc8540_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppc8540,ppc8548")) (eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Stores. ;; Stores.
(define_insn_reservation "ppc8540_store" 3 (define_insn_reservation "ppc8540_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppc8540,ppc8548")) (eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
......
gcc/config/rs6000/a2.md
...@@ -71,7 +71,7 @@ ...@@ -71,7 +71,7 @@
;; D.4.13 ;; D.4.13
(define_insn_reservation "ppca2-load" 5 (define_insn_reservation "ppca2-load" 5
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "cpu" "ppca2")) (eq_attr "cpu" "ppca2"))
"nothing") "nothing")
...@@ -83,13 +83,13 @@ ...@@ -83,13 +83,13 @@
;; D.8.4 ;; D.8.4
(define_insn_reservation "ppca2-fp-load" 6 (define_insn_reservation "ppca2-fp-load" 6
(and (eq_attr "type" "fpload,fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppca2")) (eq_attr "cpu" "ppca2"))
"axu") "axu")
;; D.8.5 ;; D.8.5
(define_insn_reservation "ppca2-fp-store" 2 (define_insn_reservation "ppca2-fp-store" 2
(and (eq_attr "type" "fpstore,fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppca2")) (eq_attr "cpu" "ppca2"))
"axu") "axu")
......
gcc/config/rs6000/cell.md
...@@ -92,32 +92,39 @@ ...@@ -92,32 +92,39 @@
;; these instr are not simulated ;; these instr are not simulated
(define_insn_reservation "cell-load" 2 (define_insn_reservation "cell-load" 2
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"slot01,lsu_cell") "slot01,lsu_cell")
;; ldux, ldu, lbzux, lbzu, hardware breaks it down to two instrs, ;; ldux, ldu, lbzux, lbzu, hardware breaks it down to two instrs,
;; if with 32bytes alignment, CMC ;; if with 32bytes alignment, CMC
(define_insn_reservation "cell-load-ux" 2 (define_insn_reservation "cell-load-ux" 2
(and (eq_attr "type" "load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"slot01,fxu_cell+lsu_cell") "slot01,fxu_cell+lsu_cell")
;; lha, lhax, lhau, lhaux, lwa, lwax, lwaux, MC, latency unknown ;; lha, lhax, lhau, lhaux, lwa, lwax, lwaux, MC, latency unknown
;; 11/7, 11/8, 11/12 ;; 11/7, 11/8, 11/12
(define_insn_reservation "cell-load-ext" 2 (define_insn_reservation "cell-load-ext" 2
(and (eq_attr "type" "load_ext,load_ext_u,load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "cpu" "cell")) (eq_attr "sign_extend" "yes")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell+lsu_cell") "slot01,fxu_cell+lsu_cell")
;;lfs,lfsx,lfd,lfdx, 1 cycle ;;lfs,lfsx,lfd,lfdx, 1 cycle
(define_insn_reservation "cell-fpload" 1 (define_insn_reservation "cell-fpload" 1
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"vsu2_cell+lsu_cell+slot01") "vsu2_cell+lsu_cell+slot01")
;; lfsu,lfsux,lfdu,lfdux 1cycle(fpr) 2 cycle(gpr) ;; lfsu,lfsux,lfdu,lfdux 1cycle(fpr) 2 cycle(gpr)
(define_insn_reservation "cell-fpload-update" 1 (define_insn_reservation "cell-fpload-update" 1
(and (eq_attr "type" "fpload,fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"fxu_cell+vsu2_cell+lsu_cell+slot01") "fxu_cell+vsu2_cell+lsu_cell+slot01")
...@@ -129,22 +136,26 @@ ...@@ -129,22 +136,26 @@
;;st? stw(MC) ;;st? stw(MC)
(define_insn_reservation "cell-store" 1 (define_insn_reservation "cell-store" 1
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"lsu_cell+slot01") "lsu_cell+slot01")
;;stdux, stdu, (hardware breaks into store and add) 2 for update reg ;;stdux, stdu, (hardware breaks into store and add) 2 for update reg
(define_insn_reservation "cell-store-update" 1 (define_insn_reservation "cell-store-update" 1
(and (eq_attr "type" "store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"fxu_cell+lsu_cell+slot01") "fxu_cell+lsu_cell+slot01")
(define_insn_reservation "cell-fpstore" 1 (define_insn_reservation "cell-fpstore" 1
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"vsu2_cell+lsu_cell+slot01") "vsu2_cell+lsu_cell+slot01")
(define_insn_reservation "cell-fpstore-update" 1 (define_insn_reservation "cell-fpstore-update" 1
(and (eq_attr "type" "fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"vsu2_cell+fxu_cell+lsu_cell+slot01") "vsu2_cell+fxu_cell+lsu_cell+slot01")
......
gcc/config/rs6000/dfp.md
...@@ -37,14 +37,7 @@ ...@@ -37,14 +37,7 @@
|| gpc_reg_operand (operands[1], SDmode)) || gpc_reg_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS" && TARGET_HARD_FLOAT && TARGET_FPRS"
"stfd%U0%X0 %1,%0" "stfd%U0%X0 %1,%0"
[(set (attr "type") [(set_attr "type" "fpstore")
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore"))))
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "movsd_load" (define_insn "movsd_load"
...@@ -55,14 +48,7 @@ ...@@ -55,14 +48,7 @@
|| gpc_reg_operand (operands[1], DDmode)) || gpc_reg_operand (operands[1], DDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS" && TARGET_HARD_FLOAT && TARGET_FPRS"
"lfd%U1%X1 %0,%1" "lfd%U1%X1 %0,%1"
[(set (attr "type") [(set_attr "type" "fpload")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload"))))
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Hardware support for decimal floating point operations. ;; Hardware support for decimal floating point operations.
......
gcc/config/rs6000/e300c2c3.md
...@@ -168,22 +168,22 @@ ...@@ -168,22 +168,22 @@
;; Loads ;; Loads
(define_insn_reservation "ppce300c3_load" 2 (define_insn_reservation "ppce300c3_load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpload" 2 (define_insn_reservation "ppce300c3_fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce300c3")) (eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
;; Stores. ;; Stores.
(define_insn_reservation "ppce300c3_store" 2 (define_insn_reservation "ppce300c3_store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpstore" 2 (define_insn_reservation "ppce300c3_fpstore" 2
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce300c3")) (eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
gcc/config/rs6000/e500mc.md
...@@ -141,24 +141,23 @@ ...@@ -141,24 +141,23 @@
;; Loads. ;; Loads.
(define_insn_reservation "e500mc_load" 3 (define_insn_reservation "e500mc_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpload" 4 (define_insn_reservation "e500mc_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
;; Stores. ;; Stores.
(define_insn_reservation "e500mc_store" 3 (define_insn_reservation "e500mc_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpstore" 3 (define_insn_reservation "e500mc_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
......
gcc/config/rs6000/e500mc64.md
...@@ -149,24 +149,23 @@ ...@@ -149,24 +149,23 @@
;; Loads. ;; Loads.
(define_insn_reservation "e500mc64_load" 3 (define_insn_reservation "e500mc64_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpload" 4 (define_insn_reservation "e500mc64_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
;; Stores. ;; Stores.
(define_insn_reservation "e500mc64_store" 3 (define_insn_reservation "e500mc64_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpstore" 3 (define_insn_reservation "e500mc64_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
......
gcc/config/rs6000/e5500.md
...@@ -126,24 +126,23 @@ ...@@ -126,24 +126,23 @@
;; LSU - Loads. ;; LSU - Loads.
(define_insn_reservation "e5500_load" 3 (define_insn_reservation "e5500_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpload" 4 (define_insn_reservation "e5500_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
;; LSU - Stores. ;; LSU - Stores.
(define_insn_reservation "e5500_store" 3 (define_insn_reservation "e5500_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpstore" 3 (define_insn_reservation "e5500_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
......
gcc/config/rs6000/e6500.md
...@@ -129,13 +129,12 @@ ...@@ -129,13 +129,12 @@
;; LSU - Loads. ;; LSU - Loads.
(define_insn_reservation "e6500_load" 3 (define_insn_reservation "e6500_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_fpload" 4 (define_insn_reservation "e6500_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
...@@ -146,12 +145,12 @@ ...@@ -146,12 +145,12 @@
;; LSU - Stores. ;; LSU - Stores.
(define_insn_reservation "e6500_store" 3 (define_insn_reservation "e6500_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_fpstore" 3 (define_insn_reservation "e6500_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
......
gcc/config/rs6000/mpc.md
...@@ -26,18 +26,17 @@ ...@@ -26,18 +26,17 @@
;; 505/801/821/823 ;; 505/801/821/823
(define_insn_reservation "mpccore-load" 2 (define_insn_reservation "mpccore-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
(define_insn_reservation "mpccore-store" 2 (define_insn_reservation "mpccore-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
(define_insn_reservation "mpccore-fpload" 2 (define_insn_reservation "mpccore-fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
......
gcc/config/rs6000/power4.md
...@@ -77,11 +77,15 @@ ...@@ -77,11 +77,15 @@
; Load/store ; Load/store
(define_insn_reservation "power4-load" 4 ; 3 (define_insn_reservation "power4-load" 4 ; 3
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsq_power4") "lsq_power4")
(define_insn_reservation "power4-load-ext" 5 (define_insn_reservation "power4-load-ext" 5
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,lsu1_power4\ "(du1_power4+du2_power4,lsu1_power4\
|du2_power4+du3_power4,lsu2_power4\ |du2_power4+du3_power4,lsu2_power4\
...@@ -90,35 +94,49 @@ ...@@ -90,35 +94,49 @@
(iu2_power4|iu1_power4)") (iu2_power4|iu1_power4)")
(define_insn_reservation "power4-load-ext-update" 5 (define_insn_reservation "power4-load-ext-update" 5
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
lsu1_power4+iu2_power4,nothing,nothing,iu2_power4") lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-ext-update-indexed" 5 (define_insn_reservation "power4-load-ext-update-indexed" 5
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4") iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-update-indexed" 3 (define_insn_reservation "power4-load-update-indexed" 3
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4") iu1_power4,lsu2_power4+iu2_power4")
(define_insn_reservation "power4-load-update" 4 ; 3 (define_insn_reservation "power4-load-update" 4 ; 3
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsuq_power4") "lsuq_power4")
(define_insn_reservation "power4-fpload" 6 ; 5 (define_insn_reservation "power4-fpload" 6 ; 5
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsq_power4") "lsq_power4")
(define_insn_reservation "power4-fpload-update" 6 ; 5 (define_insn_reservation "power4-fpload-update" 6 ; 5
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsuq_power4") "lsuq_power4")
...@@ -129,6 +147,7 @@ ...@@ -129,6 +147,7 @@
(define_insn_reservation "power4-store" 12 (define_insn_reservation "power4-store" 12
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4,lsu1_power4)\ "((du1_power4,lsu1_power4)\
|(du2_power4,lsu2_power4)\ |(du2_power4,lsu2_power4)\
...@@ -137,7 +156,9 @@ ...@@ -137,7 +156,9 @@
(iu1_power4|iu2_power4)") (iu1_power4|iu2_power4)")
(define_insn_reservation "power4-store-update" 12 (define_insn_reservation "power4-store-update" 12
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4+du2_power4,lsu1_power4)\ "((du1_power4+du2_power4,lsu1_power4)\
|(du2_power4+du3_power4,lsu2_power4)\ |(du2_power4+du3_power4,lsu2_power4)\
...@@ -147,13 +168,16 @@ ...@@ -147,13 +168,16 @@
|(nothing,iu2_power4,iu1_power4))") |(nothing,iu2_power4,iu1_power4))")
(define_insn_reservation "power4-store-update-indexed" 12 (define_insn_reservation "power4-store-update-indexed" 12
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4,iu2_power4") iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
(define_insn_reservation "power4-fpstore" 12 (define_insn_reservation "power4-fpstore" 12
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4,lsu1_power4)\ "((du1_power4,lsu1_power4)\
|(du2_power4,lsu2_power4)\ |(du2_power4,lsu2_power4)\
...@@ -162,7 +186,8 @@ ...@@ -162,7 +186,8 @@
(fpu1_power4|fpu2_power4)") (fpu1_power4|fpu2_power4)")
(define_insn_reservation "power4-fpstore-update" 12 (define_insn_reservation "power4-fpstore-update" 12
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4+du2_power4,lsu1_power4)\ "((du1_power4+du2_power4,lsu1_power4)\
|(du2_power4+du3_power4,lsu2_power4)\ |(du2_power4+du3_power4,lsu2_power4)\
......
gcc/config/rs6000/power5.md
...@@ -57,49 +57,68 @@ ...@@ -57,49 +57,68 @@
; Load/store ; Load/store
(define_insn_reservation "power5-load" 4 ; 3 (define_insn_reservation "power5-load" 4 ; 3
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"lsq_power5") "lsq_power5")
(define_insn_reservation "power5-load-ext" 5 (define_insn_reservation "power5-load-ext" 5
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-ext-update" 5 (define_insn_reservation "power5-load-ext-update" 5
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-ext-update-indexed" 5 (define_insn_reservation "power5-load-ext-update-indexed" 5
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-update-indexed" 3 (define_insn_reservation "power5-load-update-indexed" 3
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5") iu1_power5,lsu2_power5+iu2_power5")
(define_insn_reservation "power5-load-update" 4 ; 3 (define_insn_reservation "power5-load-update" 4 ; 3
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5")
(define_insn_reservation "power5-fpload" 6 ; 5 (define_insn_reservation "power5-fpload" 6 ; 5
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"lsq_power5") "lsq_power5")
(define_insn_reservation "power5-fpload-update" 6 ; 5 (define_insn_reservation "power5-fpload-update" 6 ; 5
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5")
(define_insn_reservation "power5-store" 12 (define_insn_reservation "power5-store" 12
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"((du1_power5,lsu1_power5)\ "((du1_power5,lsu1_power5)\
|(du2_power5,lsu2_power5)\ |(du2_power5,lsu2_power5)\
...@@ -108,18 +127,23 @@ ...@@ -108,18 +127,23 @@
(iu1_power5|iu2_power5)") (iu1_power5|iu2_power5)")
(define_insn_reservation "power5-store-update" 12 (define_insn_reservation "power5-store-update" 12
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
(define_insn_reservation "power5-store-update-indexed" 12 (define_insn_reservation "power5-store-update-indexed" 12
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5,iu2_power5") iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
(define_insn_reservation "power5-fpstore" 12 (define_insn_reservation "power5-fpstore" 12
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"((du1_power5,lsu1_power5)\ "((du1_power5,lsu1_power5)\
|(du2_power5,lsu2_power5)\ |(du2_power5,lsu2_power5)\
...@@ -128,7 +152,8 @@ ...@@ -128,7 +152,8 @@
(fpu1_power5|fpu2_power5)") (fpu1_power5|fpu2_power5)")
(define_insn_reservation "power5-fpstore-update" 12 (define_insn_reservation "power5-fpstore-update" 12
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
......
gcc/config/rs6000/power6.md
...@@ -92,6 +92,8 @@ ...@@ -92,6 +92,8 @@
; that is read/written by a subsequent fixed point op. ; that is read/written by a subsequent fixed point op.
(define_insn_reservation "power6-load" 2 ; fx (define_insn_reservation "power6-load" 2 ; fx
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
...@@ -109,7 +111,9 @@ ...@@ -109,7 +111,9 @@
"store_data_bypass_p") "store_data_bypass_p")
(define_insn_reservation "power6-load-ext" 4 ; fx (define_insn_reservation "power6-load-ext" 4 ; fx
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
...@@ -127,57 +131,78 @@ ...@@ -127,57 +131,78 @@
"store_data_bypass_p") "store_data_bypass_p")
(define_insn_reservation "power6-load-update" 2 ; fx (define_insn_reservation "power6-load-update" 2 ; fx
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-load-update-indexed" 2 ; fx (define_insn_reservation "power6-load-update-indexed" 2 ; fx
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-load-ext-update" 4 ; fx (define_insn_reservation "power6-load-ext-update" 4 ; fx
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-fpload" 1 (define_insn_reservation "power6-fpload" 1
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
(define_insn_reservation "power6-fpload-update" 1 (define_insn_reservation "power6-fpload-update" 1
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-store" 14 (define_insn_reservation "power6-store" 14
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
(define_insn_reservation "power6-store-update" 14 (define_insn_reservation "power6-store-update" 14
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-store-update-indexed" 14 (define_insn_reservation "power6-store-update-indexed" 14
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LX2_power6") "LX2_power6")
(define_insn_reservation "power6-fpstore" 14 (define_insn_reservation "power6-fpstore" 14
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSF_power6") "LSF_power6")
(define_insn_reservation "power6-fpstore-update" 14 (define_insn_reservation "power6-fpstore-update" 14
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"XLF_power6") "XLF_power6")
......
gcc/config/rs6000/power7.md
...@@ -58,66 +58,91 @@ ...@@ -58,66 +58,91 @@
; LS Unit ; LS Unit
(define_insn_reservation "power7-load" 2 (define_insn_reservation "power7-load" 2
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7") "DU_power7,LSU_power7")
(define_insn_reservation "power7-load-ext" 3 (define_insn_reservation "power7-load-ext" 3
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7,FXU_power7") "DU2F_power7,LSU_power7,FXU_power7")
(define_insn_reservation "power7-load-update" 2 (define_insn_reservation "power7-load-update" 2
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7") "DU2F_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-load-update-indexed" 3 (define_insn_reservation "power7-load-update-indexed" 3
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU4_power7,FXU_power7,LSU_power7+FXU_power7") "DU4_power7,FXU_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-load-ext-update" 4 (define_insn_reservation "power7-load-ext-update" 4
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7,FXU_power7") "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-load-ext-update-indexed" 4 (define_insn_reservation "power7-load-ext-update-indexed" 4
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7") "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-fpload" 3 (define_insn_reservation "power7-fpload" 3
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7") "DU_power7,LSU_power7")
(define_insn_reservation "power7-fpload-update" 3 (define_insn_reservation "power7-fpload-update" 3
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7") "DU2F_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-store" 6 ; store-forwarding latency (define_insn_reservation "power7-store" 6 ; store-forwarding latency
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+FXU_power7") "DU_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-store-update" 6 (define_insn_reservation "power7-store-update" 6
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7,FXU_power7") "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-store-update-indexed" 6 (define_insn_reservation "power7-store-update-indexed" 6
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU4_power7,LSU_power7+FXU_power7,FXU_power7") "DU4_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-fpstore" 6 (define_insn_reservation "power7-fpstore" 6
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+VSU_power7") "DU_power7,LSU_power7+VSU_power7")
(define_insn_reservation "power7-fpstore-update" 6 (define_insn_reservation "power7-fpstore-update" 6
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+VSU_power7+FXU_power7") "DU_power7,LSU_power7+VSU_power7+FXU_power7")
......
gcc/config/rs6000/power8.md
...@@ -80,51 +80,68 @@ ...@@ -80,51 +80,68 @@
; LS Unit ; LS Unit
(define_insn_reservation "power8-load" 3 (define_insn_reservation "power8-load" 3
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LU_or_LSU_power8") "DU_any_power8,LU_or_LSU_power8")
(define_insn_reservation "power8-load-update" 3 (define_insn_reservation "power8-load-update" 3
(and (eq_attr "type" "load_u,load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8+FXU_power8") "DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
(define_insn_reservation "power8-load-ext" 3 (define_insn_reservation "power8-load-ext" 3
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8,FXU_power8") "DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
(define_insn_reservation "power8-load-ext-update" 3 (define_insn_reservation "power8-load-ext-update" 3
(and (eq_attr "type" "load_ext_u,load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8") "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
(define_insn_reservation "power8-fpload" 5 (define_insn_reservation "power8-fpload" 5
(and (eq_attr "type" "fpload,vecload") (and (ior (eq_attr "type" "vecload")
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")))
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LU_power8") "DU_any_power8,LU_power8")
(define_insn_reservation "power8-fpload-update" 5 (define_insn_reservation "power8-fpload-update" 5
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_power8+FXU_power8") "DU_cracked_power8,LU_power8+FXU_power8")
(define_insn_reservation "power8-store" 5 ; store-forwarding latency (define_insn_reservation "power8-store" 5 ; store-forwarding latency
(and (eq_attr "type" "store,store_u") (and (eq_attr "type" "store")
(not (and (eq_attr "update" "yes")
(eq_attr "indexed" "yes")))
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+LU_power8") "DU_any_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-store-update-indexed" 5 (define_insn_reservation "power8-store-update-indexed" 5
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LSU_power8+LU_power8") "DU_cracked_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-fpstore" 5 (define_insn_reservation "power8-fpstore" 5
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8") "DU_any_power8,LSU_power8+VSU_power8")
(define_insn_reservation "power8-fpstore-update" 5 (define_insn_reservation "power8-fpstore-update" 5
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8") "DU_any_power8,LSU_power8+VSU_power8")
......
gcc/config/rs6000/predicates.md
...@@ -751,6 +751,13 @@ ...@@ -751,6 +751,13 @@
&& GET_CODE (XEXP (op, 0)) == PRE_MODIFY && GET_CODE (XEXP (op, 0)) == PRE_MODIFY
&& indexed_address (XEXP (XEXP (op, 0), 1), mode))")) && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))
;; Return 1 if the operand is a MEM with an indexed-form address.
(define_special_predicate "indexed_address_mem"
(match_test "(MEM_P (op)
&& (indexed_address (XEXP (op, 0), mode)
|| (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
&& indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
;; Used for the destination of the fix_truncdfsi2 expander. ;; Used for the destination of the fix_truncdfsi2 expander.
;; If stfiwx will be used, the result goes to memory; otherwise, ;; If stfiwx will be used, the result goes to memory; otherwise,
;; we're going to emit a store and a load of a subreg, so the dest is a ;; we're going to emit a store and a load of a subreg, so the dest is a
......
gcc/config/rs6000/rs64.md
...@@ -26,17 +26,17 @@ ...@@ -26,17 +26,17 @@
;; RS64a 64-bit IU, LSU, FPU, BPU ;; RS64a 64-bit IU, LSU, FPU, BPU
(define_insn_reservation "rs64a-load" 2 (define_insn_reservation "rs64a-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
(define_insn_reservation "rs64a-store" 2 (define_insn_reservation "rs64a-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
(define_insn_reservation "rs64a-fpload" 3 (define_insn_reservation "rs64a-fpload" 3
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
......
gcc/config/rs6000/titan.md
...@@ -95,13 +95,12 @@ ...@@ -95,13 +95,12 @@
;; Loads. ;; Loads.
(define_insn_reservation "titan_lsu_load" 3 (define_insn_reservation "titan_lsu_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
(define_insn_reservation "titan_lsu_fpload" 12 (define_insn_reservation "titan_lsu_fpload" 12
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
...@@ -115,12 +114,12 @@ ...@@ -115,12 +114,12 @@
;; Stores. ;; Stores.
(define_insn_reservation "titan_lsu_store" 12 (define_insn_reservation "titan_lsu_store" 12
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
(define_insn_reservation "titan_lsu_fpstore" 12 (define_insn_reservation "titan_lsu_fpstore" 12
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
......
gcc/config/rs6000/vsx.md
...@@ -657,8 +657,9 @@ ...@@ -657,8 +657,9 @@
gcc_unreachable (); gcc_unreachable ();
} }
} }
[(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store_ux,store_ux,load_ux,load_ux, *, *") [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,store,load,load, *, *")
(set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16") (set_attr "update" " *, *, *, *, *, *, *, yes, yes, yes, yes, *, *")
(set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16")
(set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
(const_string "always") (const_string "always")
(const_string "conditional")))]) (const_string "conditional")))])
...@@ -1613,22 +1614,7 @@ ...@@ -1613,22 +1614,7 @@
lfd%U1%X1 %0,%1 lfd%U1%X1 %0,%1
lxsd%U1x %x0,%y1 lxsd%U1x %x0,%y1
ld%U1%X1 %0,%1" ld%U1%X1 %0,%1"
[(set_attr_alternative "type" [(set_attr "type" "fpload,fpload,load")
[(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(const_string "fpload")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))])
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Optimize storing a single scalar element that is the right location to ;; Optimize storing a single scalar element that is the right location to
...@@ -1643,16 +1629,7 @@ ...@@ -1643,16 +1629,7 @@
stfd%U0%X0 %1,%0 stfd%U0%X0 %1,%0
stxsd%U0x %x1,%y0 stxsd%U0x %x1,%y0
stxsd%U0x %x1,%y0" stxsd%U0x %x1,%y0"
[(set_attr_alternative "type" [(set_attr "type" "fpstore")
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(const_string "fpstore")
(const_string "fpstore")])
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Extract a SF element from V4SF ;; Extract a SF element from V4SF
......
gcc/config/rs6000/xfpu.md
...@@ -118,12 +118,12 @@ ...@@ -118,12 +118,12 @@
"Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub") "Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
(define_insn_reservation "fp-load" 10 ;; FIXME. Is double/single precision the same ? (define_insn_reservation "fp-load" 10 ;; FIXME. Is double/single precision the same ?
(and (eq_attr "type" "fpload, fpload_ux, fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc405")) (eq_attr "cpu" "ppc405"))
"Xfpu_issue*10") "Xfpu_issue*10")
(define_insn_reservation "fp-store" 4 (define_insn_reservation "fp-store" 4
(and (eq_attr "type" "fpstore, fpstore_ux, fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc405")) (eq_attr "cpu" "ppc405"))
"Xfpu_issue*4") "Xfpu_issue*4")
......
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