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Commit d839f53b by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: New attributes for load/store: "sign_extend", "update" and "indexed" 

The new attributes replace the instruction types *_ext*, *_u, *_ux.

This simplifies all code that does not care about the addressing modes,
putting the burden on the code that does care (mostly the scheduling
descriptions for certain CPUs).

It fixes a few minor bugs in the process.

The "update" and "indexed" attributes are automatic for any insn that
has a MEM as operand 0 or 1.  Other insns have to set it manually, if
they do not like the default (which is "no").  Insns that are type
load/store/fpload/fpstore but have fewer than two operands need to set
it too, or the compiler will crash.  There are very few of those.

This tries not to change semantics anywhere; in particular, the string
and multiple instructions set both "update" and "indexed" (although
they are neither).

From-SVN: r210190
parent d3b4df0b
Showing with 647 additions and 757 deletions
gcc/ChangeLog
2014-05-07 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md (indexed_address_mem): New.
* config/rs6000/rs6000.md (type): Remove load_ext, load_ext_u,
load_ext_ux, load_ux, load_u, store_ux, store_u, fpload_ux, fpload_u,
fpstore_ux, fpstore_u.
(sign_extend, indexed, update): New.
(cell_micro): Adjust.
(*zero_extend<mode>di2_internal1, *zero_extendsidi2_lfiwzx,
*extendsidi2_lfiwax, *extendsidi2_nocell, *extendsfdf2_fpr,
*movsi_internal1, *movsi_internal1_single, *movhi_internal,
*movqi_internal, *movcc_internal1, mov<mode>_hardfloat,
*mov<mode>_softfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
*mov<mode>_softfloat64, *movdi_internal32, *movdi_internal64,
*mov<mode>_string, *ldmsi8, *ldmsi7, *ldmsi6, *ldmsi5, *ldmsi4,
*ldmsi3, *stmsi8, *stmsi7, *stmsi6, *stmsi5, *stmsi4, *stmsi3,
*movdi_update1, movdi_<mode>_update, movdi_<mode>_update_stack,
*movsi_update1, *movsi_update2, movsi_update, movsi_update_stack,
*movhi_update1, *movhi_update2, *movhi_update3, *movhi_update4,
*movqi_update1, *movqi_update2, *movqi_update3, *movsf_update1,
*movsf_update2, *movsf_update3, *movsf_update4, *movdf_update1,
*movdf_update2, load_toc_aix_si, load_toc_aix_di, probe_stack_<mode>,
*stmw, *lmw, as well as 10 anonymous patterns): Adjust.
* config/rs6000/dfp.md (movsd_store, movsd_load): Adjust.
* config/rs6000/vsx.md (*vsx_movti_32bit, *vsx_extract_<mode>_load,
*vsx_extract_<mode>_store): Adjust.
* config/rs6000/rs6000.c (rs6000_adjust_cost, is_microcoded_insn,
is_cracked_insn, insn_must_be_first_in_group,
insn_must_be_last_in_group): Adjust.
* config/rs6000/40x.md (ppc403-load, ppc403-store, ppc405-float):
Adjust.
* config/rs6000/440.md (ppc440-load, ppc440-store, ppc440-fpload,
ppc440-fpstore): Adjust.
* config/rs6000/476.md (ppc476-load, ppc476-store, ppc476-fpload,
ppc476-fpstore): Adjust.
* config/rs6000/601.md (ppc601-load, ppc601-store, ppc601-fpload,
ppc601-fpstore): Adjust.
* config/rs6000/603.md (ppc603-load, ppc603-store, ppc603-fpload):
Adjust.
* config/rs6000/6xx.md (ppc604-load, ppc604-store, ppc604-fpload):
Adjust.
* config/rs6000/7450.md (ppc7450-load, ppc7450-store, ppc7450-fpload,
ppc7450-fpstore): Adjust.
* config/rs6000/7xx.md (ppc750-load, ppc750-store): Adjust.
* config/rs6000/8540.md (ppc8540_load, ppc8540_store): Adjust.
* config/rs6000/a2.md (ppca2-load, ppca2-fp-load, ppca2-fp-store):
Adjust.
* config/rs6000/cell.md (cell-load, cell-load-ux, cell-load-ext,
cell-fpload, cell-fpload-update, cell-store, cell-store-update,
cell-fpstore, cell-fpstore-update): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_load, ppce300c3_fpload,
ppce300c3_store, ppce300c3_fpstore): Adjust.
* config/rs6000/e500mc.md (e500mc_load, e500mc_fpload, e500mc_store,
e500mc_fpstore): Adjust.
* config/rs6000/e500mc64.md (e500mc64_load, e500mc64_fpload,
e500mc64_store, e500mc64_fpstore): Adjust.
* config/rs6000/e5500.md (e5500_load, e5500_fpload, e5500_store,
e5500_fpstore): Adjust.
* config/rs6000/e6500.md (e6500_load, e6500_fpload, e6500_store,
e6500_fpstore): Adjust.
* config/rs6000/mpc.md (mpccore-load, mpccore-store, mpccore-fpload):
Adjust.
* config/rs6000/power4.md (power4-load, power4-load-ext,
power4-load-ext-update, power4-load-ext-update-indexed,
power4-load-update-indexed, power4-load-update, power4-fpload,
power4-fpload-update, power4-store, power4-store-update,
power4-store-update-indexed, power4-fpstore, power4-fpstore-update):
Adjust.
* config/rs6000/power5.md (power5-load, power5-load-ext,
power5-load-ext-update, power5-load-ext-update-indexed,
power5-load-update-indexed, power5-load-update, power5-fpload,
power5-fpload-update, power5-store, power5-store-update,
power5-store-update-indexed, power5-fpstore, power5-fpstore-update):
Adjust.
* config/rs6000/power6.md (power6-load, power6-load-ext,
power6-load-update, power6-load-update-indexed,
power6-load-ext-update, power6-load-ext-update-indexed, power6-fpload,
power6-fpload-update, power6-store, power6-store-update,
power6-store-update-indexed, power6-fpstore, power6-fpstore-update):
Adjust.
* config/rs6000/power7.md (power7-load, power7-load-ext,
power7-load-update, power7-load-update-indexed,
power7-load-ext-update, power7-load-ext-update-indexed, power7-fpload,
power7-fpload-update, power7-store, power7-store-update,
power7-store-update-indexed, power7-fpstore, power7-fpstore-update):
Adjust.
* config/rs6000/power8.md (power8-load, power8-load-update,
power8-load-ext, power8-load-ext-update, power8-fpload,
power8-fpload-update, power8-store, power8-store-update-indexed,
power8-fpstore, power8-fpstore-update): Adjust.
* config/rs6000/rs64.md (rs64a-load, rs64a-store, rs64a-fpload):
Adjust.
* config/rs6000/titan.md (titan_lsu_load, titan_lsu_fpload,
titan_lsu_store, titan_lsu_fpstore): Adjust.
* config/rs6000/xfpu.md (fp-load, fp-store): Adjust.
2014-05-07 Oleg Endo <olegendo@gcc.gnu.org> 2014-05-07 Oleg Endo <olegendo@gcc.gnu.org>
PR target/60884 PR target/60884
......
gcc/config/rs6000/40x.md
...@@ -26,13 +26,12 @@ ...@@ -26,13 +26,12 @@
;; In-order execution ;; In-order execution
;; Max issue two insns/cycle (includes one branch) ;; Max issue two insns/cycle (includes one branch)
(define_insn_reservation "ppc403-load" 2 (define_insn_reservation "ppc403-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc403,ppc405")) (eq_attr "cpu" "ppc403,ppc405"))
"iu_40x") "iu_40x")
(define_insn_reservation "ppc403-store" 2 (define_insn_reservation "ppc403-store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc403,ppc405")) (eq_attr "cpu" "ppc403,ppc405"))
"iu_40x") "iu_40x")
...@@ -114,7 +113,6 @@ ...@@ -114,7 +113,6 @@
"bpu_40x") "bpu_40x")
(define_insn_reservation "ppc405-float" 11 (define_insn_reservation "ppc405-float" 11
(and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,\ (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv")
fpcompare,fp,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405")) (eq_attr "cpu" "ppc405"))
"fpu_405*10") "fpu_405*10")
gcc/config/rs6000/440.md
...@@ -33,23 +33,22 @@ ...@@ -33,23 +33,22 @@
(define_insn_reservation "ppc440-load" 3 (define_insn_reservation "ppc440-load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-store" 3 (define_insn_reservation "ppc440-store" 3
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpload" 4 (define_insn_reservation "ppc440-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpstore" 3 (define_insn_reservation "ppc440-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc440")) (eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe") "ppc440_issue,ppc440_l_pipe")
......
gcc/config/rs6000/476.md
...@@ -39,26 +39,25 @@ ...@@ -39,26 +39,25 @@
(define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2") (define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2")
(define_insn_reservation "ppc476-load" 4 (define_insn_reservation "ppc476-load" 4
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
(define_insn_reservation "ppc476-store" 4 (define_insn_reservation "ppc476-store" 4
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpload" 4 (define_insn_reservation "ppc476-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpstore" 4 (define_insn_reservation "ppc476-fpstore" 4
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc476")) (eq_attr "cpu" "ppc476"))
"ppc476_issue,\ "ppc476_issue,\
ppc476_lj_pipe") ppc476_lj_pipe")
......
gcc/config/rs6000/601.md
...@@ -25,23 +25,22 @@ ...@@ -25,23 +25,22 @@
;; PPC601 32-bit IU, FPU, BPU ;; PPC601 32-bit IU, FPU, BPU
(define_insn_reservation "ppc601-load" 2 (define_insn_reservation "ppc601-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601") "iu_ppc601")
(define_insn_reservation "ppc601-store" 2 (define_insn_reservation "ppc601-store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601") "iu_ppc601")
(define_insn_reservation "ppc601-fpload" 3 (define_insn_reservation "ppc601-fpload" 3
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601") "iu_ppc601")
(define_insn_reservation "ppc601-fpstore" 3 (define_insn_reservation "ppc601-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
"iu_ppc601+fpu_ppc601") "iu_ppc601+fpu_ppc601")
......
gcc/config/rs6000/603.md
...@@ -38,17 +38,17 @@ ...@@ -38,17 +38,17 @@
;; CR insns get executed in the SRU. Not modelled. ;; CR insns get executed in the SRU. Not modelled.
(define_insn_reservation "ppc603-load" 2 (define_insn_reservation "ppc603-load" 2
(and (eq_attr "type" "load,load_ext,load_ux,load_u,load_l") (and (eq_attr "type" "load,load_l")
(eq_attr "cpu" "ppc603")) (eq_attr "cpu" "ppc603"))
"lsu_603") "lsu_603")
(define_insn_reservation "ppc603-store" 2 (define_insn_reservation "ppc603-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc603")) (eq_attr "cpu" "ppc603"))
"lsu_603*2") "lsu_603*2")
(define_insn_reservation "ppc603-fpload" 2 (define_insn_reservation "ppc603-fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc603")) (eq_attr "cpu" "ppc603"))
"lsu_603") "lsu_603")
......
gcc/config/rs6000/6xx.md
...@@ -48,17 +48,17 @@ ...@@ -48,17 +48,17 @@
;; Four insns can be dispatched per cycle. ;; Four insns can be dispatched per cycle.
(define_insn_reservation "ppc604-load" 2 (define_insn_reservation "ppc604-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
(define_insn_reservation "ppc604-fpload" 3 (define_insn_reservation "ppc604-fpload" 3
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
(define_insn_reservation "ppc604-store" 3 (define_insn_reservation "ppc604-store" 3
(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx") "lsu_6xx")
......
gcc/config/rs6000/7450.md
...@@ -43,23 +43,22 @@ ...@@ -43,23 +43,22 @@
(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450") (define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
(define_insn_reservation "ppc7450-load" 3 (define_insn_reservation "ppc7450-load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\ (and (eq_attr "type" "load,vecload")
load_ux,load_u,vecload")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450") "ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-store" 3 (define_insn_reservation "ppc7450-store" 3
(and (eq_attr "type" "store,store_ux,store_u,vecstore") (and (eq_attr "type" "store,vecstore")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450") "ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpload" 4 (define_insn_reservation "ppc7450-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450") "ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpstore" 3 (define_insn_reservation "ppc7450-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc7450")) (eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450*3") "ppc7450_du,lsu_7450*3")
......
gcc/config/rs6000/7xx.md
...@@ -46,15 +46,12 @@ ...@@ -46,15 +46,12 @@
(define_reservation "ppc7400_vec_du" "vdu_7xx") (define_reservation "ppc7400_vec_du" "vdu_7xx")
(define_insn_reservation "ppc750-load" 2 (define_insn_reservation "ppc750-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\ (and (eq_attr "type" "load,fpload,vecload,load_l")
load_ux,load_u,fpload,fpload_ux,fpload_u,\
vecload,load_l")
(eq_attr "cpu" "ppc750,ppc7400")) (eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx") "ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-store" 2 (define_insn_reservation "ppc750-store" 2
(and (eq_attr "type" "store,store_ux,store_u,\ (and (eq_attr "type" "store,fpstore,vecstore")
fpstore,fpstore_ux,fpstore_u,vecstore")
(eq_attr "cpu" "ppc750,ppc7400")) (eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx") "ppc750_du,lsu_7xx")
......
gcc/config/rs6000/8540.md
...@@ -152,14 +152,13 @@ ...@@ -152,14 +152,13 @@
;; Loads ;; Loads
(define_insn_reservation "ppc8540_load" 3 (define_insn_reservation "ppc8540_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppc8540,ppc8548")) (eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Stores. ;; Stores.
(define_insn_reservation "ppc8540_store" 3 (define_insn_reservation "ppc8540_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppc8540,ppc8548")) (eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
......
gcc/config/rs6000/a2.md
...@@ -71,7 +71,7 @@ ...@@ -71,7 +71,7 @@
;; D.4.13 ;; D.4.13
(define_insn_reservation "ppca2-load" 5 (define_insn_reservation "ppca2-load" 5
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "cpu" "ppca2")) (eq_attr "cpu" "ppca2"))
"nothing") "nothing")
...@@ -83,13 +83,13 @@ ...@@ -83,13 +83,13 @@
;; D.8.4 ;; D.8.4
(define_insn_reservation "ppca2-fp-load" 6 (define_insn_reservation "ppca2-fp-load" 6
(and (eq_attr "type" "fpload,fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppca2")) (eq_attr "cpu" "ppca2"))
"axu") "axu")
;; D.8.5 ;; D.8.5
(define_insn_reservation "ppca2-fp-store" 2 (define_insn_reservation "ppca2-fp-store" 2
(and (eq_attr "type" "fpstore,fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppca2")) (eq_attr "cpu" "ppca2"))
"axu") "axu")
......
gcc/config/rs6000/cell.md
...@@ -92,32 +92,39 @@ ...@@ -92,32 +92,39 @@
;; these instr are not simulated ;; these instr are not simulated
(define_insn_reservation "cell-load" 2 (define_insn_reservation "cell-load" 2
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"slot01,lsu_cell") "slot01,lsu_cell")
;; ldux, ldu, lbzux, lbzu, hardware breaks it down to two instrs, ;; ldux, ldu, lbzux, lbzu, hardware breaks it down to two instrs,
;; if with 32bytes alignment, CMC ;; if with 32bytes alignment, CMC
(define_insn_reservation "cell-load-ux" 2 (define_insn_reservation "cell-load-ux" 2
(and (eq_attr "type" "load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"slot01,fxu_cell+lsu_cell") "slot01,fxu_cell+lsu_cell")
;; lha, lhax, lhau, lhaux, lwa, lwax, lwaux, MC, latency unknown ;; lha, lhax, lhau, lhaux, lwa, lwax, lwaux, MC, latency unknown
;; 11/7, 11/8, 11/12 ;; 11/7, 11/8, 11/12
(define_insn_reservation "cell-load-ext" 2 (define_insn_reservation "cell-load-ext" 2
(and (eq_attr "type" "load_ext,load_ext_u,load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "cpu" "cell")) (eq_attr "sign_extend" "yes")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell+lsu_cell") "slot01,fxu_cell+lsu_cell")
;;lfs,lfsx,lfd,lfdx, 1 cycle ;;lfs,lfsx,lfd,lfdx, 1 cycle
(define_insn_reservation "cell-fpload" 1 (define_insn_reservation "cell-fpload" 1
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"vsu2_cell+lsu_cell+slot01") "vsu2_cell+lsu_cell+slot01")
;; lfsu,lfsux,lfdu,lfdux 1cycle(fpr) 2 cycle(gpr) ;; lfsu,lfsux,lfdu,lfdux 1cycle(fpr) 2 cycle(gpr)
(define_insn_reservation "cell-fpload-update" 1 (define_insn_reservation "cell-fpload-update" 1
(and (eq_attr "type" "fpload,fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"fxu_cell+vsu2_cell+lsu_cell+slot01") "fxu_cell+vsu2_cell+lsu_cell+slot01")
...@@ -129,22 +136,26 @@ ...@@ -129,22 +136,26 @@
;;st? stw(MC) ;;st? stw(MC)
(define_insn_reservation "cell-store" 1 (define_insn_reservation "cell-store" 1
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"lsu_cell+slot01") "lsu_cell+slot01")
;;stdux, stdu, (hardware breaks into store and add) 2 for update reg ;;stdux, stdu, (hardware breaks into store and add) 2 for update reg
(define_insn_reservation "cell-store-update" 1 (define_insn_reservation "cell-store-update" 1
(and (eq_attr "type" "store_ux,store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"fxu_cell+lsu_cell+slot01") "fxu_cell+lsu_cell+slot01")
(define_insn_reservation "cell-fpstore" 1 (define_insn_reservation "cell-fpstore" 1
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"vsu2_cell+lsu_cell+slot01") "vsu2_cell+lsu_cell+slot01")
(define_insn_reservation "cell-fpstore-update" 1 (define_insn_reservation "cell-fpstore-update" 1
(and (eq_attr "type" "fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell")) (eq_attr "cpu" "cell"))
"vsu2_cell+fxu_cell+lsu_cell+slot01") "vsu2_cell+fxu_cell+lsu_cell+slot01")
......
gcc/config/rs6000/dfp.md
...@@ -37,14 +37,7 @@ ...@@ -37,14 +37,7 @@
|| gpc_reg_operand (operands[1], SDmode)) || gpc_reg_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS" && TARGET_HARD_FLOAT && TARGET_FPRS"
"stfd%U0%X0 %1,%0" "stfd%U0%X0 %1,%0"
[(set (attr "type") [(set_attr "type" "fpstore")
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore"))))
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "movsd_load" (define_insn "movsd_load"
...@@ -55,14 +48,7 @@ ...@@ -55,14 +48,7 @@
|| gpc_reg_operand (operands[1], DDmode)) || gpc_reg_operand (operands[1], DDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS" && TARGET_HARD_FLOAT && TARGET_FPRS"
"lfd%U1%X1 %0,%1" "lfd%U1%X1 %0,%1"
[(set (attr "type") [(set_attr "type" "fpload")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload"))))
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Hardware support for decimal floating point operations. ;; Hardware support for decimal floating point operations.
......
gcc/config/rs6000/e300c2c3.md
...@@ -168,22 +168,22 @@ ...@@ -168,22 +168,22 @@
;; Loads ;; Loads
(define_insn_reservation "ppce300c3_load" 2 (define_insn_reservation "ppce300c3_load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpload" 2 (define_insn_reservation "ppce300c3_fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce300c3")) (eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
;; Stores. ;; Stores.
(define_insn_reservation "ppce300c3_store" 2 (define_insn_reservation "ppce300c3_store" 2
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpstore" 2 (define_insn_reservation "ppce300c3_fpstore" 2
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce300c3")) (eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
gcc/config/rs6000/e500mc.md
...@@ -141,24 +141,23 @@ ...@@ -141,24 +141,23 @@
;; Loads. ;; Loads.
(define_insn_reservation "e500mc_load" 3 (define_insn_reservation "e500mc_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpload" 4 (define_insn_reservation "e500mc_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
;; Stores. ;; Stores.
(define_insn_reservation "e500mc_store" 3 (define_insn_reservation "e500mc_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpstore" 3 (define_insn_reservation "e500mc_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc")) (eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
......
gcc/config/rs6000/e500mc64.md
...@@ -149,24 +149,23 @@ ...@@ -149,24 +149,23 @@
;; Loads. ;; Loads.
(define_insn_reservation "e500mc64_load" 3 (define_insn_reservation "e500mc64_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpload" 4 (define_insn_reservation "e500mc64_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
;; Stores. ;; Stores.
(define_insn_reservation "e500mc64_store" 3 (define_insn_reservation "e500mc64_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpstore" 3 (define_insn_reservation "e500mc64_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc64")) (eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
......
gcc/config/rs6000/e5500.md
...@@ -126,24 +126,23 @@ ...@@ -126,24 +126,23 @@
;; LSU - Loads. ;; LSU - Loads.
(define_insn_reservation "e5500_load" 3 (define_insn_reservation "e5500_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpload" 4 (define_insn_reservation "e5500_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
;; LSU - Stores. ;; LSU - Stores.
(define_insn_reservation "e5500_store" 3 (define_insn_reservation "e5500_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpstore" 3 (define_insn_reservation "e5500_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce5500")) (eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu") "e5500_decode,e5500_lsu")
......
gcc/config/rs6000/e6500.md
...@@ -129,13 +129,12 @@ ...@@ -129,13 +129,12 @@
;; LSU - Loads. ;; LSU - Loads.
(define_insn_reservation "e6500_load" 3 (define_insn_reservation "e6500_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_fpload" 4 (define_insn_reservation "e6500_fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
...@@ -146,12 +145,12 @@ ...@@ -146,12 +145,12 @@
;; LSU - Stores. ;; LSU - Stores.
(define_insn_reservation "e6500_store" 3 (define_insn_reservation "e6500_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_fpstore" 3 (define_insn_reservation "e6500_fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce6500")) (eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu") "e6500_decode,e6500_lsu")
......
gcc/config/rs6000/mpc.md
...@@ -26,18 +26,17 @@ ...@@ -26,18 +26,17 @@
;; 505/801/821/823 ;; 505/801/821/823
(define_insn_reservation "mpccore-load" 2 (define_insn_reservation "mpccore-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,store_c,sync")
load_l,store_c,sync")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
(define_insn_reservation "mpccore-store" 2 (define_insn_reservation "mpccore-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
(define_insn_reservation "mpccore-fpload" 2 (define_insn_reservation "mpccore-fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
"lsu_mpc") "lsu_mpc")
......
gcc/config/rs6000/power4.md
...@@ -77,11 +77,15 @@ ...@@ -77,11 +77,15 @@
; Load/store ; Load/store
(define_insn_reservation "power4-load" 4 ; 3 (define_insn_reservation "power4-load" 4 ; 3
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsq_power4") "lsq_power4")
(define_insn_reservation "power4-load-ext" 5 (define_insn_reservation "power4-load-ext" 5
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,lsu1_power4\ "(du1_power4+du2_power4,lsu1_power4\
|du2_power4+du3_power4,lsu2_power4\ |du2_power4+du3_power4,lsu2_power4\
...@@ -90,35 +94,49 @@ ...@@ -90,35 +94,49 @@
(iu2_power4|iu1_power4)") (iu2_power4|iu1_power4)")
(define_insn_reservation "power4-load-ext-update" 5 (define_insn_reservation "power4-load-ext-update" 5
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
lsu1_power4+iu2_power4,nothing,nothing,iu2_power4") lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-ext-update-indexed" 5 (define_insn_reservation "power4-load-ext-update-indexed" 5
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4") iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-update-indexed" 3 (define_insn_reservation "power4-load-update-indexed" 3
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4") iu1_power4,lsu2_power4+iu2_power4")
(define_insn_reservation "power4-load-update" 4 ; 3 (define_insn_reservation "power4-load-update" 4 ; 3
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsuq_power4") "lsuq_power4")
(define_insn_reservation "power4-fpload" 6 ; 5 (define_insn_reservation "power4-fpload" 6 ; 5
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsq_power4") "lsq_power4")
(define_insn_reservation "power4-fpload-update" 6 ; 5 (define_insn_reservation "power4-fpload-update" 6 ; 5
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"lsuq_power4") "lsuq_power4")
...@@ -129,6 +147,7 @@ ...@@ -129,6 +147,7 @@
(define_insn_reservation "power4-store" 12 (define_insn_reservation "power4-store" 12
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4,lsu1_power4)\ "((du1_power4,lsu1_power4)\
|(du2_power4,lsu2_power4)\ |(du2_power4,lsu2_power4)\
...@@ -137,7 +156,9 @@ ...@@ -137,7 +156,9 @@
(iu1_power4|iu2_power4)") (iu1_power4|iu2_power4)")
(define_insn_reservation "power4-store-update" 12 (define_insn_reservation "power4-store-update" 12
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4+du2_power4,lsu1_power4)\ "((du1_power4+du2_power4,lsu1_power4)\
|(du2_power4+du3_power4,lsu2_power4)\ |(du2_power4+du3_power4,lsu2_power4)\
...@@ -147,13 +168,16 @@ ...@@ -147,13 +168,16 @@
|(nothing,iu2_power4,iu1_power4))") |(nothing,iu2_power4,iu1_power4))")
(define_insn_reservation "power4-store-update-indexed" 12 (define_insn_reservation "power4-store-update-indexed" 12
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\ "du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4,iu2_power4") iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
(define_insn_reservation "power4-fpstore" 12 (define_insn_reservation "power4-fpstore" 12
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4,lsu1_power4)\ "((du1_power4,lsu1_power4)\
|(du2_power4,lsu2_power4)\ |(du2_power4,lsu2_power4)\
...@@ -162,7 +186,8 @@ ...@@ -162,7 +186,8 @@
(fpu1_power4|fpu2_power4)") (fpu1_power4|fpu2_power4)")
(define_insn_reservation "power4-fpstore-update" 12 (define_insn_reservation "power4-fpstore-update" 12
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power4")) (eq_attr "cpu" "power4"))
"((du1_power4+du2_power4,lsu1_power4)\ "((du1_power4+du2_power4,lsu1_power4)\
|(du2_power4+du3_power4,lsu2_power4)\ |(du2_power4+du3_power4,lsu2_power4)\
......
gcc/config/rs6000/power5.md
...@@ -57,49 +57,68 @@ ...@@ -57,49 +57,68 @@
; Load/store ; Load/store
(define_insn_reservation "power5-load" 4 ; 3 (define_insn_reservation "power5-load" 4 ; 3
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"lsq_power5") "lsq_power5")
(define_insn_reservation "power5-load-ext" 5 (define_insn_reservation "power5-load-ext" 5
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-ext-update" 5 (define_insn_reservation "power5-load-ext-update" 5
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-ext-update-indexed" 5 (define_insn_reservation "power5-load-ext-update-indexed" 5
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-update-indexed" 3 (define_insn_reservation "power5-load-update-indexed" 3
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5") iu1_power5,lsu2_power5+iu2_power5")
(define_insn_reservation "power5-load-update" 4 ; 3 (define_insn_reservation "power5-load-update" 4 ; 3
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5")
(define_insn_reservation "power5-fpload" 6 ; 5 (define_insn_reservation "power5-fpload" 6 ; 5
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"lsq_power5") "lsq_power5")
(define_insn_reservation "power5-fpload-update" 6 ; 5 (define_insn_reservation "power5-fpload-update" 6 ; 5
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5")
(define_insn_reservation "power5-store" 12 (define_insn_reservation "power5-store" 12
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"((du1_power5,lsu1_power5)\ "((du1_power5,lsu1_power5)\
|(du2_power5,lsu2_power5)\ |(du2_power5,lsu2_power5)\
...@@ -108,18 +127,23 @@ ...@@ -108,18 +127,23 @@
(iu1_power5|iu2_power5)") (iu1_power5|iu2_power5)")
(define_insn_reservation "power5-store-update" 12 (define_insn_reservation "power5-store-update" 12
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
(define_insn_reservation "power5-store-update-indexed" 12 (define_insn_reservation "power5-store-update-indexed" 12
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\ "du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5,iu2_power5") iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
(define_insn_reservation "power5-fpstore" 12 (define_insn_reservation "power5-fpstore" 12
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"((du1_power5,lsu1_power5)\ "((du1_power5,lsu1_power5)\
|(du2_power5,lsu2_power5)\ |(du2_power5,lsu2_power5)\
...@@ -128,7 +152,8 @@ ...@@ -128,7 +152,8 @@
(fpu1_power5|fpu2_power5)") (fpu1_power5|fpu2_power5)")
(define_insn_reservation "power5-fpstore-update" 12 (define_insn_reservation "power5-fpstore-update" 12
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power5")) (eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
......
gcc/config/rs6000/power6.md
...@@ -92,6 +92,8 @@ ...@@ -92,6 +92,8 @@
; that is read/written by a subsequent fixed point op. ; that is read/written by a subsequent fixed point op.
(define_insn_reservation "power6-load" 2 ; fx (define_insn_reservation "power6-load" 2 ; fx
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
...@@ -109,7 +111,9 @@ ...@@ -109,7 +111,9 @@
"store_data_bypass_p") "store_data_bypass_p")
(define_insn_reservation "power6-load-ext" 4 ; fx (define_insn_reservation "power6-load-ext" 4 ; fx
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
...@@ -127,57 +131,78 @@ ...@@ -127,57 +131,78 @@
"store_data_bypass_p") "store_data_bypass_p")
(define_insn_reservation "power6-load-update" 2 ; fx (define_insn_reservation "power6-load-update" 2 ; fx
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-load-update-indexed" 2 ; fx (define_insn_reservation "power6-load-update-indexed" 2 ; fx
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-load-ext-update" 4 ; fx (define_insn_reservation "power6-load-ext-update" 4 ; fx
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-fpload" 1 (define_insn_reservation "power6-fpload" 1
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
(define_insn_reservation "power6-fpload-update" 1 (define_insn_reservation "power6-fpload-update" 1
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-store" 14 (define_insn_reservation "power6-store" 14
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSU_power6") "LSU_power6")
(define_insn_reservation "power6-store-update" 14 (define_insn_reservation "power6-store-update" 14
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSX_power6") "LSX_power6")
(define_insn_reservation "power6-store-update-indexed" 14 (define_insn_reservation "power6-store-update-indexed" 14
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LX2_power6") "LX2_power6")
(define_insn_reservation "power6-fpstore" 14 (define_insn_reservation "power6-fpstore" 14
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"LSF_power6") "LSF_power6")
(define_insn_reservation "power6-fpstore-update" 14 (define_insn_reservation "power6-fpstore-update" 14
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power6")) (eq_attr "cpu" "power6"))
"XLF_power6") "XLF_power6")
......
gcc/config/rs6000/power7.md
...@@ -58,66 +58,91 @@ ...@@ -58,66 +58,91 @@
; LS Unit ; LS Unit
(define_insn_reservation "power7-load" 2 (define_insn_reservation "power7-load" 2
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7") "DU_power7,LSU_power7")
(define_insn_reservation "power7-load-ext" 3 (define_insn_reservation "power7-load-ext" 3
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7,FXU_power7") "DU2F_power7,LSU_power7,FXU_power7")
(define_insn_reservation "power7-load-update" 2 (define_insn_reservation "power7-load-update" 2
(and (eq_attr "type" "load_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7") "DU2F_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-load-update-indexed" 3 (define_insn_reservation "power7-load-update-indexed" 3
(and (eq_attr "type" "load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU4_power7,FXU_power7,LSU_power7+FXU_power7") "DU4_power7,FXU_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-load-ext-update" 4 (define_insn_reservation "power7-load-ext-update" 4
(and (eq_attr "type" "load_ext_u") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7,FXU_power7") "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-load-ext-update-indexed" 4 (define_insn_reservation "power7-load-ext-update-indexed" 4
(and (eq_attr "type" "load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7") "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-fpload" 3 (define_insn_reservation "power7-fpload" 3
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7") "DU_power7,LSU_power7")
(define_insn_reservation "power7-fpload-update" 3 (define_insn_reservation "power7-fpload-update" 3
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7") "DU2F_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-store" 6 ; store-forwarding latency (define_insn_reservation "power7-store" 6 ; store-forwarding latency
(and (eq_attr "type" "store") (and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+FXU_power7") "DU_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-store-update" 6 (define_insn_reservation "power7-store-update" 6
(and (eq_attr "type" "store_u") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7,FXU_power7") "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-store-update-indexed" 6 (define_insn_reservation "power7-store-update-indexed" 6
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU4_power7,LSU_power7+FXU_power7,FXU_power7") "DU4_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-fpstore" 6 (define_insn_reservation "power7-fpstore" 6
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+VSU_power7") "DU_power7,LSU_power7+VSU_power7")
(define_insn_reservation "power7-fpstore-update" 6 (define_insn_reservation "power7-fpstore-update" 6
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power7")) (eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+VSU_power7+FXU_power7") "DU_power7,LSU_power7+VSU_power7+FXU_power7")
......
gcc/config/rs6000/power8.md
...@@ -80,51 +80,68 @@ ...@@ -80,51 +80,68 @@
; LS Unit ; LS Unit
(define_insn_reservation "power8-load" 3 (define_insn_reservation "power8-load" 3
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LU_or_LSU_power8") "DU_any_power8,LU_or_LSU_power8")
(define_insn_reservation "power8-load-update" 3 (define_insn_reservation "power8-load-update" 3
(and (eq_attr "type" "load_u,load_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8+FXU_power8") "DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
(define_insn_reservation "power8-load-ext" 3 (define_insn_reservation "power8-load-ext" 3
(and (eq_attr "type" "load_ext") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8,FXU_power8") "DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
(define_insn_reservation "power8-load-ext-update" 3 (define_insn_reservation "power8-load-ext-update" 3
(and (eq_attr "type" "load_ext_u,load_ext_ux") (and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8") "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
(define_insn_reservation "power8-fpload" 5 (define_insn_reservation "power8-fpload" 5
(and (eq_attr "type" "fpload,vecload") (and (ior (eq_attr "type" "vecload")
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")))
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LU_power8") "DU_any_power8,LU_power8")
(define_insn_reservation "power8-fpload-update" 5 (define_insn_reservation "power8-fpload-update" 5
(and (eq_attr "type" "fpload_u,fpload_ux") (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_power8+FXU_power8") "DU_cracked_power8,LU_power8+FXU_power8")
(define_insn_reservation "power8-store" 5 ; store-forwarding latency (define_insn_reservation "power8-store" 5 ; store-forwarding latency
(and (eq_attr "type" "store,store_u") (and (eq_attr "type" "store")
(not (and (eq_attr "update" "yes")
(eq_attr "indexed" "yes")))
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+LU_power8") "DU_any_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-store-update-indexed" 5 (define_insn_reservation "power8-store-update-indexed" 5
(and (eq_attr "type" "store_ux") (and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_cracked_power8,LSU_power8+LU_power8") "DU_cracked_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-fpstore" 5 (define_insn_reservation "power8-fpstore" 5
(and (eq_attr "type" "fpstore") (and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8") "DU_any_power8,LSU_power8+VSU_power8")
(define_insn_reservation "power8-fpstore-update" 5 (define_insn_reservation "power8-fpstore-update" 5
(and (eq_attr "type" "fpstore_u,fpstore_ux") (and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8")) (eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8") "DU_any_power8,LSU_power8+VSU_power8")
......
gcc/config/rs6000/predicates.md
...@@ -751,6 +751,13 @@ ...@@ -751,6 +751,13 @@
&& GET_CODE (XEXP (op, 0)) == PRE_MODIFY && GET_CODE (XEXP (op, 0)) == PRE_MODIFY
&& indexed_address (XEXP (XEXP (op, 0), 1), mode))")) && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))
;; Return 1 if the operand is a MEM with an indexed-form address.
(define_special_predicate "indexed_address_mem"
(match_test "(MEM_P (op)
&& (indexed_address (XEXP (op, 0), mode)
|| (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
&& indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
;; Used for the destination of the fix_truncdfsi2 expander. ;; Used for the destination of the fix_truncdfsi2 expander.
;; If stfiwx will be used, the result goes to memory; otherwise, ;; If stfiwx will be used, the result goes to memory; otherwise,
;; we're going to emit a store and a load of a subreg, so the dest is a ;; we're going to emit a store and a load of a subreg, so the dest is a
......
gcc/config/rs6000/rs6000.c
...@@ -26152,11 +26152,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26152,11 +26152,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
break; break;
case TYPE_STORE: case TYPE_STORE:
case TYPE_STORE_U:
case TYPE_STORE_UX:
case TYPE_FPSTORE: case TYPE_FPSTORE:
case TYPE_FPSTORE_U:
case TYPE_FPSTORE_UX:
if ((rs6000_cpu == PROCESSOR_POWER6) if ((rs6000_cpu == PROCESSOR_POWER6)
&& recog_memoized (dep_insn) && recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0)) && (INSN_CODE (dep_insn) >= 0))
...@@ -26173,17 +26169,13 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26173,17 +26169,13 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
switch (get_attr_type (dep_insn)) switch (get_attr_type (dep_insn))
{ {
case TYPE_LOAD: case TYPE_LOAD:
case TYPE_LOAD_U:
case TYPE_LOAD_UX:
case TYPE_CNTLZ: case TYPE_CNTLZ:
{ {
if (! store_data_bypass_p (dep_insn, insn)) if (! store_data_bypass_p (dep_insn, insn))
return 4; return get_attr_sign_extend (dep_insn)
== SIGN_EXTEND_YES ? 6 : 4;
break; break;
} }
case TYPE_LOAD_EXT:
case TYPE_LOAD_EXT_U:
case TYPE_LOAD_EXT_UX:
case TYPE_VAR_SHIFT_ROTATE: case TYPE_VAR_SHIFT_ROTATE:
case TYPE_VAR_DELAYED_COMPARE: case TYPE_VAR_DELAYED_COMPARE:
{ {
...@@ -26198,17 +26190,20 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26198,17 +26190,20 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_SHIFT: case TYPE_SHIFT:
case TYPE_INSERT_WORD: case TYPE_INSERT_WORD:
case TYPE_INSERT_DWORD: case TYPE_INSERT_DWORD:
case TYPE_FPLOAD_U:
case TYPE_FPLOAD_UX:
case TYPE_STORE_U:
case TYPE_STORE_UX:
case TYPE_FPSTORE_U:
case TYPE_FPSTORE_UX:
{ {
if (! store_data_bypass_p (dep_insn, insn)) if (! store_data_bypass_p (dep_insn, insn))
return 3; return 3;
break; break;
} }
case TYPE_STORE:
case TYPE_FPLOAD:
case TYPE_FPSTORE:
{
if (get_attr_update (dep_insn) == UPDATE_YES
&& ! store_data_bypass_p (dep_insn, insn))
return 3;
break;
}
case TYPE_IMUL: case TYPE_IMUL:
case TYPE_IMUL2: case TYPE_IMUL2:
case TYPE_IMUL3: case TYPE_IMUL3:
...@@ -26239,11 +26234,6 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26239,11 +26234,6 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
break; break;
case TYPE_LOAD: case TYPE_LOAD:
case TYPE_LOAD_U:
case TYPE_LOAD_UX:
case TYPE_LOAD_EXT:
case TYPE_LOAD_EXT_U:
case TYPE_LOAD_EXT_UX:
if ((rs6000_cpu == PROCESSOR_POWER6) if ((rs6000_cpu == PROCESSOR_POWER6)
&& recog_memoized (dep_insn) && recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0)) && (INSN_CODE (dep_insn) >= 0))
...@@ -26255,17 +26245,13 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26255,17 +26245,13 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
switch (get_attr_type (dep_insn)) switch (get_attr_type (dep_insn))
{ {
case TYPE_LOAD: case TYPE_LOAD:
case TYPE_LOAD_U:
case TYPE_LOAD_UX:
case TYPE_CNTLZ: case TYPE_CNTLZ:
{ {
if (set_to_load_agen (dep_insn, insn)) if (set_to_load_agen (dep_insn, insn))
return 4; return get_attr_sign_extend (dep_insn)
== SIGN_EXTEND_YES ? 6 : 4;
break; break;
} }
case TYPE_LOAD_EXT:
case TYPE_LOAD_EXT_U:
case TYPE_LOAD_EXT_UX:
case TYPE_VAR_SHIFT_ROTATE: case TYPE_VAR_SHIFT_ROTATE:
case TYPE_VAR_DELAYED_COMPARE: case TYPE_VAR_DELAYED_COMPARE:
{ {
...@@ -26280,17 +26266,20 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26280,17 +26266,20 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_SHIFT: case TYPE_SHIFT:
case TYPE_INSERT_WORD: case TYPE_INSERT_WORD:
case TYPE_INSERT_DWORD: case TYPE_INSERT_DWORD:
case TYPE_FPLOAD_U:
case TYPE_FPLOAD_UX:
case TYPE_STORE_U:
case TYPE_STORE_UX:
case TYPE_FPSTORE_U:
case TYPE_FPSTORE_UX:
{ {
if (set_to_load_agen (dep_insn, insn)) if (set_to_load_agen (dep_insn, insn))
return 3; return 3;
break; break;
} }
case TYPE_STORE:
case TYPE_FPLOAD:
case TYPE_FPSTORE:
{
if (get_attr_update (dep_insn) == UPDATE_YES
&& set_to_load_agen (dep_insn, insn))
return 3;
break;
}
case TYPE_IMUL: case TYPE_IMUL:
case TYPE_IMUL2: case TYPE_IMUL2:
case TYPE_IMUL3: case TYPE_IMUL3:
...@@ -26322,6 +26311,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26322,6 +26311,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_FPLOAD: case TYPE_FPLOAD:
if ((rs6000_cpu == PROCESSOR_POWER6) if ((rs6000_cpu == PROCESSOR_POWER6)
&& get_attr_update (insn) == UPDATE_NO
&& recog_memoized (dep_insn) && recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0) && (INSN_CODE (dep_insn) >= 0)
&& (get_attr_type (dep_insn) == TYPE_MFFGPR)) && (get_attr_type (dep_insn) == TYPE_MFFGPR))
...@@ -26351,7 +26341,8 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) ...@@ -26351,7 +26341,8 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return 1; return 1;
break; break;
case TYPE_FPLOAD: case TYPE_FPLOAD:
if (get_attr_type (dep_insn) == TYPE_MFFGPR) if (get_attr_update (insn) == UPDATE_NO
&& get_attr_type (dep_insn) == TYPE_MFFGPR)
return 2; return 2;
break; break;
default: default:
...@@ -26417,10 +26408,12 @@ is_microcoded_insn (rtx insn) ...@@ -26417,10 +26408,12 @@ is_microcoded_insn (rtx insn)
&& (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5)) && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
{ {
enum attr_type type = get_attr_type (insn); enum attr_type type = get_attr_type (insn);
if (type == TYPE_LOAD_EXT_U if ((type == TYPE_LOAD
|| type == TYPE_LOAD_EXT_UX && get_attr_update (insn) == UPDATE_YES
|| type == TYPE_LOAD_UX && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
|| type == TYPE_STORE_UX || ((type == TYPE_LOAD || type == TYPE_STORE)
&& get_attr_update (insn) == UPDATE_YES
&& get_attr_indexed (insn) == INDEXED_YES)
|| type == TYPE_MFCR) || type == TYPE_MFCR)
return true; return true;
} }
...@@ -26443,10 +26436,19 @@ is_cracked_insn (rtx insn) ...@@ -26443,10 +26436,19 @@ is_cracked_insn (rtx insn)
&& (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5)) && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
{ {
enum attr_type type = get_attr_type (insn); enum attr_type type = get_attr_type (insn);
if (type == TYPE_LOAD_U || type == TYPE_STORE_U if ((type == TYPE_LOAD
|| type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
|| type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX && get_attr_update (insn) == UPDATE_NO)
|| type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR || (type == TYPE_LOAD
&& get_attr_sign_extend (insn) == SIGN_EXTEND_NO
&& get_attr_update (insn) == UPDATE_YES
&& get_attr_indexed (insn) == INDEXED_NO)
|| (type == TYPE_STORE
&& get_attr_update (insn) == UPDATE_YES
&& get_attr_indexed (insn) == INDEXED_NO)
|| ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
&& get_attr_update (insn) == UPDATE_YES)
|| type == TYPE_DELAYED_CR
|| type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
|| type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
|| type == TYPE_IDIV || type == TYPE_LDIV || type == TYPE_IDIV || type == TYPE_LDIV
...@@ -27299,16 +27301,15 @@ insn_must_be_first_in_group (rtx insn) ...@@ -27299,16 +27301,15 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_SYNC: case TYPE_SYNC:
case TYPE_LOAD_L: case TYPE_LOAD_L:
case TYPE_STORE_C: case TYPE_STORE_C:
case TYPE_LOAD_U:
case TYPE_LOAD_UX:
case TYPE_LOAD_EXT_UX:
case TYPE_STORE_U:
case TYPE_STORE_UX:
case TYPE_FPLOAD_U:
case TYPE_FPLOAD_UX:
case TYPE_FPSTORE_U:
case TYPE_FPSTORE_UX:
return true; return true;
case TYPE_LOAD:
case TYPE_STORE:
case TYPE_FPLOAD:
case TYPE_FPSTORE:
if (get_attr_update (insn) == UPDATE_YES)
return true;
else
break;
default: default:
break; break;
} }
...@@ -27330,20 +27331,22 @@ insn_must_be_first_in_group (rtx insn) ...@@ -27330,20 +27331,22 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_ISYNC: case TYPE_ISYNC:
case TYPE_LOAD_L: case TYPE_LOAD_L:
case TYPE_STORE_C: case TYPE_STORE_C:
case TYPE_LOAD_U:
case TYPE_LOAD_UX:
case TYPE_LOAD_EXT:
case TYPE_LOAD_EXT_U:
case TYPE_LOAD_EXT_UX:
case TYPE_STORE_U:
case TYPE_STORE_UX:
case TYPE_FPLOAD_U:
case TYPE_FPLOAD_UX:
case TYPE_FPSTORE_U:
case TYPE_FPSTORE_UX:
case TYPE_MFJMPR: case TYPE_MFJMPR:
case TYPE_MTJMPR: case TYPE_MTJMPR:
return true; return true;
case TYPE_LOAD:
if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
|| get_attr_update (insn) == UPDATE_YES)
return true;
else
break;
case TYPE_STORE:
case TYPE_FPLOAD:
case TYPE_FPSTORE:
if (get_attr_update (insn) == UPDATE_YES)
return true;
else
break;
default: default:
break; break;
} }
...@@ -27367,16 +27370,22 @@ insn_must_be_first_in_group (rtx insn) ...@@ -27367,16 +27370,22 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_ISYNC: case TYPE_ISYNC:
case TYPE_LOAD_L: case TYPE_LOAD_L:
case TYPE_STORE_C: case TYPE_STORE_C:
case TYPE_LOAD_U:
case TYPE_LOAD_UX:
case TYPE_LOAD_EXT:
case TYPE_LOAD_EXT_U:
case TYPE_LOAD_EXT_UX:
case TYPE_STORE_UX:
case TYPE_VECSTORE: case TYPE_VECSTORE:
case TYPE_MFJMPR: case TYPE_MFJMPR:
case TYPE_MTJMPR: case TYPE_MTJMPR:
return true; return true;
case TYPE_LOAD:
if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
|| get_attr_update (insn) == UPDATE_YES)
return true;
else
break;
case TYPE_STORE:
if (get_attr_update (insn) == UPDATE_YES
&& get_attr_indexed (insn) == INDEXED_YES)
return true;
else
break;
default: default:
break; break;
} }
...@@ -27451,10 +27460,19 @@ insn_must_be_last_in_group (rtx insn) ...@@ -27451,10 +27460,19 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_SYNC: case TYPE_SYNC:
case TYPE_LOAD_L: case TYPE_LOAD_L:
case TYPE_STORE_C: case TYPE_STORE_C:
case TYPE_LOAD_EXT_U:
case TYPE_LOAD_EXT_UX:
case TYPE_STORE_UX:
return true; return true;
case TYPE_LOAD:
if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
&& get_attr_update (insn) == UPDATE_YES)
return true;
else
break;
case TYPE_STORE:
if (get_attr_update (insn) == UPDATE_YES
&& get_attr_indexed (insn) == INDEXED_YES)
return true;
else
break;
default: default:
break; break;
} }
...@@ -27470,10 +27488,19 @@ insn_must_be_last_in_group (rtx insn) ...@@ -27470,10 +27488,19 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_SYNC: case TYPE_SYNC:
case TYPE_LOAD_L: case TYPE_LOAD_L:
case TYPE_STORE_C: case TYPE_STORE_C:
case TYPE_LOAD_EXT_U:
case TYPE_LOAD_EXT_UX:
case TYPE_STORE_UX:
return true; return true;
case TYPE_LOAD:
if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
&& get_attr_update (insn) == UPDATE_YES)
return true;
else
break;
case TYPE_STORE:
if (get_attr_update (insn) == UPDATE_YES
&& get_attr_indexed (insn) == INDEXED_YES)
return true;
else
break;
default: default:
break; break;
} }
......
gcc/config/rs6000/rs6000.md
...@@ -157,9 +157,32 @@ ...@@ -157,9 +157,32 @@
;; Define an insn type attribute. This is used in function unit delay ;; Define an insn type attribute. This is used in function unit delay
;; computations. ;; computations.
(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm" (define_attr "type" "integer,two,three,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
(const_string "integer")) (const_string "integer"))
;; Does this instruction sign-extend its result?
;; This is used for load insns.
(define_attr "sign_extend" "no,yes" (const_string "no"))
;; Does this instruction use indexed (that is, reg+reg) addressing?
;; This is used for load and store insns. If operand 0 or 1 is a MEM
;; it is automatically set based on that. If a load or store instruction
;; has fewer than two operands it needs to set this attribute manually
;; or the compiler will crash.
(define_attr "indexed" "no,yes"
(if_then_else (ior (match_operand 0 "indexed_address_mem")
(match_operand 1 "indexed_address_mem"))
(const_string "yes")
(const_string "no")))
;; Does this instruction use update addressing?
;; This is used for load and store insns. See the comments for "indexed".
(define_attr "update" "no,yes"
(if_then_else (ior (match_operand 0 "update_address_mem")
(match_operand 1 "update_address_mem"))
(const_string "yes")
(const_string "no")))
;; Define floating point instruction sub-types for use with Xfpu.md ;; Define floating point instruction sub-types for use with Xfpu.md
(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default")) (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
...@@ -191,7 +214,9 @@ ...@@ -191,7 +214,9 @@
;; If this instruction is microcoded on the CELL processor ;; If this instruction is microcoded on the CELL processor
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always" (define_attr "cell_micro" "not,conditional,always"
(if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare") (if_then_else (ior (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,var_shift_rotate,var_delayed_compare")
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")))
(const_string "always") (const_string "always")
(const_string "not"))) (const_string "not")))
...@@ -512,15 +537,7 @@ ...@@ -512,15 +537,7 @@
"@ "@
l<wd>z%U1%X1 %0,%1 l<wd>z%U1%X1 %0,%1
rldicl %0,%1,0,<dbits>" rldicl %0,%1,0,<dbits>"
[(set_attr_alternative "type" [(set_attr "type" "load,*")])
[(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")])])
(define_insn "*zero_extend<mode>di2_internal2" (define_insn "*zero_extend<mode>di2_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
...@@ -584,18 +601,7 @@ ...@@ -584,18 +601,7 @@
mtvsrwz %x0,%1 mtvsrwz %x0,%1
lfiwzx %0,%y1 lfiwzx %0,%y1
lxsiwzx %x0,%y1" lxsiwzx %x0,%y1"
[(set_attr_alternative "type" [(set_attr "type" "load,*,mffgpr,fpload,fpload")])
[(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")
(const_string "mffgpr")
(const_string "fpload")
(const_string "fpload")])])
(define_insn "extendqidi2" (define_insn "extendqidi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -669,15 +675,8 @@ ...@@ -669,15 +675,8 @@
"@ "@
lha%U1%X1 %0,%1 lha%U1%X1 %0,%1
extsh %0,%1" extsh %0,%1"
[(set_attr_alternative "type" [(set_attr "type" "load,exts")
[(if_then_else (set_attr "sign_extend" "yes")])
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_u")
(const_string "load_ext")))
(const_string "exts")])])
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -754,18 +753,8 @@ ...@@ -754,18 +753,8 @@
mtvsrwa %x0,%1 mtvsrwa %x0,%1
lfiwax %0,%y1 lfiwax %0,%y1
lxsiwax %x0,%y1" lxsiwax %x0,%y1"
[(set_attr_alternative "type" [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
[(if_then_else (set_attr "sign_extend" "yes")])
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_u")
(const_string "load_ext")))
(const_string "exts")
(const_string "mffgpr")
(const_string "fpload")
(const_string "fpload")])])
(define_insn "*extendsidi2_nocell" (define_insn "*extendsidi2_nocell"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
...@@ -774,15 +763,8 @@ ...@@ -774,15 +763,8 @@
"@ "@
lwa%U1%X1 %0,%1 lwa%U1%X1 %0,%1
extsw %0,%1" extsw %0,%1"
[(set_attr_alternative "type" [(set_attr "type" "load,exts")
[(if_then_else (set_attr "sign_extend" "yes")])
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_u")
(const_string "load_ext")))
(const_string "exts")])])
(define_insn "*extendsidi2_nocell" (define_insn "*extendsidi2_nocell"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -856,15 +838,7 @@ ...@@ -856,15 +838,7 @@
"@ "@
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
rlwinm %0,%1,0,0xff" rlwinm %0,%1,0,0xff"
[(set_attr_alternative "type" [(set_attr "type" "load,*")])
[(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")])])
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
...@@ -984,15 +958,7 @@ ...@@ -984,15 +958,7 @@
"@ "@
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
rlwinm %0,%1,0,0xff" rlwinm %0,%1,0,0xff"
[(set_attr_alternative "type" [(set_attr "type" "load,*")])
[(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")])])
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
...@@ -1118,15 +1084,7 @@ ...@@ -1118,15 +1084,7 @@
"@ "@
lhz%U1%X1 %0,%1 lhz%U1%X1 %0,%1
rlwinm %0,%1,0,0xffff" rlwinm %0,%1,0,0xffff"
[(set_attr_alternative "type" [(set_attr "type" "load,*")])
[(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")])])
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
...@@ -1193,15 +1151,8 @@ ...@@ -1193,15 +1151,8 @@
"@ "@
lha%U1%X1 %0,%1 lha%U1%X1 %0,%1
extsh %0,%1" extsh %0,%1"
[(set_attr_alternative "type" [(set_attr "type" "load,exts")
[(if_then_else (set_attr "sign_extend" "yes")])
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_ext_u")
(const_string "load_ext")))
(const_string "exts")])])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -5260,25 +5211,7 @@ ...@@ -5260,25 +5211,7 @@
emit_note (NOTE_INSN_DELETED); emit_note (NOTE_INSN_DELETED);
DONE; DONE;
} }
[(set_attr_alternative "type" [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
[(const_string "fp")
(const_string "fp")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(const_string "fp")
(const_string "vecsimple")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))])])
(define_expand "truncdfsf2" (define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
...@@ -8878,31 +8811,7 @@ ...@@ -8878,31 +8811,7 @@
mt%0 %1 mt%0 %1
mt%0 %1 mt%0 %1
nop" nop"
[(set_attr_alternative "type" [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
[(const_string "*")
(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "mfjmpr")
(const_string "mtjmpr")
(const_string "*")
(const_string "*")])
(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")]) (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
(define_insn "*movsi_internal1_single" (define_insn "*movsi_internal1_single"
...@@ -8924,44 +8833,7 @@ ...@@ -8924,44 +8833,7 @@
nop nop
stfs%U0%X0 %1,%0 stfs%U0%X0 %1,%0
lfs%U1%X1 %0,%1" lfs%U1%X1 %0,%1"
[(set_attr_alternative "type" [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
[(const_string "*")
(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "mfjmpr")
(const_string "mtjmpr")
(const_string "*")
(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))])
(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
;; Split a load of a large constant into the appropriate two-insn ;; Split a load of a large constant into the appropriate two-insn
...@@ -9024,26 +8896,7 @@ ...@@ -9024,26 +8896,7 @@
mf%1 %0 mf%1 %0
mt%0 %1 mt%0 %1
nop" nop"
[(set_attr_alternative "type" [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
[(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(const_string "*")
(const_string "mfjmpr")
(const_string "mtjmpr")
(const_string "*")])])
(define_expand "mov<mode>" (define_expand "mov<mode>"
[(set (match_operand:INT 0 "general_operand" "") [(set (match_operand:INT 0 "general_operand" "")
...@@ -9064,26 +8917,7 @@ ...@@ -9064,26 +8917,7 @@
mf%1 %0 mf%1 %0
mt%0 %1 mt%0 %1
nop" nop"
[(set_attr_alternative "type" [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
[(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(const_string "*")
(const_string "mfjmpr")
(const_string "mtjmpr")
(const_string "*")])])
;; Here is how to move condition codes around. When we store CC data in ;; Here is how to move condition codes around. When we store CC data in
;; an integer register or memory, we store just the high-order 4 bits. ;; an integer register or memory, we store just the high-order 4 bits.
...@@ -9124,23 +8958,9 @@ ...@@ -9124,23 +8958,9 @@
(eq_attr "alternative" "9") (eq_attr "alternative" "9")
(const_string "mtjmpr") (const_string "mtjmpr")
(eq_attr "alternative" "10") (eq_attr "alternative" "10")
(if_then_else (const_string "load")
(match_test "update_indexed_address_mem (operands[1],
VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(eq_attr "alternative" "11") (eq_attr "alternative" "11")
(if_then_else (const_string "store")
(match_test "update_indexed_address_mem (operands[0],
VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(match_test "TARGET_MFCRF") (match_test "TARGET_MFCRF")
(const_string "mfcrf") (const_string "mfcrf")
] ]
...@@ -9209,48 +9029,7 @@ ...@@ -9209,48 +9029,7 @@
nop nop
# #
#" #"
[(set_attr_alternative "type" [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
[(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(const_string "fp")
(const_string "vecsimple")
(const_string "vecsimple")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(const_string "fpload")
(const_string "fpstore")
(const_string "mftgpr")
(const_string "mffgpr")
(const_string "mtjmpr")
(const_string "mfjmpr")
(const_string "*")
(const_string "*")
(const_string "*")])
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")]) (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
(define_insn "*mov<mode>_softfloat" (define_insn "*mov<mode>_softfloat"
...@@ -9270,29 +9049,7 @@ ...@@ -9270,29 +9049,7 @@
# #
# #
nop" nop"
[(set_attr_alternative "type" [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
[(const_string "*")
(const_string "mtjmpr")
(const_string "mfjmpr")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "*")])
(set_attr "length" "4,4,4,4,4,4,4,4,8,4")]) (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
...@@ -9407,38 +9164,7 @@ ...@@ -9407,38 +9164,7 @@
# #
# #
#" #"
[(set_attr_alternative "type" [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(const_string "fp")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(const_string "fpload"))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(const_string "fpstore"))
(const_string "vecsimple")
(const_string "vecsimple")
(const_string "store")
(const_string "load")
(const_string "two")
(const_string "fp")
(const_string "fp")
(const_string "*")])
(set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")]) (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
(define_insn "*mov<mode>_softfloat32" (define_insn "*mov<mode>_softfloat32"
...@@ -9483,57 +9209,7 @@ ...@@ -9483,57 +9209,7 @@
mffgpr %0,%1 mffgpr %0,%1
mfvsrd %0,%x1 mfvsrd %0,%x1
mtvsrd %x0,%1" mtvsrd %x0,%1"
[(set_attr_alternative "type" [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(const_string "fp")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(const_string "fpload"))
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(const_string "fpstore"))
(const_string "vecsimple")
(const_string "vecsimple")
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")
(const_string "mtjmpr")
(const_string "mfjmpr")
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "mftgpr")
(const_string "mffgpr")
(const_string "mftgpr")
(const_string "mffgpr")])
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")]) (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
(define_insn "*mov<mode>_softfloat64" (define_insn "*mov<mode>_softfloat64"
...@@ -9552,28 +9228,7 @@ ...@@ -9552,28 +9228,7 @@
# #
# #
nop" nop"
[(set_attr_alternative "type" [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")
(const_string "mtjmpr")
(const_string "mfjmpr")
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "*")])
(set_attr "length" "4,4,4,4,4,8,12,16,4")]) (set_attr "length" "4,4,4,4,4,8,12,16,4")])
(define_expand "mov<mode>" (define_expand "mov<mode>"
...@@ -10187,26 +9842,7 @@ ...@@ -10187,26 +9842,7 @@
lfd%U1%X1 %0,%1 lfd%U1%X1 %0,%1
fmr %0,%1 fmr %0,%1
#" #"
[(set_attr_alternative "type" [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
[(const_string "store")
(const_string "load")
(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(const_string "fp")
(const_string "*")])])
(define_split (define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "") [(set (match_operand:DI 0 "gpc_reg_operand" "")
...@@ -10259,47 +9895,7 @@ ...@@ -10259,47 +9895,7 @@
mffgpr %0,%1 mffgpr %0,%1
mfvsrd %0,%x1 mfvsrd %0,%x1
mtvsrd %x0,%1" mtvsrd %x0,%1"
[(set_attr_alternative "type" [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "store_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "store_u")
(const_string "store")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))
(const_string "*")
(const_string "*")
(const_string "*")
(const_string "*")
(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(const_string "fp")
(const_string "mfjmpr")
(const_string "mtjmpr")
(const_string "*")
(const_string "mftgpr")
(const_string "mffgpr")
(const_string "mftgpr")
(const_string "mffgpr")])
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")]) (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
;; Generate all one-bits and clear left or right. ;; Generate all one-bits and clear left or right.
...@@ -10383,7 +9979,9 @@ ...@@ -10383,7 +9979,9 @@
return \"#\"; return \"#\";
} }
}" }"
[(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*") [(set_attr "type" "store,store,load,load,*,*")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
(const_string "always") (const_string "always")
(const_string "conditional")))]) (const_string "conditional")))])
...@@ -10495,7 +10093,9 @@ ...@@ -10495,7 +10093,9 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 8" "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load_ux") [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi7" (define_insn "*ldmsi7"
...@@ -10517,7 +10117,9 @@ ...@@ -10517,7 +10117,9 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 7" "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load_ux") [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi6" (define_insn "*ldmsi6"
...@@ -10537,7 +10139,9 @@ ...@@ -10537,7 +10139,9 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 6" "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load_ux") [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi5" (define_insn "*ldmsi5"
...@@ -10555,7 +10159,9 @@ ...@@ -10555,7 +10159,9 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 5" "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load_ux") [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi4" (define_insn "*ldmsi4"
...@@ -10571,7 +10177,9 @@ ...@@ -10571,7 +10177,9 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 4" "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load_ux") [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_insn "*ldmsi3" (define_insn "*ldmsi3"
...@@ -10585,7 +10193,9 @@ ...@@ -10585,7 +10193,9 @@
"TARGET_STRING && XVECLEN (operands[0], 0) == 3" "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
"* "*
{ return rs6000_output_load_multiple (operands); }" { return rs6000_output_load_multiple (operands); }"
[(set_attr "type" "load_ux") [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "length" "32")]) (set_attr "length" "32")])
(define_expand "store_multiple" (define_expand "store_multiple"
...@@ -10653,7 +10263,9 @@ ...@@ -10653,7 +10263,9 @@
(match_operand:SI 10 "gpc_reg_operand" "r"))])] (match_operand:SI 10 "gpc_reg_operand" "r"))])]
"TARGET_STRING && XVECLEN (operands[0], 0) == 9" "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
"stswi %2,%1,%O0" "stswi %2,%1,%O0"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always")]) (set_attr "cell_micro" "always")])
(define_insn "*stmsi7" (define_insn "*stmsi7"
...@@ -10675,7 +10287,9 @@ ...@@ -10675,7 +10287,9 @@
(match_operand:SI 9 "gpc_reg_operand" "r"))])] (match_operand:SI 9 "gpc_reg_operand" "r"))])]
"TARGET_STRING && XVECLEN (operands[0], 0) == 8" "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
"stswi %2,%1,%O0" "stswi %2,%1,%O0"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always")]) (set_attr "cell_micro" "always")])
(define_insn "*stmsi6" (define_insn "*stmsi6"
...@@ -10695,7 +10309,9 @@ ...@@ -10695,7 +10309,9 @@
(match_operand:SI 8 "gpc_reg_operand" "r"))])] (match_operand:SI 8 "gpc_reg_operand" "r"))])]
"TARGET_STRING && XVECLEN (operands[0], 0) == 7" "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
"stswi %2,%1,%O0" "stswi %2,%1,%O0"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always")]) (set_attr "cell_micro" "always")])
(define_insn "*stmsi5" (define_insn "*stmsi5"
...@@ -10713,7 +10329,9 @@ ...@@ -10713,7 +10329,9 @@
(match_operand:SI 7 "gpc_reg_operand" "r"))])] (match_operand:SI 7 "gpc_reg_operand" "r"))])]
"TARGET_STRING && XVECLEN (operands[0], 0) == 6" "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
"stswi %2,%1,%O0" "stswi %2,%1,%O0"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always")]) (set_attr "cell_micro" "always")])
(define_insn "*stmsi4" (define_insn "*stmsi4"
...@@ -10729,7 +10347,9 @@ ...@@ -10729,7 +10347,9 @@
(match_operand:SI 6 "gpc_reg_operand" "r"))])] (match_operand:SI 6 "gpc_reg_operand" "r"))])]
"TARGET_STRING && XVECLEN (operands[0], 0) == 5" "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
"stswi %2,%1,%O0" "stswi %2,%1,%O0"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always")]) (set_attr "cell_micro" "always")])
(define_insn "*stmsi3" (define_insn "*stmsi3"
...@@ -10743,7 +10363,9 @@ ...@@ -10743,7 +10363,9 @@
(match_operand:SI 5 "gpc_reg_operand" "r"))])] (match_operand:SI 5 "gpc_reg_operand" "r"))])]
"TARGET_STRING && XVECLEN (operands[0], 0) == 4" "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
"stswi %2,%1,%O0" "stswi %2,%1,%O0"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always")]) (set_attr "cell_micro" "always")])
(define_expand "setmemsi" (define_expand "setmemsi"
...@@ -10825,7 +10447,9 @@ ...@@ -10825,7 +10447,9 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"lswi %4,%1,%2\;stswi %4,%0,%2" "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always") (set_attr "cell_micro" "always")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -10865,7 +10489,9 @@ ...@@ -10865,7 +10489,9 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"lswi %4,%1,%2\;stswi %4,%0,%2" "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always") (set_attr "cell_micro" "always")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -10901,7 +10527,9 @@ ...@@ -10901,7 +10527,9 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5" && REGNO (operands[4]) == 5"
"lswi %4,%1,%2\;stswi %4,%0,%2" "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always") (set_attr "cell_micro" "always")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -10926,7 +10554,9 @@ ...@@ -10926,7 +10554,9 @@
"TARGET_STRING && ! TARGET_POWERPC64 "TARGET_STRING && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"lswi %4,%1,%2\;stswi %4,%0,%2" "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always") (set_attr "cell_micro" "always")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -10950,7 +10580,9 @@ ...@@ -10950,7 +10580,9 @@
(clobber (match_scratch:SI 5 "=X"))] (clobber (match_scratch:SI 5 "=X"))]
"TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"lswi %4,%1,%2\;stswi %4,%0,%2" "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux") [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always") (set_attr "cell_micro" "always")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -10975,7 +10607,9 @@ ...@@ -10975,7 +10607,9 @@
"@ "@
ldux %3,%0,%2 ldux %3,%0,%2
ldu %3,%2(%0)" ldu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")]) [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "movdi_<mode>_update" (define_insn "movdi_<mode>_update"
[(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
...@@ -10991,7 +10625,9 @@ ...@@ -10991,7 +10625,9 @@
"@ "@
stdux %3,%0,%2 stdux %3,%0,%2
stdu %3,%2(%0)" stdu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
;; This pattern is only conditional on TARGET_POWERPC64, as it is ;; This pattern is only conditional on TARGET_POWERPC64, as it is
;; needed for stack allocation, even if the user passes -mno-update. ;; needed for stack allocation, even if the user passes -mno-update.
...@@ -11005,7 +10641,9 @@ ...@@ -11005,7 +10641,9 @@
"@ "@
stdux %3,%0,%2 stdux %3,%0,%2
stdu %3,%2(%0)" stdu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movsi_update1" (define_insn "*movsi_update1"
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
...@@ -11019,7 +10657,9 @@ ...@@ -11019,7 +10657,9 @@
"@ "@
lwzux %3,%0,%2 lwzux %3,%0,%2
lwzu %3,%2(%0)" lwzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")]) [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movsi_update2" (define_insn "*movsi_update2"
[(set (match_operand:DI 3 "gpc_reg_operand" "=r") [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
...@@ -11031,7 +10671,10 @@ ...@@ -11031,7 +10671,10 @@
"TARGET_POWERPC64 && rs6000_gen_cell_microcode "TARGET_POWERPC64 && rs6000_gen_cell_microcode
&& !avoiding_indexed_address_p (DImode)" && !avoiding_indexed_address_p (DImode)"
"lwaux %3,%0,%2" "lwaux %3,%0,%2"
[(set_attr "type" "load_ext_ux")]) [(set_attr "type" "load")
(set_attr "sign_extend" "yes")
(set_attr "update" "yes")
(set_attr "indexed" "yes")])
(define_insn "movsi_update" (define_insn "movsi_update"
[(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
...@@ -11047,7 +10690,9 @@ ...@@ -11047,7 +10690,9 @@
"@ "@
stwux %3,%0,%2 stwux %3,%0,%2
stwu %3,%2(%0)" stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
;; This is an unconditional pattern; needed for stack allocation, even ;; This is an unconditional pattern; needed for stack allocation, even
;; if the user passes -mno-update. ;; if the user passes -mno-update.
...@@ -11061,7 +10706,9 @@ ...@@ -11061,7 +10706,9 @@
"@ "@
stwux %3,%0,%2 stwux %3,%0,%2
stwu %3,%2(%0)" stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movhi_update1" (define_insn "*movhi_update1"
[(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
...@@ -11075,7 +10722,9 @@ ...@@ -11075,7 +10722,9 @@
"@ "@
lhzux %3,%0,%2 lhzux %3,%0,%2
lhzu %3,%2(%0)" lhzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")]) [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movhi_update2" (define_insn "*movhi_update2"
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
...@@ -11090,7 +10739,9 @@ ...@@ -11090,7 +10739,9 @@
"@ "@
lhzux %3,%0,%2 lhzux %3,%0,%2
lhzu %3,%2(%0)" lhzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")]) [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movhi_update3" (define_insn "*movhi_update3"
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
...@@ -11105,7 +10756,10 @@ ...@@ -11105,7 +10756,10 @@
"@ "@
lhaux %3,%0,%2 lhaux %3,%0,%2
lhau %3,%2(%0)" lhau %3,%2(%0)"
[(set_attr "type" "load_ext_ux,load_ext_u")]) [(set_attr "type" "load")
(set_attr "sign_extend" "yes")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movhi_update4" (define_insn "*movhi_update4"
[(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
...@@ -11119,7 +10773,9 @@ ...@@ -11119,7 +10773,9 @@
"@ "@
sthux %3,%0,%2 sthux %3,%0,%2
sthu %3,%2(%0)" sthu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movqi_update1" (define_insn "*movqi_update1"
[(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
...@@ -11133,7 +10789,9 @@ ...@@ -11133,7 +10789,9 @@
"@ "@
lbzux %3,%0,%2 lbzux %3,%0,%2
lbzu %3,%2(%0)" lbzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")]) [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movqi_update2" (define_insn "*movqi_update2"
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
...@@ -11148,7 +10806,9 @@ ...@@ -11148,7 +10806,9 @@
"@ "@
lbzux %3,%0,%2 lbzux %3,%0,%2
lbzu %3,%2(%0)" lbzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")]) [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movqi_update3" (define_insn "*movqi_update3"
[(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
...@@ -11162,7 +10822,9 @@ ...@@ -11162,7 +10822,9 @@
"@ "@
stbux %3,%0,%2 stbux %3,%0,%2
stbu %3,%2(%0)" stbu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movsf_update1" (define_insn "*movsf_update1"
[(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
...@@ -11176,7 +10838,9 @@ ...@@ -11176,7 +10838,9 @@
"@ "@
lfsux %3,%0,%2 lfsux %3,%0,%2
lfsu %3,%2(%0)" lfsu %3,%2(%0)"
[(set_attr "type" "fpload_ux,fpload_u")]) [(set_attr "type" "fpload")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movsf_update2" (define_insn "*movsf_update2"
[(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
...@@ -11190,7 +10854,9 @@ ...@@ -11190,7 +10854,9 @@
"@ "@
stfsux %3,%0,%2 stfsux %3,%0,%2
stfsu %3,%2(%0)" stfsu %3,%2(%0)"
[(set_attr "type" "fpstore_ux,fpstore_u")]) [(set_attr "type" "fpstore")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movsf_update3" (define_insn "*movsf_update3"
[(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
...@@ -11204,7 +10870,9 @@ ...@@ -11204,7 +10870,9 @@
"@ "@
lwzux %3,%0,%2 lwzux %3,%0,%2
lwzu %3,%2(%0)" lwzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")]) [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movsf_update4" (define_insn "*movsf_update4"
[(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
...@@ -11218,7 +10886,9 @@ ...@@ -11218,7 +10886,9 @@
"@ "@
stwux %3,%0,%2 stwux %3,%0,%2
stwu %3,%2(%0)" stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movdf_update1" (define_insn "*movdf_update1"
[(set (match_operand:DF 3 "gpc_reg_operand" "=d,d") [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
...@@ -11232,7 +10902,9 @@ ...@@ -11232,7 +10902,9 @@
"@ "@
lfdux %3,%0,%2 lfdux %3,%0,%2
lfdu %3,%2(%0)" lfdu %3,%2(%0)"
[(set_attr "type" "fpload_ux,fpload_u")]) [(set_attr "type" "fpload")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
(define_insn "*movdf_update2" (define_insn "*movdf_update2"
[(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
...@@ -11246,7 +10918,9 @@ ...@@ -11246,7 +10918,9 @@
"@ "@
stfdux %3,%0,%2 stfdux %3,%0,%2
stfdu %3,%2(%0)" stfdu %3,%2(%0)"
[(set_attr "type" "fpstore_ux,fpstore_u")]) [(set_attr "type" "fpstore")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")])
;; After inserting conditional returns we can sometimes have ;; After inserting conditional returns we can sometimes have
...@@ -11916,7 +11590,9 @@ ...@@ -11916,7 +11590,9 @@
operands[2] = gen_rtx_REG (Pmode, 2); operands[2] = gen_rtx_REG (Pmode, 2);
return \"lwz %0,%1(%2)\"; return \"lwz %0,%1(%2)\";
}" }"
[(set_attr "type" "load")]) [(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
(define_insn "load_toc_aix_di" (define_insn "load_toc_aix_di"
[(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -11938,7 +11614,9 @@ ...@@ -11938,7 +11614,9 @@
operands[2] = gen_rtx_REG (Pmode, 2); operands[2] = gen_rtx_REG (Pmode, 2);
return \"ld %0,%1(%2)\"; return \"ld %0,%1(%2)\";
}" }"
[(set_attr "type" "load")]) [(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
(define_insn "load_toc_v4_pic_si" (define_insn "load_toc_v4_pic_si"
[(set (reg:SI LR_REGNO) [(set (reg:SI LR_REGNO)
...@@ -12914,14 +12592,15 @@ ...@@ -12914,14 +12592,15 @@
operands[1] = gen_rtx_REG (Pmode, 0); operands[1] = gen_rtx_REG (Pmode, 0);
return "st<wd>%U0%X0 %1,%0"; return "st<wd>%U0%X0 %1,%0";
} }
[(set (attr "type") [(set_attr "type" "store")
(if_then_else (set (attr "update")
(match_test "update_indexed_address_mem (operands[0], VOIDmode)") (if_then_else (match_operand 0 "update_address_mem")
(const_string "store_ux") (const_string "yes")
(if_then_else (const_string "no")))
(match_test "update_address_mem (operands[0], VOIDmode)") (set (attr "indexed")
(const_string "store_u") (if_then_else (match_operand 0 "indexed_address_mem")
(const_string "store")))) (const_string "yes")
(const_string "no")))
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "probe_stack_range<P:mode>" (define_insn "probe_stack_range<P:mode>"
...@@ -15118,7 +14797,9 @@ ...@@ -15118,7 +14797,9 @@
(match_operand:SI 2 "gpc_reg_operand" "r"))])] (match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE" "TARGET_MULTIPLE"
"stmw %2,%1" "stmw %2,%1"
[(set_attr "type" "store_ux")]) [(set_attr "type" "store")
(set_attr "update" "yes")
(set_attr "indexed" "yes")])
; The following comment applies to: ; The following comment applies to:
; save_gpregs_* ; save_gpregs_*
...@@ -15277,7 +14958,9 @@ ...@@ -15277,7 +14958,9 @@
(match_operand:SI 2 "memory_operand" "m"))])] (match_operand:SI 2 "memory_operand" "m"))])]
"TARGET_MULTIPLE" "TARGET_MULTIPLE"
"lmw %1,%2" "lmw %1,%2"
[(set_attr "type" "load_ux") [(set_attr "type" "load")
(set_attr "update" "yes")
(set_attr "indexed" "yes")
(set_attr "cell_micro" "always")]) (set_attr "cell_micro" "always")])
(define_insn "*return_internal_<mode>" (define_insn "*return_internal_<mode>"
......
gcc/config/rs6000/rs64.md
...@@ -26,17 +26,17 @@ ...@@ -26,17 +26,17 @@
;; RS64a 64-bit IU, LSU, FPU, BPU ;; RS64a 64-bit IU, LSU, FPU, BPU
(define_insn_reservation "rs64a-load" 2 (define_insn_reservation "rs64a-load" 2
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load")
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
(define_insn_reservation "rs64a-store" 2 (define_insn_reservation "rs64a-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
(define_insn_reservation "rs64a-fpload" 3 (define_insn_reservation "rs64a-fpload" 3
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "rs64a")) (eq_attr "cpu" "rs64a"))
"lsu_rs64") "lsu_rs64")
......
gcc/config/rs6000/titan.md
...@@ -95,13 +95,12 @@ ...@@ -95,13 +95,12 @@
;; Loads. ;; Loads.
(define_insn_reservation "titan_lsu_load" 3 (define_insn_reservation "titan_lsu_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ (and (eq_attr "type" "load,load_l,sync")
load_l,sync")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
(define_insn_reservation "titan_lsu_fpload" 12 (define_insn_reservation "titan_lsu_fpload" 12
(and (eq_attr "type" "fpload,fpload_ux,fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
...@@ -115,12 +114,12 @@ ...@@ -115,12 +114,12 @@
;; Stores. ;; Stores.
(define_insn_reservation "titan_lsu_store" 12 (define_insn_reservation "titan_lsu_store" 12
(and (eq_attr "type" "store,store_ux,store_u,store_c") (and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
(define_insn_reservation "titan_lsu_fpstore" 12 (define_insn_reservation "titan_lsu_fpstore" 12
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "titan")) (eq_attr "cpu" "titan"))
"titan_issue,titan_lsu_sh") "titan_issue,titan_lsu_sh")
......
gcc/config/rs6000/vsx.md
...@@ -657,8 +657,9 @@ ...@@ -657,8 +657,9 @@
gcc_unreachable (); gcc_unreachable ();
} }
} }
[(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store_ux,store_ux,load_ux,load_ux, *, *") [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,store,load,load, *, *")
(set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16") (set_attr "update" " *, *, *, *, *, *, *, yes, yes, yes, yes, *, *")
(set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16")
(set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
(const_string "always") (const_string "always")
(const_string "conditional")))]) (const_string "conditional")))])
...@@ -1613,22 +1614,7 @@ ...@@ -1613,22 +1614,7 @@
lfd%U1%X1 %0,%1 lfd%U1%X1 %0,%1
lxsd%U1x %x0,%y1 lxsd%U1x %x0,%y1
ld%U1%X1 %0,%1" ld%U1%X1 %0,%1"
[(set_attr_alternative "type" [(set_attr "type" "fpload,fpload,load")
[(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "fpload_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "fpload_u")
(const_string "fpload")))
(const_string "fpload")
(if_then_else
(match_test "update_indexed_address_mem (operands[1], VOIDmode)")
(const_string "load_ux")
(if_then_else
(match_test "update_address_mem (operands[1], VOIDmode)")
(const_string "load_u")
(const_string "load")))])
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Optimize storing a single scalar element that is the right location to ;; Optimize storing a single scalar element that is the right location to
...@@ -1643,16 +1629,7 @@ ...@@ -1643,16 +1629,7 @@
stfd%U0%X0 %1,%0 stfd%U0%X0 %1,%0
stxsd%U0x %x1,%y0 stxsd%U0x %x1,%y0
stxsd%U0x %x1,%y0" stxsd%U0x %x1,%y0"
[(set_attr_alternative "type" [(set_attr "type" "fpstore")
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_ux")
(if_then_else
(match_test "update_address_mem (operands[0], VOIDmode)")
(const_string "fpstore_u")
(const_string "fpstore")))
(const_string "fpstore")
(const_string "fpstore")])
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Extract a SF element from V4SF ;; Extract a SF element from V4SF
......
gcc/config/rs6000/xfpu.md
...@@ -118,12 +118,12 @@ ...@@ -118,12 +118,12 @@
"Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub") "Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
(define_insn_reservation "fp-load" 10 ;; FIXME. Is double/single precision the same ? (define_insn_reservation "fp-load" 10 ;; FIXME. Is double/single precision the same ?
(and (eq_attr "type" "fpload, fpload_ux, fpload_u") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc405")) (eq_attr "cpu" "ppc405"))
"Xfpu_issue*10") "Xfpu_issue*10")
(define_insn_reservation "fp-store" 4 (define_insn_reservation "fp-store" 4
(and (eq_attr "type" "fpstore, fpstore_ux, fpstore_u") (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc405")) (eq_attr "cpu" "ppc405"))
"Xfpu_issue*4") "Xfpu_issue*4")
......
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