x86: fix CVT{,T}PD2PI insns

With just an "m" constraint misaligned memory operands won't be forced
into a register, and hence cause #GP. So far this was guaranteed only
in the case that CVT{,T}PD2DQ were chosen (which looks to be the case on
x86-64 only).

Switch the second alternative to Bm and also replace
nonimmediate_operand by vector_operand.

From-SVN: r272780

gcc/ChangeLog

+2019-06-28  Jan Beulich  <jbeulich@suse.com>
+
+	* config/i386/sse.md (sse2_cvtpd2pi, sse2_cvttpd2pi): Use
+	vector_operand plus, on both alternatives, "Bm" constraint.
+
 2019-06-28  Dennis Zhang  <dennis.zhang@arm.com>
 
 	* config/arm/arm.md: Remove redundant constraints from

gcc/config/i386/sse.md

@@ -5505,7 +5505,7 @@
 
 (define_insn "sse2_cvtpd2pi"
   [(set (match_operand:V2SI 0 "register_operand" "=v,?!y")
-	(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vBm,xm")]
+	(unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vBm,xBm")]
 		     UNSPEC_FIX_NOTRUNC))]
   "TARGET_SSE2"
   "@
@@ -5523,7 +5523,7 @@
 
 (define_insn "sse2_cvttpd2pi"
   [(set (match_operand:V2SI 0 "register_operand" "=v,?!y")
-	(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vBm,xm")))]
+	(fix:V2SI (match_operand:V2DF 1 "vector_operand" "vBm,xBm")))]
   "TARGET_SSE2"
   "@
    * return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\" : \"cvttpd2dq\t{%1, %0|%0, %1}\";

gcc/testsuite/ChangeLog

+2019-06-28  Jan Beulich  <jbeulich@suse.com>
+
+	* gcc.target/i386/cvtpd2pi: New.
+
 2019-06-27  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c++/91024