Skip to content

R
riscv-gcc-1
Commit cd65e265 by Dennis Zhang Committed by Kyrylo Tkachov
Options

[Arm] Remove constraint strings from define_expand constructs in the back end 

A number of Arm define_expand patterns have specified constraints for
their operands. But the constraint strings are ignored at expand time
and are therefore redundant/useless. We now avoid specifying constraints
in new define_expands, but we should clean up the existing define_expand
definitions.

2019-06-28  Dennis Zhang  <dennis.zhang@arm.com>

        * config/arm/arm.md: Remove redundant constraints from
        define_expand but leave reload_inm and reload_outm patterns
        untouched since they need special constraints to work.
        * config/arm/arm-fixed.md: Remove redundant constraints from
        define_expand.
        * config/arm/iwmmxt.md: Likewise.
        * config/arm/neon.md: Likewise.
        * config/arm/sync.md: Likewise.
        * config/arm/thumb1.md: Likewise.
        * config/arm/vec-common.md: Likewise.

From-SVN: r272779
parent 494cd9e8
Showing with 92 additions and 79 deletions
gcc/ChangeLog
2019-06-28 Dennis Zhang <dennis.zhang@arm.com>
* config/arm/arm.md: Remove redundant constraints from
define_expand but leave reload_inm and reload_outm patterns
untouched since they need special constraints to work.
* config/arm/arm-fixed.md: Remove redundant constraints from
define_expand.
* config/arm/iwmmxt.md: Likewise.
* config/arm/neon.md: Likewise.
* config/arm/sync.md: Likewise.
* config/arm/thumb1.md: Likewise.
* config/arm/vec-common.md: Likewise.
2019-06-27 Ilia Diachkov <ilia.diachkov@optimitech.com>
* doc/install.texi: Document --disable-tm-clone-registry.
......
gcc/config/arm/arm-fixed.md
......@@ -98,9 +98,9 @@
; Note: none of these do any rounding.
(define_expand "mulqq3"
[(set (match_operand:QQ 0 "s_register_operand" "")
(mult:QQ (match_operand:QQ 1 "s_register_operand" "")
(match_operand:QQ 2 "s_register_operand" "")))]
[(set (match_operand:QQ 0 "s_register_operand")
(mult:QQ (match_operand:QQ 1 "s_register_operand")
(match_operand:QQ 2 "s_register_operand")))]
"TARGET_DSP_MULTIPLY && arm_arch_thumb2"
{
rtx tmp1 = gen_reg_rtx (HImode);
......@@ -116,9 +116,9 @@
})
(define_expand "mulhq3"
[(set (match_operand:HQ 0 "s_register_operand" "")
(mult:HQ (match_operand:HQ 1 "s_register_operand" "")
(match_operand:HQ 2 "s_register_operand" "")))]
[(set (match_operand:HQ 0 "s_register_operand")
(mult:HQ (match_operand:HQ 1 "s_register_operand")
(match_operand:HQ 2 "s_register_operand")))]
"TARGET_DSP_MULTIPLY && arm_arch_thumb2"
{
rtx tmp = gen_reg_rtx (SImode);
......@@ -134,9 +134,9 @@
})
(define_expand "mulsq3"
[(set (match_operand:SQ 0 "s_register_operand" "")
(mult:SQ (match_operand:SQ 1 "s_register_operand" "")
(match_operand:SQ 2 "s_register_operand" "")))]
[(set (match_operand:SQ 0 "s_register_operand")
(mult:SQ (match_operand:SQ 1 "s_register_operand")
(match_operand:SQ 2 "s_register_operand")))]
"TARGET_32BIT"
{
rtx tmp1 = gen_reg_rtx (DImode);
......@@ -156,9 +156,9 @@
;; Accumulator multiplies.
(define_expand "mulsa3"
[(set (match_operand:SA 0 "s_register_operand" "")
(mult:SA (match_operand:SA 1 "s_register_operand" "")
(match_operand:SA 2 "s_register_operand" "")))]
[(set (match_operand:SA 0 "s_register_operand")
(mult:SA (match_operand:SA 1 "s_register_operand")
(match_operand:SA 2 "s_register_operand")))]
"TARGET_32BIT"
{
rtx tmp1 = gen_reg_rtx (DImode);
......@@ -175,9 +175,9 @@
})
(define_expand "mulusa3"
[(set (match_operand:USA 0 "s_register_operand" "")
(mult:USA (match_operand:USA 1 "s_register_operand" "")
(match_operand:USA 2 "s_register_operand" "")))]
[(set (match_operand:USA 0 "s_register_operand")
(mult:USA (match_operand:USA 1 "s_register_operand")
(match_operand:USA 2 "s_register_operand")))]
"TARGET_32BIT"
{
rtx tmp1 = gen_reg_rtx (DImode);
......@@ -317,9 +317,9 @@
(const_int 32)))])
(define_expand "mulha3"
[(set (match_operand:HA 0 "s_register_operand" "")
(mult:HA (match_operand:HA 1 "s_register_operand" "")
(match_operand:HA 2 "s_register_operand" "")))]
[(set (match_operand:HA 0 "s_register_operand")
(mult:HA (match_operand:HA 1 "s_register_operand")
(match_operand:HA 2 "s_register_operand")))]
"TARGET_DSP_MULTIPLY && arm_arch_thumb2"
{
rtx tmp = gen_reg_rtx (SImode);
......@@ -333,9 +333,9 @@
})
(define_expand "muluha3"
[(set (match_operand:UHA 0 "s_register_operand" "")
(mult:UHA (match_operand:UHA 1 "s_register_operand" "")
(match_operand:UHA 2 "s_register_operand" "")))]
[(set (match_operand:UHA 0 "s_register_operand")
(mult:UHA (match_operand:UHA 1 "s_register_operand")
(match_operand:UHA 2 "s_register_operand")))]
"TARGET_DSP_MULTIPLY"
{
rtx tmp1 = gen_reg_rtx (SImode);
......@@ -353,9 +353,9 @@
})
(define_expand "ssmulha3"
[(set (match_operand:HA 0 "s_register_operand" "")
(ss_mult:HA (match_operand:HA 1 "s_register_operand" "")
(match_operand:HA 2 "s_register_operand" "")))]
[(set (match_operand:HA 0 "s_register_operand")
(ss_mult:HA (match_operand:HA 1 "s_register_operand")
(match_operand:HA 2 "s_register_operand")))]
"TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6"
{
rtx tmp = gen_reg_rtx (SImode);
......@@ -373,9 +373,9 @@
})
(define_expand "usmuluha3"
[(set (match_operand:UHA 0 "s_register_operand" "")
(us_mult:UHA (match_operand:UHA 1 "s_register_operand" "")
(match_operand:UHA 2 "s_register_operand" "")))]
[(set (match_operand:UHA 0 "s_register_operand")
(us_mult:UHA (match_operand:UHA 1 "s_register_operand")
(match_operand:UHA 2 "s_register_operand")))]
"TARGET_INT_SIMD"
{
rtx tmp1 = gen_reg_rtx (SImode);
......
gcc/config/arm/iwmmxt.md
......@@ -256,55 +256,55 @@
(define_expand "iwmmxt_setwcgr0"
[(set (reg:SI WCGR0)
(match_operand:SI 0 "register_operand" ""))]
(match_operand:SI 0 "register_operand"))]
"TARGET_REALLY_IWMMXT"
{}
)
(define_expand "iwmmxt_setwcgr1"
[(set (reg:SI WCGR1)
(match_operand:SI 0 "register_operand" ""))]
(match_operand:SI 0 "register_operand"))]
"TARGET_REALLY_IWMMXT"
{}
)
(define_expand "iwmmxt_setwcgr2"
[(set (reg:SI WCGR2)
(match_operand:SI 0 "register_operand" ""))]
(match_operand:SI 0 "register_operand"))]
"TARGET_REALLY_IWMMXT"
{}
)
(define_expand "iwmmxt_setwcgr3"
[(set (reg:SI WCGR3)
(match_operand:SI 0 "register_operand" ""))]
(match_operand:SI 0 "register_operand"))]
"TARGET_REALLY_IWMMXT"
{}
)
(define_expand "iwmmxt_getwcgr0"
[(set (match_operand:SI 0 "register_operand" "")
[(set (match_operand:SI 0 "register_operand")
(reg:SI WCGR0))]
"TARGET_REALLY_IWMMXT"
{}
)
(define_expand "iwmmxt_getwcgr1"
[(set (match_operand:SI 0 "register_operand" "")
[(set (match_operand:SI 0 "register_operand")
(reg:SI WCGR1))]
"TARGET_REALLY_IWMMXT"
{}
)
(define_expand "iwmmxt_getwcgr2"
[(set (match_operand:SI 0 "register_operand" "")
[(set (match_operand:SI 0 "register_operand")
(reg:SI WCGR2))]
"TARGET_REALLY_IWMMXT"
{}
)
(define_expand "iwmmxt_getwcgr3"
[(set (match_operand:SI 0 "register_operand" "")
[(set (match_operand:SI 0 "register_operand")
(reg:SI WCGR3))]
"TARGET_REALLY_IWMMXT"
{}
......
gcc/config/arm/sync.md
......@@ -170,11 +170,11 @@
})
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "s_register_operand" "") ;; bool out
(match_operand:QHSD 1 "s_register_operand" "") ;; val out
(match_operand:QHSD 2 "mem_noofs_operand" "") ;; memory
(match_operand:QHSD 3 "general_operand" "") ;; expected
(match_operand:QHSD 4 "s_register_operand" "") ;; desired
[(match_operand:SI 0 "s_register_operand") ;; bool out
(match_operand:QHSD 1 "s_register_operand") ;; val out
(match_operand:QHSD 2 "mem_noofs_operand") ;; memory
(match_operand:QHSD 3 "general_operand") ;; expected
(match_operand:QHSD 4 "s_register_operand") ;; desired
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; mod_s
(match_operand:SI 7 "const_int_operand")] ;; mod_f
......
gcc/config/arm/thumb1.md
......@@ -794,9 +794,9 @@
(set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob,nocond")])
(define_expand "thumb_movhi_clobber"
[(set (match_operand:HI 0 "memory_operand" "")
(match_operand:HI 1 "register_operand" ""))
(clobber (match_operand:DI 2 "register_operand" ""))]
[(set (match_operand:HI 0 "memory_operand")
(match_operand:HI 1 "register_operand"))
(clobber (match_operand:DI 2 "register_operand"))]
"TARGET_THUMB1"
"
if (strict_memory_address_p (HImode, XEXP (operands[0], 0))
......@@ -977,8 +977,8 @@
(define_expand "cbranchqi4"
[(set (pc) (if_then_else
(match_operator 0 "lt_ge_comparison_operator"
[(match_operand:QI 1 "memory_operand" "")
(match_operand:QI 2 "const0_operand" "")])
[(match_operand:QI 1 "memory_operand")
(match_operand:QI 2 "const0_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
"TARGET_THUMB1"
......@@ -1616,8 +1616,8 @@
(define_expand "cstoresi_eq0_thumb1"
[(parallel
[(set (match_operand:SI 0 "s_register_operand" "")
(eq:SI (match_operand:SI 1 "s_register_operand" "")
[(set (match_operand:SI 0 "s_register_operand")
(eq:SI (match_operand:SI 1 "s_register_operand")
(const_int 0)))
(clobber (match_dup:SI 2))])]
"TARGET_THUMB1"
......@@ -1626,8 +1626,8 @@
(define_expand "cstoresi_ne0_thumb1"
[(parallel
[(set (match_operand:SI 0 "s_register_operand" "")
(ne:SI (match_operand:SI 1 "s_register_operand" "")
[(set (match_operand:SI 0 "s_register_operand")
(ne:SI (match_operand:SI 1 "s_register_operand")
(const_int 0)))
(clobber (match_dup:SI 2))])]
"TARGET_THUMB1"
......@@ -1838,8 +1838,8 @@
)
(define_expand "thumb1_casesi_internal_pic"
[(match_operand:SI 0 "s_register_operand" "")
(match_operand:SI 1 "thumb1_cmp_operand" "")
[(match_operand:SI 0 "s_register_operand")
(match_operand:SI 1 "thumb1_cmp_operand")
(match_operand 2 "" "")
(match_operand 3 "" "")]
"TARGET_THUMB1"
......@@ -1911,7 +1911,7 @@
;; Miscellaneous Thumb patterns
(define_expand "tablejump"
[(parallel [(set (pc) (match_operand:SI 0 "register_operand" ""))
[(parallel [(set (pc) (match_operand:SI 0 "register_operand"))
(use (label_ref (match_operand 1 "" "")))])]
"TARGET_THUMB1"
"
......
gcc/config/arm/vec-common.md
......@@ -21,8 +21,8 @@
;; Vector Moves
(define_expand "mov<mode>"
[(set (match_operand:VALL 0 "nonimmediate_operand" "")
(match_operand:VALL 1 "general_operand" ""))]
[(set (match_operand:VALL 0 "nonimmediate_operand")
(match_operand:VALL 1 "general_operand"))]
"TARGET_NEON
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
......@@ -42,9 +42,9 @@
;; patterns separately for IWMMXT and Neon.
(define_expand "add<mode>3"
[(set (match_operand:VALL 0 "s_register_operand" "")
(plus:VALL (match_operand:VALL 1 "s_register_operand" "")
(match_operand:VALL 2 "s_register_operand" "")))]
[(set (match_operand:VALL 0 "s_register_operand")
(plus:VALL (match_operand:VALL 1 "s_register_operand")
(match_operand:VALL 2 "s_register_operand")))]
"(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
|| flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
......@@ -52,9 +52,9 @@
})
(define_expand "sub<mode>3"
[(set (match_operand:VALL 0 "s_register_operand" "")
(minus:VALL (match_operand:VALL 1 "s_register_operand" "")
(match_operand:VALL 2 "s_register_operand" "")))]
[(set (match_operand:VALL 0 "s_register_operand")
(minus:VALL (match_operand:VALL 1 "s_register_operand")
(match_operand:VALL 2 "s_register_operand")))]
"(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
|| flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
......@@ -62,9 +62,9 @@
})
(define_expand "mul<mode>3"
[(set (match_operand:VALLW 0 "s_register_operand" "")
(mult:VALLW (match_operand:VALLW 1 "s_register_operand" "")
(match_operand:VALLW 2 "s_register_operand" "")))]
[(set (match_operand:VALLW 0 "s_register_operand")
(mult:VALLW (match_operand:VALLW 1 "s_register_operand")
(match_operand:VALLW 2 "s_register_operand")))]
"(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
|| flag_unsafe_math_optimizations))
|| (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
......@@ -72,9 +72,9 @@
})
(define_expand "smin<mode>3"
[(set (match_operand:VALLW 0 "s_register_operand" "")
(smin:VALLW (match_operand:VALLW 1 "s_register_operand" "")
(match_operand:VALLW 2 "s_register_operand" "")))]
[(set (match_operand:VALLW 0 "s_register_operand")
(smin:VALLW (match_operand:VALLW 1 "s_register_operand")
(match_operand:VALLW 2 "s_register_operand")))]
"(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
|| flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
......@@ -82,18 +82,18 @@
})
(define_expand "umin<mode>3"
[(set (match_operand:VINTW 0 "s_register_operand" "")
(umin:VINTW (match_operand:VINTW 1 "s_register_operand" "")
(match_operand:VINTW 2 "s_register_operand" "")))]
[(set (match_operand:VINTW 0 "s_register_operand")
(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
(match_operand:VINTW 2 "s_register_operand")))]
"TARGET_NEON
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
})
(define_expand "smax<mode>3"
[(set (match_operand:VALLW 0 "s_register_operand" "")
(smax:VALLW (match_operand:VALLW 1 "s_register_operand" "")
(match_operand:VALLW 2 "s_register_operand" "")))]
[(set (match_operand:VALLW 0 "s_register_operand")
(smax:VALLW (match_operand:VALLW 1 "s_register_operand")
(match_operand:VALLW 2 "s_register_operand")))]
"(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
|| flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
......@@ -101,19 +101,19 @@
})
(define_expand "umax<mode>3"
[(set (match_operand:VINTW 0 "s_register_operand" "")
(umax:VINTW (match_operand:VINTW 1 "s_register_operand" "")
(match_operand:VINTW 2 "s_register_operand" "")))]
[(set (match_operand:VINTW 0 "s_register_operand")
(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
(match_operand:VINTW 2 "s_register_operand")))]
"TARGET_NEON
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
})
(define_expand "vec_perm<mode>"
[(match_operand:VE 0 "s_register_operand" "")
(match_operand:VE 1 "s_register_operand" "")
(match_operand:VE 2 "s_register_operand" "")
(match_operand:VE 3 "s_register_operand" "")]
[(match_operand:VE 0 "s_register_operand")
(match_operand:VE 1 "s_register_operand")
(match_operand:VE 2 "s_register_operand")
(match_operand:VE 3 "s_register_operand")]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
{
arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment