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riscv-gcc-1
Commit bcd48995 by Alex Velenko Committed by Marcus Shawcroft
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[AArch64] 64-bit float vreinterpret implemention 

This patch introduces vreinterpret implementation for vectors with
64-bit float lanes and adds testcase for those intrinsics.

From-SVN: r209642
parent 0bf3afc1
Showing with 136 additions and 0 deletions
gcc/ChangeLog
2014-04-22 Alex Velenko <Alex.Velenko@arm.com> 2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
(aarch64_types_signed_unsigned_qualifiers): Qualifier added.
(aarch64_types_signed_poly_qualifiers): Likewise.
(aarch64_types_unsigned_signed_qualifiers): Likewise.
(aarch64_types_poly_signed_qualifiers): Likewise.
(TYPES_REINTERP_SS): Type macro added.
(TYPES_REINTERP_SU): Likewise.
(TYPES_REINTERP_SP): Likewise.
(TYPES_REINTERP_US): Likewise.
(TYPES_REINTERP_PS): Likewise.
(aarch64_fold_builtin): New expression folding added.
* config/aarch64/aarch64-simd-builtins.def (REINTERP):
Declarations removed.
(REINTERP_SS): Declarations added.
(REINTERP_US): Likewise.
(REINTERP_PS): Likewise.
(REINTERP_SU): Likewise.
(REINTERP_SP): Likewise.
* config/aarch64/arm_neon.h (vreinterpret_p8_f64): Implemented.
(vreinterpretq_p8_f64): Likewise.
(vreinterpret_p16_f64): Likewise.
(vreinterpretq_p16_f64): Likewise.
(vreinterpret_f32_f64): Likewise.
(vreinterpretq_f32_f64): Likewise.
(vreinterpret_f64_f32): Likewise.
(vreinterpret_f64_p8): Likewise.
(vreinterpret_f64_p16): Likewise.
(vreinterpret_f64_s8): Likewise.
(vreinterpret_f64_s16): Likewise.
(vreinterpret_f64_s32): Likewise.
(vreinterpret_f64_s64): Likewise.
(vreinterpret_f64_u8): Likewise.
(vreinterpret_f64_u16): Likewise.
(vreinterpret_f64_u32): Likewise.
(vreinterpret_f64_u64): Likewise.
(vreinterpretq_f64_f32): Likewise.
(vreinterpretq_f64_p8): Likewise.
(vreinterpretq_f64_p16): Likewise.
(vreinterpretq_f64_s8): Likewise.
(vreinterpretq_f64_s16): Likewise.
(vreinterpretq_f64_s32): Likewise.
(vreinterpretq_f64_s64): Likewise.
(vreinterpretq_f64_u8): Likewise.
(vreinterpretq_f64_u16): Likewise.
(vreinterpretq_f64_u32): Likewise.
(vreinterpretq_f64_u64): Likewise.
(vreinterpret_s64_f64): Likewise.
(vreinterpretq_s64_f64): Likewise.
(vreinterpret_u64_f64): Likewise.
(vreinterpretq_u64_f64): Likewise.
(vreinterpret_s8_f64): Likewise.
(vreinterpretq_s8_f64): Likewise.
(vreinterpret_s16_f64): Likewise.
(vreinterpretq_s16_f64): Likewise.
(vreinterpret_s32_f64): Likewise.
(vreinterpretq_s32_f64): Likewise.
(vreinterpret_u8_f64): Likewise.
(vreinterpretq_u8_f64): Likewise.
(vreinterpret_u16_f64): Likewise.
(vreinterpretq_u16_f64): Likewise.
(vreinterpret_u32_f64): Likewise.
(vreinterpretq_u32_f64): Likewise.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed. * config/aarch64/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
* config/aarch64/aarch64/aarch64-simd-builtins.def (REINTERP): Removed. * config/aarch64/aarch64/aarch64-simd-builtins.def (REINTERP): Removed.
(vreinterpret_p8_s8): Likewise. (vreinterpret_p8_s8): Likewise.
......
gcc/config/aarch64/aarch64-builtins.c
...@@ -147,6 +147,23 @@ aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS] ...@@ -147,6 +147,23 @@ aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned }; = { qualifier_unsigned, qualifier_unsigned };
#define TYPES_UNOPU (aarch64_types_unopu_qualifiers) #define TYPES_UNOPU (aarch64_types_unopu_qualifiers)
#define TYPES_CREATE (aarch64_types_unop_qualifiers) #define TYPES_CREATE (aarch64_types_unop_qualifiers)
#define TYPES_REINTERP_SS (aarch64_types_unop_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_unop_su_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_unsigned };
#define TYPES_REINTERP_SU (aarch64_types_unop_su_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_unop_sp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_poly };
#define TYPES_REINTERP_SP (aarch64_types_unop_sp_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_unop_us_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_none };
#define TYPES_REINTERP_US (aarch64_types_unop_us_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_unop_ps_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_poly, qualifier_none };
#define TYPES_REINTERP_PS (aarch64_types_unop_ps_qualifiers)
static enum aarch64_type_qualifiers static enum aarch64_type_qualifiers
aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS] aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_maybe_immediate }; = { qualifier_none, qualifier_none, qualifier_maybe_immediate };
...@@ -1128,6 +1145,25 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args, ...@@ -1128,6 +1145,25 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
return fold_build2 (NE_EXPR, type, and_node, vec_zero_node); return fold_build2 (NE_EXPR, type, and_node, vec_zero_node);
break; break;
} }
VAR1 (REINTERP_SS, reinterpretdi, 0, df)
VAR1 (REINTERP_SS, reinterpretv8qi, 0, df)
VAR1 (REINTERP_SS, reinterpretv4hi, 0, df)
VAR1 (REINTERP_SS, reinterpretv2si, 0, df)
VAR1 (REINTERP_SS, reinterpretv2sf, 0, df)
BUILTIN_VD (REINTERP_SS, reinterpretdf, 0)
BUILTIN_VD (REINTERP_SU, reinterpretdf, 0)
VAR1 (REINTERP_US, reinterpretdi, 0, df)
VAR1 (REINTERP_US, reinterpretv8qi, 0, df)
VAR1 (REINTERP_US, reinterpretv4hi, 0, df)
VAR1 (REINTERP_US, reinterpretv2si, 0, df)
VAR1 (REINTERP_US, reinterpretv2sf, 0, df)
BUILTIN_VD (REINTERP_SP, reinterpretdf, 0)
VAR1 (REINTERP_PS, reinterpretdi, 0, df)
VAR1 (REINTERP_PS, reinterpretv8qi, 0, df)
VAR1 (REINTERP_PS, reinterpretv4hi, 0, df)
VAR1 (REINTERP_PS, reinterpretv2si, 0, df)
VAR1 (REINTERP_PS, reinterpretv2sf, 0, df)
return fold_build1 (VIEW_CONVERT_EXPR, type, args[0]);
VAR1 (UNOP, floatv2si, 2, v2sf) VAR1 (UNOP, floatv2si, 2, v2sf)
VAR1 (UNOP, floatv4si, 2, v4sf) VAR1 (UNOP, floatv4si, 2, v4sf)
VAR1 (UNOP, floatv2di, 2, v2df) VAR1 (UNOP, floatv2di, 2, v2df)
......
gcc/config/aarch64/aarch64-simd-builtins.def
...@@ -51,6 +51,28 @@ ...@@ -51,6 +51,28 @@
VAR1 (GETLANE, get_lane, 0, di) VAR1 (GETLANE, get_lane, 0, di)
BUILTIN_VALL (GETLANE, be_checked_get_lane, 0) BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
VAR1 (REINTERP_SS, reinterpretdi, 0, df)
VAR1 (REINTERP_SS, reinterpretv8qi, 0, df)
VAR1 (REINTERP_SS, reinterpretv4hi, 0, df)
VAR1 (REINTERP_SS, reinterpretv2si, 0, df)
VAR1 (REINTERP_SS, reinterpretv2sf, 0, df)
BUILTIN_VD (REINTERP_SS, reinterpretdf, 0)
BUILTIN_VD (REINTERP_SU, reinterpretdf, 0)
VAR1 (REINTERP_US, reinterpretdi, 0, df)
VAR1 (REINTERP_US, reinterpretv8qi, 0, df)
VAR1 (REINTERP_US, reinterpretv4hi, 0, df)
VAR1 (REINTERP_US, reinterpretv2si, 0, df)
VAR1 (REINTERP_US, reinterpretv2sf, 0, df)
BUILTIN_VD (REINTERP_SP, reinterpretdf, 0)
VAR1 (REINTERP_PS, reinterpretdi, 0, df)
VAR1 (REINTERP_PS, reinterpretv8qi, 0, df)
VAR1 (REINTERP_PS, reinterpretv4hi, 0, df)
VAR1 (REINTERP_PS, reinterpretv2si, 0, df)
VAR1 (REINTERP_PS, reinterpretv2sf, 0, df)
BUILTIN_VDQ_I (BINOP, dup_lane, 0) BUILTIN_VDQ_I (BINOP, dup_lane, 0)
/* Implemented by aarch64_<sur>q<r>shl<mode>. */ /* Implemented by aarch64_<sur>q<r>shl<mode>. */
......
gcc/config/aarch64/aarch64-simd.md
...@@ -2259,6 +2259,15 @@ ...@@ -2259,6 +2259,15 @@
DONE; DONE;
}) })
(define_expand "aarch64_reinterpretdf<mode>"
[(match_operand:DF 0 "register_operand" "")
(match_operand:VD_RE 1 "register_operand" "")]
"TARGET_SIMD"
{
aarch64_simd_reinterpret (operands[0], operands[1]);
DONE;
})
(define_expand "aarch64_reinterpretv16qi<mode>" (define_expand "aarch64_reinterpretv16qi<mode>"
[(match_operand:V16QI 0 "register_operand" "") [(match_operand:V16QI 0 "register_operand" "")
(match_operand:VQ 1 "register_operand" "")] (match_operand:VQ 1 "register_operand" "")]
......
gcc/testsuite/ChangeLog
2014-04-22 Alex Velenko <Alex.Velenko@arm.com> 2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vreinterpret_f64_1.c: New.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vqneg_s64_1.c: New testcase. * gcc.target/aarch64/vqneg_s64_1.c: New testcase.
* gcc.target/aarch64/vqabs_s64_1.c: New testcase. * gcc.target/aarch64/vqabs_s64_1.c: New testcase.
......
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