Commit bb68ff55 by Michael Meissner

Silence warnings on uminsi3, umaxsi3.

From-SVN: r9100
parent 02103577
...@@ -936,9 +936,9 @@ ...@@ -936,9 +936,9 @@
(define_expand "uminsi3" (define_expand "uminsi3"
[(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(const_int -2147483648))) (match_dup 5)))
(set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
(const_int -2147483648))) (match_dup 5)))
(set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
(const_int 0) (const_int 0)
(minus:SI (match_dup 4) (match_dup 3)))) (minus:SI (match_dup 4) (match_dup 3))))
...@@ -946,13 +946,17 @@ ...@@ -946,13 +946,17 @@
(minus:SI (match_dup 2) (match_dup 3)))] (minus:SI (match_dup 2) (match_dup 3)))]
"TARGET_POWER" "TARGET_POWER"
" "
{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") {
operands[3] = gen_reg_rtx (SImode);
operands[4] = gen_reg_rtx (SImode);
operands[5] = GEN_INT (-2147483647 - 1);
}")
(define_expand "umaxsi3" (define_expand "umaxsi3"
[(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(const_int -2147483648))) (match_dup 5)))
(set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
(const_int -2147483648))) (match_dup 5)))
(set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
(const_int 0) (const_int 0)
(minus:SI (match_dup 4) (match_dup 3)))) (minus:SI (match_dup 4) (match_dup 3))))
...@@ -960,7 +964,11 @@ ...@@ -960,7 +964,11 @@
(plus:SI (match_dup 3) (match_dup 1)))] (plus:SI (match_dup 3) (match_dup 1)))]
"TARGET_POWER" "TARGET_POWER"
" "
{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") {
operands[3] = gen_reg_rtx (SImode);
operands[4] = gen_reg_rtx (SImode);
operands[5] = GEN_INT (-2147483647 - 1);
}")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
......
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