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Commit ba1a78ff by Steve Ellcey
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aarch64-torture.exp: New file. 

2018-12-17  Steve Ellcey  <sellcey@cavium.com>

	* gcc.target/aarch64/torture/aarch64-torture.exp: New file.
	* gcc.target/aarch64/torture/simd-abi-1.c: New test.
	* gcc.target/aarch64/torture/simd-abi-2.c: Ditto.
	* gcc.target/aarch64/torture/simd-abi-3.c: Ditto.
	* gcc.target/aarch64/torture/simd-abi-4.c: Ditto.
	* gcc.target/aarch64/torture/simd-abi-5.c: Ditto.
	* gcc.target/aarch64/torture/simd-abi-6.c: Ditto.
	* gcc.target/aarch64/torture/simd-abi-7.c: Ditto.

From-SVN: r267209
parent a0d0b980
Showing with 253 additions and 0 deletions
gcc/testsuite/gcc.target/aarch64/torture/aarch64-torture.exp 0 → 100644
# Copyright (C) 2018 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
# optimization options.
# Exit immediately if this isn't a Aarch64 target.
if { ![istarget aarch64*-*-*] } then {
return
}
# Load support procs.
load_lib gcc-dg.exp
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
set DEFAULT_CFLAGS " -ansi -pedantic-errors"
}
# Initialize `dg'.
dg-init
# Main loop.
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] "" $DEFAULT_CFLAGS
# All done.
dg-finish
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-1.c 0 → 100644
/* { dg-do compile } */
void __attribute__ ((aarch64_vector_pcs))
f (void)
{
/* Clobber all fp/simd regs and verify that the correct ones are saved
and restored in the prologue and epilogue of a SIMD function. */
__asm__ __volatile__ ("" ::: "q0", "q1", "q2", "q3");
__asm__ __volatile__ ("" ::: "q4", "q5", "q6", "q7");
__asm__ __volatile__ ("" ::: "q8", "q9", "q10", "q11");
__asm__ __volatile__ ("" ::: "q12", "q13", "q14", "q15");
__asm__ __volatile__ ("" ::: "q16", "q17", "q18", "q19");
__asm__ __volatile__ ("" ::: "q20", "q21", "q22", "q23");
__asm__ __volatile__ ("" ::: "q24", "q25", "q26", "q27");
__asm__ __volatile__ ("" ::: "q28", "q29", "q30", "q31");
}
/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
/* { dg-final { scan-assembler {\sstp\tq10, q11} } } */
/* { dg-final { scan-assembler {\sstp\tq12, q13} } } */
/* { dg-final { scan-assembler {\sstp\tq14, q15} } } */
/* { dg-final { scan-assembler {\sstp\tq16, q17} } } */
/* { dg-final { scan-assembler {\sstp\tq18, q19} } } */
/* { dg-final { scan-assembler {\sstp\tq20, q21} } } */
/* { dg-final { scan-assembler {\sstp\tq22, q23} } } */
/* { dg-final { scan-assembler {\sldp\tq8, q9} } } */
/* { dg-final { scan-assembler {\sldp\tq10, q11} } } */
/* { dg-final { scan-assembler {\sldp\tq12, q13} } } */
/* { dg-final { scan-assembler {\sldp\tq14, q15} } } */
/* { dg-final { scan-assembler {\sldp\tq16, q17} } } */
/* { dg-final { scan-assembler {\sldp\tq18, q19} } } */
/* { dg-final { scan-assembler {\sldp\tq20, q21} } } */
/* { dg-final { scan-assembler {\sldp\tq22, q23} } } */
/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\td} } } */
/* { dg-final { scan-assembler-not {\sldp\td} } } */
/* { dg-final { scan-assembler-not {\sstr\t} } } */
/* { dg-final { scan-assembler-not {\sldr\t} } } */
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-2.c 0 → 100644
/* { dg-do compile } */
void
f (void)
{
/* Clobber all fp/simd regs and verify that the correct ones are saved
and restored in the prologue and epilogue of a normal non-SIMD function. */
__asm__ __volatile__ ("" ::: "q0", "q1", "q2", "q3");
__asm__ __volatile__ ("" ::: "q4", "q5", "q6", "q7");
__asm__ __volatile__ ("" ::: "q8", "q9", "q10", "q11");
__asm__ __volatile__ ("" ::: "q12", "q13", "q14", "q15");
__asm__ __volatile__ ("" ::: "q16", "q17", "q18", "q19");
__asm__ __volatile__ ("" ::: "q20", "q21", "q22", "q23");
__asm__ __volatile__ ("" ::: "q24", "q25", "q26", "q27");
__asm__ __volatile__ ("" ::: "q28", "q29", "q30", "q31");
}
/* { dg-final { scan-assembler {\sstp\td8, d9} } } */
/* { dg-final { scan-assembler {\sstp\td10, d11} } } */
/* { dg-final { scan-assembler {\sstp\td12, d13} } } */
/* { dg-final { scan-assembler {\sstp\td14, d15} } } */
/* { dg-final { scan-assembler {\sldp\td8, d9} } } */
/* { dg-final { scan-assembler {\sldp\td10, d11} } } */
/* { dg-final { scan-assembler {\sldp\td12, d13} } } */
/* { dg-final { scan-assembler {\sldp\td14, d15} } } */
/* { dg-final { scan-assembler-not {\sstp\tq} } } */
/* { dg-final { scan-assembler-not {\sldp\tq} } } */
/* { dg-final { scan-assembler-not {\sstp\tq[01234567]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq[01234567]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq1[6789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq1[6789]} } } */
/* { dg-final { scan-assembler-not {\sstr\t} } } */
/* { dg-final { scan-assembler-not {\sldr\t} } } */
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-3.c 0 → 100644
/* { dg-do compile } */
extern void g (void);
void __attribute__ ((aarch64_vector_pcs))
f (void)
{
g();
}
/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
/* { dg-final { scan-assembler {\sstp\tq10, q11} } } */
/* { dg-final { scan-assembler {\sstp\tq12, q13} } } */
/* { dg-final { scan-assembler {\sstp\tq14, q15} } } */
/* { dg-final { scan-assembler {\sstp\tq16, q17} } } */
/* { dg-final { scan-assembler {\sstp\tq18, q19} } } */
/* { dg-final { scan-assembler {\sstp\tq20, q21} } } */
/* { dg-final { scan-assembler {\sstp\tq22, q23} } } */
/* { dg-final { scan-assembler {\sldp\tq8, q9} } } */
/* { dg-final { scan-assembler {\sldp\tq10, q11} } } */
/* { dg-final { scan-assembler {\sldp\tq12, q13} } } */
/* { dg-final { scan-assembler {\sldp\tq14, q15} } } */
/* { dg-final { scan-assembler {\sldp\tq16, q17} } } */
/* { dg-final { scan-assembler {\sldp\tq18, q19} } } */
/* { dg-final { scan-assembler {\sldp\tq20, q21} } } */
/* { dg-final { scan-assembler {\sldp\tq22, q23} } } */
/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\td} } } */
/* { dg-final { scan-assembler-not {\sldp\td} } } */
/* { dg-final { scan-assembler-not {\sstr\t} } } */
/* { dg-final { scan-assembler-not {\sldr\t} } } */
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-4.c 0 → 100644
/* dg-do run */
/* { dg-additional-options "-std=c99" } */
/* There is nothing special about the calculations here, this is just
a test that can be compiled and run. */
extern void abort (void);
__Float64x2_t __attribute__ ((noinline, aarch64_vector_pcs))
foo(__Float64x2_t a, __Float64x2_t b, __Float64x2_t c,
__Float64x2_t d, __Float64x2_t e, __Float64x2_t f,
__Float64x2_t g, __Float64x2_t h, __Float64x2_t i)
{
__Float64x2_t w, x, y, z;
w = a + b * c;
x = d + e * f;
y = g + h * i;
return w + x * y;
}
int main()
{
__Float64x2_t a, b, c, d;
a = (__Float64x2_t) { 1.0, 2.0 };
b = (__Float64x2_t) { 3.0, 4.0 };
c = (__Float64x2_t) { 5.0, 6.0 };
d = foo (a, b, c, (a+b), (b+c), (a+c), (a-b), (b-c), (a-c)) + a + b + c;
if (d[0] != 337.0 || d[1] != 554.0)
abort ();
return 0;
}
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-5.c 0 → 100644
/* { dg-do compile } */
void __attribute__ ((aarch64_vector_pcs))
f (void)
{
/* Clobber some fp/simd regs and verify that only those are saved
and restored in the prologue and epilogue of a SIMD function. */
__asm__ __volatile__ ("" ::: "q8", "q9", "q10", "q11");
}
/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
/* { dg-final { scan-assembler {\sstp\tq10, q11} } } */
/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq1[23456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq1[23456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\td} } } */
/* { dg-final { scan-assembler-not {\sldp\td} } } */
/* { dg-final { scan-assembler-not {\sstr\t} } } */
/* { dg-final { scan-assembler-not {\sldr\t} } } */
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-6.c 0 → 100644
/* { dg-do compile } */
void __attribute__ ((aarch64_vector_pcs))
f (void)
{
/* Clobber some fp/simd regs and verify that only those are saved
and restored in the prologue and epilogue of a SIMD function. */
__asm__ __volatile__ ("" ::: "q8", "q10", "q11");
}
/* { dg-final { scan-assembler {\sstp\tq8, q10} } } */
/* { dg-final { scan-assembler {\sstr\tq11} } } */
/* { dg-final { scan-assembler-not {\sstp\tq[0345679]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq[0345679]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq1[123456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq1[123456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\td} } } */
/* { dg-final { scan-assembler-not {\sldp\td} } } */
/* { dg-final { scan-assembler-not {\sstr\tq[023456789]} } } */
/* { dg-final { scan-assembler-not {\sldr\tq[023456789]} } } */
/* { dg-final { scan-assembler-not {\sstr\tq1[023456789]} } } */
/* { dg-final { scan-assembler-not {\sldr\tq1[023456789]} } } */
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-7.c 0 → 100644
/* { dg-do compile } */
void __attribute__ ((aarch64_vector_pcs))
f (void)
{
/* Clobber some fp/simd regs and verify that only those are saved
and restored in the prologue and epilogue of a SIMD function. */
__asm__ __volatile__ ("" ::: "q8", "q9", "q11");
}
/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
/* { dg-final { scan-assembler {\sstr\tq11} } } */
/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq1[0123456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq1[0123456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
/* { dg-final { scan-assembler-not {\sstp\td} } } */
/* { dg-final { scan-assembler-not {\sldp\td} } } */
/* { dg-final { scan-assembler-not {\sstr\tq[023456789]} } } */
/* { dg-final { scan-assembler-not {\sldr\tq[023456789]} } } */
/* { dg-final { scan-assembler-not {\sstr\tq1[023456789]} } } */
/* { dg-final { scan-assembler-not {\sldr\tq1[023456789]} } } */
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