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Commit a0d0b980 by Steve Ellcey Committed by Steve Ellcey
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aarch64-protos.h (aarch64_use_simple_return_insn_p): New prototype. 

2018-12-17  Steve Ellcey  <sellcey@cavium.com>

	* config/aarch64/aarch64-protos.h (aarch64_use_simple_return_insn_p):
	New prototype.
	(aarch64_epilogue_uses): Ditto.
	* config/aarch64/aarch64.c (aarch64_attribute_table): New array.
	(aarch64_simd_decl_p): New function.
	(aarch64_reg_save_mode): New function.
	(aarch64_function_ok_for_sibcall): Check for simd calls.
	(aarch64_layout_frame): Check for simd function.
	(aarch64_gen_storewb_pair): Handle E_TFmode.
	(aarch64_push_regs): Use aarch64_reg_save_mode to get mode.
	(aarch64_gen_loadwb_pair): Handle E_TFmode.
	(aarch64_pop_regs): Use aarch64_reg_save_mode to get mode.
	(aarch64_gen_store_pair): Handle E_TFmode.
	(aarch64_gen_load_pair): Ditto.
	(aarch64_save_callee_saves): Handle different mode sizes.
	(aarch64_restore_callee_saves): Ditto.
	(aarch64_components_for_bb): Check for simd function.
	(aarch64_epilogue_uses): New function.
	(aarch64_process_components): Check for simd function.
	(aarch64_expand_prologue): Ditto.
	(aarch64_expand_epilogue): Ditto.
	(aarch64_expand_call): Ditto.
	(aarch64_use_simple_return_insn_p): New function.
	(TARGET_ATTRIBUTE_TABLE): New define.
	* config/aarch64/aarch64.h (EPILOGUE_USES): Redefine.
	(FP_SIMD_SAVED_REGNUM_P): New macro.
	* config/aarch64/aarch64.md (simple_return): New define_expand.
	(load_pair_dw_tftf): New instruction.
	(store_pair_dw_tftf): Ditto.
	(loadwb_pair<TX:mode>_<P:mode>): Ditto.
	(storewb_pair<TX:mode>_<P:mode>): Ditto.

From-SVN: r267208
parent 4d814b69
Showing with 104 additions and 8 deletions
gcc/ChangeLog
2018-12-17 Steve Ellcey <sellcey@cavium.com>
* config/aarch64/aarch64-protos.h (aarch64_use_simple_return_insn_p):
New prototype.
(aarch64_epilogue_uses): Ditto.
* config/aarch64/aarch64.c (aarch64_attribute_table): New array.
(aarch64_simd_decl_p): New function.
(aarch64_reg_save_mode): New function.
(aarch64_function_ok_for_sibcall): Check for simd calls.
(aarch64_layout_frame): Check for simd function.
(aarch64_gen_storewb_pair): Handle E_TFmode.
(aarch64_push_regs): Use aarch64_reg_save_mode to get mode.
(aarch64_gen_loadwb_pair): Handle E_TFmode.
(aarch64_pop_regs): Use aarch64_reg_save_mode to get mode.
(aarch64_gen_store_pair): Handle E_TFmode.
(aarch64_gen_load_pair): Ditto.
(aarch64_save_callee_saves): Handle different mode sizes.
(aarch64_restore_callee_saves): Ditto.
(aarch64_components_for_bb): Check for simd function.
(aarch64_epilogue_uses): New function.
(aarch64_process_components): Check for simd function.
(aarch64_expand_prologue): Ditto.
(aarch64_expand_epilogue): Ditto.
(aarch64_expand_call): Ditto.
(aarch64_use_simple_return_insn_p): New function.
(TARGET_ATTRIBUTE_TABLE): New define.
* config/aarch64/aarch64.h (EPILOGUE_USES): Redefine.
(FP_SIMD_SAVED_REGNUM_P): New macro.
* config/aarch64/aarch64.md (simple_return): New define_expand.
(load_pair_dw_tftf): New instruction.
(store_pair_dw_tftf): Ditto.
(loadwb_pair<TX:mode>_<P:mode>): Ditto.
(storewb_pair<TX:mode>_<P:mode>): Ditto.
2018-12-17 Uros Bizjak <ubizjak@gmail.com> 2018-12-17 Uros Bizjak <ubizjak@gmail.com>
PR target/88502 PR target/88502
gcc/config/aarch64/aarch64-protos.h
...@@ -471,6 +471,7 @@ bool aarch64_split_dimode_const_store (rtx, rtx); ...@@ -471,6 +471,7 @@ bool aarch64_split_dimode_const_store (rtx, rtx);
bool aarch64_symbolic_address_p (rtx); bool aarch64_symbolic_address_p (rtx);
bool aarch64_uimm12_shift (HOST_WIDE_INT); bool aarch64_uimm12_shift (HOST_WIDE_INT);
bool aarch64_use_return_insn_p (void); bool aarch64_use_return_insn_p (void);
bool aarch64_use_simple_return_insn_p (void);
const char *aarch64_mangle_builtin_type (const_tree); const char *aarch64_mangle_builtin_type (const_tree);
const char *aarch64_output_casesi (rtx *); const char *aarch64_output_casesi (rtx *);
...@@ -556,6 +557,8 @@ void aarch64_split_simd_move (rtx, rtx); ...@@ -556,6 +557,8 @@ void aarch64_split_simd_move (rtx, rtx);
/* Check for a legitimate floating point constant for FMOV. */ /* Check for a legitimate floating point constant for FMOV. */
bool aarch64_float_const_representable_p (rtx); bool aarch64_float_const_representable_p (rtx);
extern int aarch64_epilogue_uses (int);
#if defined (RTX_CODE) #if defined (RTX_CODE)
void aarch64_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode, void aarch64_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
rtx label_ref); rtx label_ref);
......
gcc/config/aarch64/aarch64.h
...@@ -409,13 +409,7 @@ extern unsigned aarch64_architecture_version; ...@@ -409,13 +409,7 @@ extern unsigned aarch64_architecture_version;
V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \
} }
/* Say that the return address register is used by the epilogue, but only after #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO))
epilogue generation is complete. Note that in the case of sibcalls, the
values "used by the epilogue" are considered live at the start of the called
function. */
#define EPILOGUE_USES(REGNO) \
(epilogue_completed && (REGNO) == LR_REGNUM)
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. This is only true if the function the stack pointer does not matter. This is only true if the function
...@@ -523,6 +517,8 @@ extern unsigned aarch64_architecture_version; ...@@ -523,6 +517,8 @@ extern unsigned aarch64_architecture_version;
#define PR_LO_REGNUM_P(REGNO)\ #define PR_LO_REGNUM_P(REGNO)\
(((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM))
#define FP_SIMD_SAVED_REGNUM_P(REGNO) \
(((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM))
/* Register and constant classes. */ /* Register and constant classes. */
......
gcc/config/aarch64/aarch64.md
...@@ -727,7 +727,7 @@ ...@@ -727,7 +727,7 @@
(define_insn "simple_return" (define_insn "simple_return"
[(simple_return)] [(simple_return)]
"" "aarch64_use_simple_return_insn_p ()"
"ret" "ret"
[(set_attr "type" "branch")] [(set_attr "type" "branch")]
) )
...@@ -1387,6 +1387,21 @@ ...@@ -1387,6 +1387,21 @@
(set_attr "arch" "*,fp")] (set_attr "arch" "*,fp")]
) )
(define_insn "load_pair_dw_tftf"
[(set (match_operand:TF 0 "register_operand" "=w")
(match_operand:TF 1 "aarch64_mem_pair_operand" "Ump"))
(set (match_operand:TF 2 "register_operand" "=w")
(match_operand:TF 3 "memory_operand" "m"))]
"TARGET_SIMD
&& rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
XEXP (operands[1], 0),
GET_MODE_SIZE (TFmode)))"
"ldp\\t%q0, %q2, %1"
[(set_attr "type" "neon_ldp_q")
(set_attr "fp" "yes")]
)
;; Operands 0 and 2 are tied together by the final condition; so we allow ;; Operands 0 and 2 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation. ;; fairly lax checking on the second memory operation.
(define_insn "store_pair_sw_<SX:mode><SX2:mode>" (define_insn "store_pair_sw_<SX:mode><SX2:mode>"
...@@ -1422,6 +1437,21 @@ ...@@ -1422,6 +1437,21 @@
(set_attr "arch" "*,fp")] (set_attr "arch" "*,fp")]
) )
(define_insn "store_pair_dw_tftf"
[(set (match_operand:TF 0 "aarch64_mem_pair_operand" "=Ump")
(match_operand:TF 1 "register_operand" "w"))
(set (match_operand:TF 2 "memory_operand" "=m")
(match_operand:TF 3 "register_operand" "w"))]
"TARGET_SIMD &&
rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
GET_MODE_SIZE (TFmode)))"
"stp\\t%q1, %q3, %0"
[(set_attr "type" "neon_stp_q")
(set_attr "fp" "yes")]
)
;; Load pair with post-index writeback. This is primarily used in function ;; Load pair with post-index writeback. This is primarily used in function
;; epilogues. ;; epilogues.
(define_insn "loadwb_pair<GPI:mode>_<P:mode>" (define_insn "loadwb_pair<GPI:mode>_<P:mode>"
...@@ -1454,6 +1484,21 @@ ...@@ -1454,6 +1484,21 @@
[(set_attr "type" "neon_load1_2reg")] [(set_attr "type" "neon_load1_2reg")]
) )
(define_insn "loadwb_pair<TX:mode>_<P:mode>"
[(parallel
[(set (match_operand:P 0 "register_operand" "=k")
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (match_operand:TX 2 "register_operand" "=w")
(mem:TX (match_dup 1)))
(set (match_operand:TX 3 "register_operand" "=w")
(mem:TX (plus:P (match_dup 1)
(match_operand:P 5 "const_int_operand" "n"))))])]
"TARGET_SIMD && INTVAL (operands[5]) == GET_MODE_SIZE (<TX:MODE>mode)"
"ldp\\t%q2, %q3, [%1], %4"
[(set_attr "type" "neon_ldp_q")]
)
;; Store pair with pre-index writeback. This is primarily used in function ;; Store pair with pre-index writeback. This is primarily used in function
;; prologues. ;; prologues.
(define_insn "storewb_pair<GPI:mode>_<P:mode>" (define_insn "storewb_pair<GPI:mode>_<P:mode>"
...@@ -1488,6 +1533,24 @@ ...@@ -1488,6 +1533,24 @@
[(set_attr "type" "neon_store1_2reg<q>")] [(set_attr "type" "neon_store1_2reg<q>")]
) )
(define_insn "storewb_pair<TX:mode>_<P:mode>"
[(parallel
[(set (match_operand:P 0 "register_operand" "=&k")
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (mem:TX (plus:P (match_dup 0)
(match_dup 4)))
(match_operand:TX 2 "register_operand" "w"))
(set (mem:TX (plus:P (match_dup 0)
(match_operand:P 5 "const_int_operand" "n")))
(match_operand:TX 3 "register_operand" "w"))])]
"TARGET_SIMD
&& INTVAL (operands[5])
== INTVAL (operands[4]) + GET_MODE_SIZE (<TX:MODE>mode)"
"stp\\t%q2, %q3, [%0, %4]!"
[(set_attr "type" "neon_stp_q")]
)
;; ------------------------------------------------------------------- ;; -------------------------------------------------------------------
;; Sign/Zero extension ;; Sign/Zero extension
;; ------------------------------------------------------------------- ;; -------------------------------------------------------------------
......
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