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riscv-gcc-1
Commit a46c7e85 by Richard Earnshaw Committed by Richard Earnshaw
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* arm.md (movhi): REGNO_POINTER_ALIGN is now bits. 

From-SVN: r33163
parent 624c87aa
Showing with 4 additions and 2 deletions
gcc/ChangeLog
...@@ -3,6 +3,8 @@ ...@@ -3,6 +3,8 @@
* emit-rtl.c (unshare_all_rtl_again): Unmark everything, then * emit-rtl.c (unshare_all_rtl_again): Unmark everything, then
call unshare_all_rtl. call unshare_all_rtl.
* arm.md (movhi): REGNO_POINTER_ALIGN is now bits.
Fri Apr 14 16:58:45 2000 Jim Wilson <wilson@cygnus.com> Fri Apr 14 16:58:45 2000 Jim Wilson <wilson@cygnus.com>
* config/ia64/lib1funcs.asm (__divdi3, __moddi3, __udivdi3, __umoddi3): * config/ia64/lib1funcs.asm (__divdi3, __moddi3, __udivdi3, __umoddi3):
......
gcc/config/arm/arm.md
...@@ -4193,7 +4193,7 @@ ...@@ -4193,7 +4193,7 @@
&& GET_CODE (offset = XEXP (base, 1)) == CONST_INT && GET_CODE (offset = XEXP (base, 1)) == CONST_INT
&& ((INTVAL(offset) & 1) != 1) && ((INTVAL(offset) & 1) != 1)
&& GET_CODE (base = XEXP (base, 0)) == REG)) && GET_CODE (base = XEXP (base, 0)) == REG))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 4) && REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{ {
HOST_WIDE_INT new_offset = INTVAL (offset) & ~3; HOST_WIDE_INT new_offset = INTVAL (offset) & ~3;
rtx new; rtx new;
...@@ -4226,7 +4226,7 @@ ...@@ -4226,7 +4226,7 @@
|| (GET_CODE (base) == PLUS || (GET_CODE (base) == PLUS
&& GET_CODE (offset = XEXP (base, 1)) == CONST_INT && GET_CODE (offset = XEXP (base, 1)) == CONST_INT
&& GET_CODE (base = XEXP (base, 0)) == REG)) && GET_CODE (base = XEXP (base, 0)) == REG))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 4) && REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
rtx new; rtx new;
......
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