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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
a46c7e85
Commit
a46c7e85
authored
Apr 15, 2000
by
Richard Earnshaw
Committed by
Richard Earnshaw
Apr 15, 2000
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* arm.md (movhi): REGNO_POINTER_ALIGN is now bits.
From-SVN: r33163
parent
624c87aa
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gcc/ChangeLog
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gcc/ChangeLog
View file @
a46c7e85
...
...
@@ -3,6 +3,8 @@
*
emit
-
rtl
.
c
(
unshare_all_rtl_again
)
:
Unmark
everything
,
then
call
unshare_all_rtl
.
*
arm
.
md
(
movhi
)
:
REGNO_POINTER_ALIGN
is
now
bits
.
Fri
Apr
14
16
:
58
:
45
2000
Jim
Wilson
<
wilson
@cygnus
.
com
>
*
config
/
ia64
/
lib1funcs
.
asm
(
__divdi3
,
__moddi3
,
__udivdi3
,
__umoddi3
)
:
...
...
gcc/config/arm/arm.md
View file @
a46c7e85
...
...
@@ -4193,7 +4193,7 @@
&& GET_CODE (offset = XEXP (base, 1)) == CONST_INT
&& ((INTVAL(offset) & 1) != 1)
&& GET_CODE (base = XEXP (base, 0)) == REG))
&& REGNO_POINTER_ALIGN (REGNO (base)) >=
4
)
&& REGNO_POINTER_ALIGN (REGNO (base)) >=
32
)
{
HOST_WIDE_INT new_offset = INTVAL (offset) & ~3;
rtx new;
...
...
@@ -4226,7 +4226,7 @@
|| (GET_CODE (base) == PLUS
&& GET_CODE (offset = XEXP (base, 1)) == CONST_INT
&& GET_CODE (base = XEXP (base, 0)) == REG))
&& REGNO_POINTER_ALIGN (REGNO (base)) >=
4
)
&& REGNO_POINTER_ALIGN (REGNO (base)) >=
32
)
{
rtx reg = gen_reg_rtx (SImode);
rtx new;
...
...
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