power9.md (power9-alu): Remove 'cmp' type and add define_bypass for CR latency.

	* config/rs6000/power9.md (power9-alu): Remove 'cmp' type and add
	define_bypass for CR latency.
	(power9-cracked-alu): Update bypass latency and remove power9-branch.
	(power9-alu2): Add define_bypass for CR latency.
	(power9-cmp): New.
	(power9-mul): Update insn latency.
	(power9-mul-compare): Update insn latency, bypass latency and remove
	power9-branch.

From-SVN: r244645

gcc/ChangeLog

+2017-01-19  Pat Haugen  <pthaugen@us.ibm.com>
+
+	* config/rs6000/power9.md (power9-alu): Remove 'cmp' type and add
+	define_bypass for CR latency.
+	(power9-cracked-alu): Update bypass latency and remove power9-branch.
+	(power9-alu2): Add define_bypass for CR latency.
+	(power9-cmp): New.
+	(power9-mul): Update insn latency.
+	(power9-mul-compare): Update insn latency, bypass latency and remove
+	power9-branch.
+
 2016-01-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/aarch64-protos.h (aarch64_nopcrelative_literal_loads):

gcc/config/rs6000/power9.md

@@ -243,11 +243,14 @@
 
 ; Most ALU insns are simple 2 cycle, including record form
 (define_insn_reservation "power9-alu" 2
-  (and (ior (eq_attr "type" "add,cmp,exts,integer,logical,isel")
+  (and (ior (eq_attr "type" "add,exts,integer,logical,isel")
 	    (and (eq_attr "type" "insert,shift")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "power9"))
   "DU_any_power9,VSU_power9")
+; 5 cycle CR latency
+(define_bypass 5 "power9-alu"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
 
 ; Record form rotate/shift are cracked
 (define_insn_reservation "power9-cracked-alu" 2
@@ -255,14 +258,23 @@
        (eq_attr "dot" "yes")
        (eq_attr "cpu" "power9"))
   "DU_C2_power9,VSU_power9")
-; 4 cycle CR latency
-(define_bypass 4 "power9-cracked-alu"
-		 "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch")
+; 7 cycle CR latency
+(define_bypass 7 "power9-cracked-alu"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
 
 (define_insn_reservation "power9-alu2" 3
   (and (eq_attr "type" "cntlz,popcnt,trap")
        (eq_attr "cpu" "power9"))
   "DU_any_power9,VSU_power9")
+; 6 cycle CR latency
+(define_bypass 6 "power9-alu2"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
+
+(define_insn_reservation "power9-cmp" 2
+  (and (eq_attr "type" "cmp")
+       (eq_attr "cpu" "power9"))
+  "DU_any_power9,VSU_power9")
+
 
 ; Treat 'two' and 'three' types as 2 or 3 way cracked
 (define_insn_reservation "power9-two" 4
@@ -275,20 +287,20 @@
        (eq_attr "cpu" "power9"))
   "DU_C3_power9,VSU_power9")
 
-(define_insn_reservation "power9-mul" 4
+(define_insn_reservation "power9-mul" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "no")
        (eq_attr "cpu" "power9"))
   "DU_any_power9,VSU_power9")
 
-(define_insn_reservation "power9-mul-compare" 4
+(define_insn_reservation "power9-mul-compare" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "yes")
        (eq_attr "cpu" "power9"))
   "DU_C2_power9,VSU_power9")
-; 6 cycle CR latency
-(define_bypass 6 "power9-mul-compare"
-		 "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch")
+; 10 cycle CR latency
+(define_bypass 10 "power9-mul-compare"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
 
 ; Fixed point divides reserve the divide units for a minimum of 8 cycles
 (define_insn_reservation "power9-idiv" 16