Commit 16a34ca6 by Uros Bizjak Committed by Uros Bizjak

target.h (htm_available): Determine vendor from __get_cpuid_max return.

	* config/x86/target.h (htm_available): Determine vendor from
	__get_cpuid_max return.  Use signature_INTEL_ebx.  Cleanup.

From-SVN: r244644
parent 197d1c09
2017-01-19 Uros Bizjak <ubizjak@gmail.com>
* config/x86/target.h (htm_available): Determine vendor from
__get_cpuid_max return. Use signature_INTEL_ebx. Cleanup.
2017-01-18 Torvald Riegel <triegel@redhat.com> 2017-01-18 Torvald Riegel <triegel@redhat.com>
* config/x86/target.h (htm_available): Add check for some processors * config/x86/target.h (htm_available): Add check for some processors
......
...@@ -75,31 +75,32 @@ static inline bool ...@@ -75,31 +75,32 @@ static inline bool
htm_available () htm_available ()
{ {
const unsigned cpuid_rtm = bit_RTM; const unsigned cpuid_rtm = bit_RTM;
if (__get_cpuid_max (0, NULL) >= 7) unsigned vendor;
if (__get_cpuid_max (0, &vendor) >= 7)
{ {
unsigned a, b, c, d; unsigned a, b, c, d;
/* TSX is broken on some processors. This can be fixed by microcode, unsigned family;
__cpuid (1, a, b, c, d);
family = (a >> 8) & 0x0f;
/* TSX is broken on some processors. TSX can be disabled by microcode,
but we cannot reliably detect whether the microcode has been but we cannot reliably detect whether the microcode has been
updated. Therefore, do not report availability of TSX on these updated. Therefore, do not report availability of TSX on these
processors. We use the same approach here as in glibc (see processors. We use the same approach here as in glibc (see
https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html). */ https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html). */
__cpuid (0, a, b, c, d); if (vendor == signature_INTEL_ebx && family == 0x06)
if (b == 0x756e6547 && c == 0x6c65746e && d == 0x49656e69)
{ {
__cpuid (1, a, b, c, d); unsigned model = ((a >> 4) & 0x0f) + ((a >> 12) & 0xf0);
if (((a >> 8) & 0x0f) == 0x06) // Family. unsigned stepping = a & 0x0f;
{ if (model == 0x3c
unsigned model = ((a >> 4) & 0x0f) // Model. /* Xeon E7 v3 has correct TSX if stepping >= 4. */
+ ((a >> 12) & 0xf0); // Extended model. || (model == 0x3f && stepping < 4)
unsigned stepping = a & 0x0f; || model == 0x45
if ((model == 0x3c) || model == 0x46)
|| (model == 0x45) return false;
|| (model == 0x46)
/* Xeon E7 v3 has correct TSX if stepping >= 4. */
|| ((model == 0x3f) && (stepping < 4)))
return false;
}
} }
__cpuid_count (7, 0, a, b, c, d); __cpuid_count (7, 0, a, b, c, d);
if (b & cpuid_rtm) if (b & cpuid_rtm)
return true; return true;
......
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