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riscv-gcc-1
Commit 7a5fffa5 by Srinath Parvathaneni Committed by Kyrylo Tkachov
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[ARM][GCC][8/5x]: Remaining MVE store intrinsics which stores an half word, word… 

[ARM][GCC][8/5x]: Remaining MVE store intrinsics which stores an half word, word and double word to memory.

This patch supports the following MVE ACLE store intrinsics which stores an halfword, word or double word to memory.

vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64,
vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64,
vstrdq_scatter_shifted_offset_u64, vstrhq_scatter_offset_f16, vstrhq_scatter_offset_p_f16, vstrhq_scatter_shifted_offset_f16, vstrhq_scatter_shifted_offset_p_f16,
vstrwq_scatter_base_f32, vstrwq_scatter_base_p_f32, vstrwq_scatter_offset_f32, vstrwq_scatter_offset_p_f32, vstrwq_scatter_offset_p_s32, vstrwq_scatter_offset_p_u32, vstrwq_scatter_offset_s32, vstrwq_scatter_offset_u32, vstrwq_scatter_shifted_offset_f32,
vstrwq_scatter_shifted_offset_p_f32, vstrwq_scatter_shifted_offset_p_s32,
vstrwq_scatter_shifted_offset_p_u32, vstrwq_scatter_shifted_offset_s32,
vstrwq_scatter_shifted_offset_u32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1]  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

In this patch a new predicate "Ri" is defined to check the immediate is in the range of +/-1016 and multiple of 8.

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
	(vstrdq_scatter_base_p_u64): Likewise.
	(vstrdq_scatter_base_s64): Likewise.
	(vstrdq_scatter_base_u64): Likewise.
	(vstrdq_scatter_offset_p_s64): Likewise.
	(vstrdq_scatter_offset_p_u64): Likewise.
	(vstrdq_scatter_offset_s64): Likewise.
	(vstrdq_scatter_offset_u64): Likewise.
	(vstrdq_scatter_shifted_offset_p_s64): Likewise.
	(vstrdq_scatter_shifted_offset_p_u64): Likewise.
	(vstrdq_scatter_shifted_offset_s64): Likewise.
	(vstrdq_scatter_shifted_offset_u64): Likewise.
	(vstrhq_scatter_offset_f16): Likewise.
	(vstrhq_scatter_offset_p_f16): Likewise.
	(vstrhq_scatter_shifted_offset_f16): Likewise.
	(vstrhq_scatter_shifted_offset_p_f16): Likewise.
	(vstrwq_scatter_base_f32): Likewise.
	(vstrwq_scatter_base_p_f32): Likewise.
	(vstrwq_scatter_offset_f32): Likewise.
	(vstrwq_scatter_offset_p_f32): Likewise.
	(vstrwq_scatter_offset_p_s32): Likewise.
	(vstrwq_scatter_offset_p_u32): Likewise.
	(vstrwq_scatter_offset_s32): Likewise.
	(vstrwq_scatter_offset_u32): Likewise.
	(vstrwq_scatter_shifted_offset_f32): Likewise.
	(vstrwq_scatter_shifted_offset_p_f32): Likewise.
	(vstrwq_scatter_shifted_offset_p_s32): Likewise.
	(vstrwq_scatter_shifted_offset_p_u32): Likewise.
	(vstrwq_scatter_shifted_offset_s32): Likewise.
	(vstrwq_scatter_shifted_offset_u32): Likewise.
	(__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
	(__arm_vstrdq_scatter_base_p_u64): Likewise.
	(__arm_vstrdq_scatter_base_s64): Likewise.
	(__arm_vstrdq_scatter_base_u64): Likewise.
	(__arm_vstrdq_scatter_offset_p_s64): Likewise.
	(__arm_vstrdq_scatter_offset_p_u64): Likewise.
	(__arm_vstrdq_scatter_offset_s64): Likewise.
	(__arm_vstrdq_scatter_offset_u64): Likewise.
	(__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
	(__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
	(__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
	(__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
	(__arm_vstrwq_scatter_offset_p_s32): Likewise.
	(__arm_vstrwq_scatter_offset_p_u32): Likewise.
	(__arm_vstrwq_scatter_offset_s32): Likewise.
	(__arm_vstrwq_scatter_offset_u32): Likewise.
	(__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
	(__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
	(__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
	(__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
	(__arm_vstrhq_scatter_offset_f16): Likewise.
	(__arm_vstrhq_scatter_offset_p_f16): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
	(__arm_vstrwq_scatter_base_f32): Likewise.
	(__arm_vstrwq_scatter_base_p_f32): Likewise.
	(__arm_vstrwq_scatter_offset_f32): Likewise.
	(__arm_vstrwq_scatter_offset_p_f32): Likewise.
	(__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
	(__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
	(vstrhq_scatter_offset): Define polymorphic variant.
	(vstrhq_scatter_offset_p): Likewise.
	(vstrhq_scatter_shifted_offset): Likewise.
	(vstrhq_scatter_shifted_offset_p): Likewise.
	(vstrwq_scatter_base): Likewise.
	(vstrwq_scatter_base_p): Likewise.
	(vstrwq_scatter_offset): Likewise.
	(vstrwq_scatter_offset_p): Likewise.
	(vstrwq_scatter_shifted_offset): Likewise.
	(vstrwq_scatter_shifted_offset_p): Likewise.
	(vstrdq_scatter_base_p): Likewise.
	(vstrdq_scatter_base): Likewise.
	(vstrdq_scatter_offset_p): Likewise.
	(vstrdq_scatter_offset): Likewise.
	(vstrdq_scatter_shifted_offset_p): Likewise.
	(vstrdq_scatter_shifted_offset): Likewise.
	* config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
	(STRSBS_P): Likewise.
	(STRSBU): Likewise.
	(STRSBU_P): Likewise.
	(STRSS): Likewise.
	(STRSS_P): Likewise.
	(STRSU): Likewise.
	(STRSU_P): Likewise.
	* config/arm/constraints.md (Ri): Define.
	* config/arm/mve.md (VSTRDSBQ): Define iterator.
	(VSTRDSOQ): Likewise.
	(VSTRDSSOQ): Likewise.
	(VSTRWSOQ): Likewise.
	(VSTRWSSOQ): Likewise.
	(mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
	(mve_vstrdq_scatter_base_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
	(mve_vstrhq_scatter_offset_fv8hf): Likewise.
	(mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
	(mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
	(mve_vstrwq_scatter_base_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_offset_fv4sf): Likewise.
	(mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
	* config/arm/predicates.md (Ri): Define predicate to check immediate
	is the range +/-1016 and multiple of 8.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: New test.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c:
	Likewise.
parent 5cad47e0
Showing with 867 additions and 1 deletions
gcc/ChangeLog
......@@ -2,6 +2,123 @@
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
(vstrdq_scatter_base_p_u64): Likewise.
(vstrdq_scatter_base_s64): Likewise.
(vstrdq_scatter_base_u64): Likewise.
(vstrdq_scatter_offset_p_s64): Likewise.
(vstrdq_scatter_offset_p_u64): Likewise.
(vstrdq_scatter_offset_s64): Likewise.
(vstrdq_scatter_offset_u64): Likewise.
(vstrdq_scatter_shifted_offset_p_s64): Likewise.
(vstrdq_scatter_shifted_offset_p_u64): Likewise.
(vstrdq_scatter_shifted_offset_s64): Likewise.
(vstrdq_scatter_shifted_offset_u64): Likewise.
(vstrhq_scatter_offset_f16): Likewise.
(vstrhq_scatter_offset_p_f16): Likewise.
(vstrhq_scatter_shifted_offset_f16): Likewise.
(vstrhq_scatter_shifted_offset_p_f16): Likewise.
(vstrwq_scatter_base_f32): Likewise.
(vstrwq_scatter_base_p_f32): Likewise.
(vstrwq_scatter_offset_f32): Likewise.
(vstrwq_scatter_offset_p_f32): Likewise.
(vstrwq_scatter_offset_p_s32): Likewise.
(vstrwq_scatter_offset_p_u32): Likewise.
(vstrwq_scatter_offset_s32): Likewise.
(vstrwq_scatter_offset_u32): Likewise.
(vstrwq_scatter_shifted_offset_f32): Likewise.
(vstrwq_scatter_shifted_offset_p_f32): Likewise.
(vstrwq_scatter_shifted_offset_p_s32): Likewise.
(vstrwq_scatter_shifted_offset_p_u32): Likewise.
(vstrwq_scatter_shifted_offset_s32): Likewise.
(vstrwq_scatter_shifted_offset_u32): Likewise.
(__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
(__arm_vstrdq_scatter_base_p_u64): Likewise.
(__arm_vstrdq_scatter_base_s64): Likewise.
(__arm_vstrdq_scatter_base_u64): Likewise.
(__arm_vstrdq_scatter_offset_p_s64): Likewise.
(__arm_vstrdq_scatter_offset_p_u64): Likewise.
(__arm_vstrdq_scatter_offset_s64): Likewise.
(__arm_vstrdq_scatter_offset_u64): Likewise.
(__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
(__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
(__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
(__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
(__arm_vstrwq_scatter_offset_p_s32): Likewise.
(__arm_vstrwq_scatter_offset_p_u32): Likewise.
(__arm_vstrwq_scatter_offset_s32): Likewise.
(__arm_vstrwq_scatter_offset_u32): Likewise.
(__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
(__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
(__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
(__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
(__arm_vstrhq_scatter_offset_f16): Likewise.
(__arm_vstrhq_scatter_offset_p_f16): Likewise.
(__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
(__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
(__arm_vstrwq_scatter_base_f32): Likewise.
(__arm_vstrwq_scatter_base_p_f32): Likewise.
(__arm_vstrwq_scatter_offset_f32): Likewise.
(__arm_vstrwq_scatter_offset_p_f32): Likewise.
(__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
(__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
(vstrhq_scatter_offset): Define polymorphic variant.
(vstrhq_scatter_offset_p): Likewise.
(vstrhq_scatter_shifted_offset): Likewise.
(vstrhq_scatter_shifted_offset_p): Likewise.
(vstrwq_scatter_base): Likewise.
(vstrwq_scatter_base_p): Likewise.
(vstrwq_scatter_offset): Likewise.
(vstrwq_scatter_offset_p): Likewise.
(vstrwq_scatter_shifted_offset): Likewise.
(vstrwq_scatter_shifted_offset_p): Likewise.
(vstrdq_scatter_base_p): Likewise.
(vstrdq_scatter_base): Likewise.
(vstrdq_scatter_offset_p): Likewise.
(vstrdq_scatter_offset): Likewise.
(vstrdq_scatter_shifted_offset_p): Likewise.
(vstrdq_scatter_shifted_offset): Likewise.
* config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
(STRSBS_P): Likewise.
(STRSBU): Likewise.
(STRSBU_P): Likewise.
(STRSS): Likewise.
(STRSS_P): Likewise.
(STRSU): Likewise.
(STRSU_P): Likewise.
* config/arm/constraints.md (Ri): Define.
* config/arm/mve.md (VSTRDSBQ): Define iterator.
(VSTRDSOQ): Likewise.
(VSTRDSSOQ): Likewise.
(VSTRWSOQ): Likewise.
(VSTRWSSOQ): Likewise.
(mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
(mve_vstrdq_scatter_base_<supf>v2di): Likewise.
(mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
(mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
(mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
(mve_vstrhq_scatter_offset_fv8hf): Likewise.
(mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
(mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
(mve_vstrwq_scatter_base_fv4sf): Likewise.
(mve_vstrwq_scatter_base_p_fv4sf): Likewise.
(mve_vstrwq_scatter_offset_fv4sf): Likewise.
(mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
(mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
(mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
(mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
(mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
* config/arm/predicates.md (Ri): Define predicate to check immediate
is the range +/-1016 and multiple of 8.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vst1q_f32): Define macro.
(vst1q_f16): Likewise.
(vst1q_s8): Likewise.
......
gcc/config/arm/arm_mve_builtins.def
......@@ -785,3 +785,33 @@ VAR1 (STRU, vstrwq_u, v4si)
VAR1 (STRS_P, vstrwq_p_f, v4sf)
VAR1 (STRS_P, vstrwq_p_s, v4si)
VAR1 (STRU_P, vstrwq_p_u, v4si)
VAR1 (STRSBS, vstrdq_scatter_base_s, v2di)
VAR1 (STRSBS, vstrwq_scatter_base_f, v4sf)
VAR1 (STRSBS_P, vstrdq_scatter_base_p_s, v2di)
VAR1 (STRSBS_P, vstrwq_scatter_base_p_f, v4sf)
VAR1 (STRSBU, vstrdq_scatter_base_u, v2di)
VAR1 (STRSBU_P, vstrdq_scatter_base_p_u, v2di)
VAR1 (STRSS, vstrdq_scatter_offset_s, v2di)
VAR1 (STRSS, vstrdq_scatter_shifted_offset_s, v2di)
VAR1 (STRSS, vstrhq_scatter_offset_f, v8hf)
VAR1 (STRSS, vstrhq_scatter_shifted_offset_f, v8hf)
VAR1 (STRSS, vstrwq_scatter_offset_f, v4sf)
VAR1 (STRSS, vstrwq_scatter_offset_s, v4si)
VAR1 (STRSS, vstrwq_scatter_shifted_offset_f, v4sf)
VAR1 (STRSS, vstrwq_scatter_shifted_offset_s, v4si)
VAR1 (STRSS_P, vstrdq_scatter_offset_p_s, v2di)
VAR1 (STRSS_P, vstrdq_scatter_shifted_offset_p_s, v2di)
VAR1 (STRSS_P, vstrhq_scatter_offset_p_f, v8hf)
VAR1 (STRSS_P, vstrhq_scatter_shifted_offset_p_f, v8hf)
VAR1 (STRSS_P, vstrwq_scatter_offset_p_f, v4sf)
VAR1 (STRSS_P, vstrwq_scatter_offset_p_s, v4si)
VAR1 (STRSS_P, vstrwq_scatter_shifted_offset_p_f, v4sf)
VAR1 (STRSS_P, vstrwq_scatter_shifted_offset_p_s, v4si)
VAR1 (STRSU, vstrdq_scatter_offset_u, v2di)
VAR1 (STRSU, vstrdq_scatter_shifted_offset_u, v2di)
VAR1 (STRSU, vstrwq_scatter_offset_u, v4si)
VAR1 (STRSU, vstrwq_scatter_shifted_offset_u, v4si)
VAR1 (STRSU_P, vstrdq_scatter_offset_p_u, v2di)
VAR1 (STRSU_P, vstrdq_scatter_shifted_offset_p_u, v2di)
VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si)
VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si)
gcc/config/arm/constraints.md
......@@ -35,7 +35,7 @@
;; Dt, Dp, Dz, Tu
;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra,
;; Rg
;; Rg, Ri
;; in all states: Pf, Pg
;; The following memory constraints have been used:
......@@ -90,6 +90,10 @@
(match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
|| (ival == 4) || (ival == 8))")))
;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
(define_predicate "mve_vldrd_immediate"
(match_test "satisfies_constraint_Ri (op)"))
(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
"The VFP registers @code{s0}-@code{s31}.")
......
gcc/config/arm/predicates.md
......@@ -59,6 +59,14 @@
(define_predicate "mve_imm_selective_upto_8"
(match_test "satisfies_constraint_Rg (op)"))
;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
(define_constraint "Ri"
"@internal In Thumb-2 state a constant is multiple of 8 and in range
of -/+ 1016 for MVE"
(and (match_code "const_int")
(match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
&& ((ival % 8) == 0)")))
; Predicate for stack protector guard's address in
; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
(define_predicate "guard_addr_operand"
......
gcc/testsuite/ChangeLog
......@@ -2,6 +2,53 @@
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: New test.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c:
Likewise.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_base_p_s64 (addr, 8, value, p);
}
/* { dg-final { scan-assembler "vstrdt.u64" } } */
void
foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_base_p (addr, 8, value, p);
}
/* { dg-final { scan-assembler "vstrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_base_p_u64 (addr, 8, value, p);
}
/* { dg-final { scan-assembler "vstrdt.u64" } } */
void
foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_base_p (addr, 8, value, p);
}
/* { dg-final { scan-assembler "vstrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64x2_t addr, const int offset, int64x2_t value)
{
vstrdq_scatter_base_s64 (addr, 1016, value);
}
/* { dg-final { scan-assembler "vstrd.u64" } } */
void
foo1 (uint64x2_t addr, const int offset, int64x2_t value)
{
vstrdq_scatter_base (addr, 1016, value);
}
/* { dg-final { scan-assembler "vstrd.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64x2_t addr, const int offset, uint64x2_t value)
{
vstrdq_scatter_base_u64 (addr, 8, value);
}
/* { dg-final { scan-assembler "vstrd.u64" } } */
void
foo1 (uint64x2_t addr, const int offset, uint64x2_t value)
{
vstrdq_scatter_base (addr, 8, value);
}
/* { dg-final { scan-assembler "vstrd.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_offset_p_s64 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
void
foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_offset_p_u64 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
void
foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int64_t * base, uint64x2_t offset, int64x2_t value)
{
vstrdq_scatter_offset_s64 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
void
foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
{
vstrdq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
{
vstrdq_scatter_offset_u64 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
void
foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
{
vstrdq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
void
foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
void
foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
vstrdq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrdt.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int64_t * base, uint64x2_t offset, int64x2_t value)
{
vstrdq_scatter_shifted_offset_s64 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
void
foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
{
vstrdq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
{
vstrdq_scatter_shifted_offset_u64 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
void
foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
{
vstrdq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrd.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float16_t * base, uint16x8_t offset, float16x8_t value)
{
vstrhq_scatter_offset_f16 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
{
vstrhq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p_f16 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float16_t * base, uint16x8_t offset, float16x8_t value)
{
vstrhq_scatter_shifted_offset_f16 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
{
vstrhq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32x4_t addr, float32x4_t value)
{
vstrwq_scatter_base_f32 (addr, 8, value);
}
/* { dg-final { scan-assembler "vstrw.u32" } } */
void
foo1 (uint32x4_t addr, float32x4_t value)
{
vstrwq_scatter_base (addr, 8, value);
}
/* { dg-final { scan-assembler "vstrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_base_p_f32 (addr, 8, value, p);
}
/* { dg-final { scan-assembler "vstrwt.u32" } } */
void
foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_base_p (addr, 8, value, p);
}
/* { dg-final { scan-assembler "vstrwt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float32_t * base, uint32x4_t offset, float32x4_t value)
{
vstrwq_scatter_offset_f32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
{
vstrwq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_offset_p_f32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_offset_p_s32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_offset_p_u32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int32_t * base, uint32x4_t offset, int32x4_t value)
{
vstrwq_scatter_offset_s32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
{
vstrwq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrwq_scatter_offset_u32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrwq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float32_t * base, uint32x4_t offset, float32x4_t value)
{
vstrwq_scatter_shifted_offset_f32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
{
vstrwq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrwq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int32_t * base, uint32x4_t offset, int32x4_t value)
{
vstrwq_scatter_shifted_offset_s32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
{
vstrwq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrwq_scatter_shifted_offset_u32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrwq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
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