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riscv-gcc-1
Commit 5cad47e0 by Srinath Parvathaneni Committed by Kyrylo Tkachov
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[ARM][GCC][7/5x]: MVE store intrinsics which stores byte,half word or word to memory. 

This patch supports the following MVE ACLE store intrinsics which stores a byte, halfword, or word to memory.

vst1q_f32, vst1q_f16, vst1q_s8, vst1q_s32, vst1q_s16, vst1q_u8, vst1q_u32, vst1q_u16, vstrhq_f16, vstrhq_scatter_offset_s32, vstrhq_scatter_offset_s16, vstrhq_scatter_offset_u32, vstrhq_scatter_offset_u16, vstrhq_scatter_offset_p_s32, vstrhq_scatter_offset_p_s16, vstrhq_scatter_offset_p_u32, vstrhq_scatter_offset_p_u16, vstrhq_scatter_shifted_offset_s32,
vstrhq_scatter_shifted_offset_s16, vstrhq_scatter_shifted_offset_u32,
vstrhq_scatter_shifted_offset_u16, vstrhq_scatter_shifted_offset_p_s32,
vstrhq_scatter_shifted_offset_p_s16, vstrhq_scatter_shifted_offset_p_u32,
vstrhq_scatter_shifted_offset_p_u16, vstrhq_s32, vstrhq_s16, vstrhq_u32, vstrhq_u16, vstrhq_p_f16, vstrhq_p_s32, vstrhq_p_s16, vstrhq_p_u32, vstrhq_p_u16, vstrwq_f32, vstrwq_s32, vstrwq_u32, vstrwq_p_f32, vstrwq_p_s32, vstrwq_p_u32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1]  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vst1q_f32): Define macro.
	(vst1q_f16): Likewise.
	(vst1q_s8): Likewise.
	(vst1q_s32): Likewise.
	(vst1q_s16): Likewise.
	(vst1q_u8): Likewise.
	(vst1q_u32): Likewise.
	(vst1q_u16): Likewise.
	(vstrhq_f16): Likewise.
	(vstrhq_scatter_offset_s32): Likewise.
	(vstrhq_scatter_offset_s16): Likewise.
	(vstrhq_scatter_offset_u32): Likewise.
	(vstrhq_scatter_offset_u16): Likewise.
	(vstrhq_scatter_offset_p_s32): Likewise.
	(vstrhq_scatter_offset_p_s16): Likewise.
	(vstrhq_scatter_offset_p_u32): Likewise.
	(vstrhq_scatter_offset_p_u16): Likewise.
	(vstrhq_scatter_shifted_offset_s32): Likewise.
	(vstrhq_scatter_shifted_offset_s16): Likewise.
	(vstrhq_scatter_shifted_offset_u32): Likewise.
	(vstrhq_scatter_shifted_offset_u16): Likewise.
	(vstrhq_scatter_shifted_offset_p_s32): Likewise.
	(vstrhq_scatter_shifted_offset_p_s16): Likewise.
	(vstrhq_scatter_shifted_offset_p_u32): Likewise.
	(vstrhq_scatter_shifted_offset_p_u16): Likewise.
	(vstrhq_s32): Likewise.
	(vstrhq_s16): Likewise.
	(vstrhq_u32): Likewise.
	(vstrhq_u16): Likewise.
	(vstrhq_p_f16): Likewise.
	(vstrhq_p_s32): Likewise.
	(vstrhq_p_s16): Likewise.
	(vstrhq_p_u32): Likewise.
	(vstrhq_p_u16): Likewise.
	(vstrwq_f32): Likewise.
	(vstrwq_s32): Likewise.
	(vstrwq_u32): Likewise.
	(vstrwq_p_f32): Likewise.
	(vstrwq_p_s32): Likewise.
	(vstrwq_p_u32): Likewise.
	(__arm_vst1q_s8): Define intrinsic.
	(__arm_vst1q_s32): Likewise.
	(__arm_vst1q_s16): Likewise.
	(__arm_vst1q_u8): Likewise.
	(__arm_vst1q_u32): Likewise.
	(__arm_vst1q_u16): Likewise.
	(__arm_vstrhq_scatter_offset_s32): Likewise.
	(__arm_vstrhq_scatter_offset_s16): Likewise.
	(__arm_vstrhq_scatter_offset_u32): Likewise.
	(__arm_vstrhq_scatter_offset_u16): Likewise.
	(__arm_vstrhq_scatter_offset_p_s32): Likewise.
	(__arm_vstrhq_scatter_offset_p_s16): Likewise.
	(__arm_vstrhq_scatter_offset_p_u32): Likewise.
	(__arm_vstrhq_scatter_offset_p_u16): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
	(__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
	(__arm_vstrhq_s32): Likewise.
	(__arm_vstrhq_s16): Likewise.
	(__arm_vstrhq_u32): Likewise.
	(__arm_vstrhq_u16): Likewise.
	(__arm_vstrhq_p_s32): Likewise.
	(__arm_vstrhq_p_s16): Likewise.
	(__arm_vstrhq_p_u32): Likewise.
	(__arm_vstrhq_p_u16): Likewise.
	(__arm_vstrwq_s32): Likewise.
	(__arm_vstrwq_u32): Likewise.
	(__arm_vstrwq_p_s32): Likewise.
	(__arm_vstrwq_p_u32): Likewise.
	(__arm_vstrwq_p_f32): Likewise.
	(__arm_vstrwq_f32): Likewise.
	(__arm_vst1q_f32): Likewise.
	(__arm_vst1q_f16): Likewise.
	(__arm_vstrhq_f16): Likewise.
	(__arm_vstrhq_p_f16): Likewise.
	(vst1q): Define polymorphic variant.
	(vstrhq): Likewise.
	(vstrhq_p): Likewise.
	(vstrhq_scatter_offset_p): Likewise.
	(vstrhq_scatter_offset): Likewise.
	(vstrhq_scatter_shifted_offset_p): Likewise.
	(vstrhq_scatter_shifted_offset): Likewise.
	(vstrwq_p): Likewise.
	(vstrwq): Likewise.
	* config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
	(STRS_P): Likewise.
	(STRSS): Likewise.
	(STRSS_P): Likewise.
	(STRSU): Likewise.
	(STRSU_P): Likewise.
	(STRU): Likewise.
	(STRU_P): Likewise.
	* config/arm/mve.md (VST1Q): Define iterator.
	(VSTRHSOQ): Likewise.
	(VSTRHSSOQ): Likewise.
	(VSTRHQ): Likewise.
	(VSTRWQ): Likewise.
	(mve_vstrhq_fv8hf): Define RTL pattern.
	(mve_vstrhq_p_fv8hf): Likewise.
	(mve_vstrhq_p_<supf><mode>): Likewise.
	(mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
	(mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
	(mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
	(mve_vstrhq_<supf><mode>): Likewise.
	(mve_vstrwq_fv4sf): Likewise.
	(mve_vstrwq_p_fv4sf): Likewise.
	(mve_vstrwq_p_<supf>v4si): Likewise.
	(mve_vstrwq_<supf>v4si): Likewise.
	(mve_vst1q_f<mode>): Define expand.
	(mve_vst1q_<supf><mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
parent 4cc23303
Showing with 1441 additions and 62 deletions
gcc/ChangeLog
...@@ -2,6 +2,127 @@ ...@@ -2,6 +2,127 @@
Mihail Ionescu <mihail.ionescu@arm.com> Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vst1q_f32): Define macro.
(vst1q_f16): Likewise.
(vst1q_s8): Likewise.
(vst1q_s32): Likewise.
(vst1q_s16): Likewise.
(vst1q_u8): Likewise.
(vst1q_u32): Likewise.
(vst1q_u16): Likewise.
(vstrhq_f16): Likewise.
(vstrhq_scatter_offset_s32): Likewise.
(vstrhq_scatter_offset_s16): Likewise.
(vstrhq_scatter_offset_u32): Likewise.
(vstrhq_scatter_offset_u16): Likewise.
(vstrhq_scatter_offset_p_s32): Likewise.
(vstrhq_scatter_offset_p_s16): Likewise.
(vstrhq_scatter_offset_p_u32): Likewise.
(vstrhq_scatter_offset_p_u16): Likewise.
(vstrhq_scatter_shifted_offset_s32): Likewise.
(vstrhq_scatter_shifted_offset_s16): Likewise.
(vstrhq_scatter_shifted_offset_u32): Likewise.
(vstrhq_scatter_shifted_offset_u16): Likewise.
(vstrhq_scatter_shifted_offset_p_s32): Likewise.
(vstrhq_scatter_shifted_offset_p_s16): Likewise.
(vstrhq_scatter_shifted_offset_p_u32): Likewise.
(vstrhq_scatter_shifted_offset_p_u16): Likewise.
(vstrhq_s32): Likewise.
(vstrhq_s16): Likewise.
(vstrhq_u32): Likewise.
(vstrhq_u16): Likewise.
(vstrhq_p_f16): Likewise.
(vstrhq_p_s32): Likewise.
(vstrhq_p_s16): Likewise.
(vstrhq_p_u32): Likewise.
(vstrhq_p_u16): Likewise.
(vstrwq_f32): Likewise.
(vstrwq_s32): Likewise.
(vstrwq_u32): Likewise.
(vstrwq_p_f32): Likewise.
(vstrwq_p_s32): Likewise.
(vstrwq_p_u32): Likewise.
(__arm_vst1q_s8): Define intrinsic.
(__arm_vst1q_s32): Likewise.
(__arm_vst1q_s16): Likewise.
(__arm_vst1q_u8): Likewise.
(__arm_vst1q_u32): Likewise.
(__arm_vst1q_u16): Likewise.
(__arm_vstrhq_scatter_offset_s32): Likewise.
(__arm_vstrhq_scatter_offset_s16): Likewise.
(__arm_vstrhq_scatter_offset_u32): Likewise.
(__arm_vstrhq_scatter_offset_u16): Likewise.
(__arm_vstrhq_scatter_offset_p_s32): Likewise.
(__arm_vstrhq_scatter_offset_p_s16): Likewise.
(__arm_vstrhq_scatter_offset_p_u32): Likewise.
(__arm_vstrhq_scatter_offset_p_u16): Likewise.
(__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
(__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
(__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
(__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
(__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
(__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
(__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
(__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
(__arm_vstrhq_s32): Likewise.
(__arm_vstrhq_s16): Likewise.
(__arm_vstrhq_u32): Likewise.
(__arm_vstrhq_u16): Likewise.
(__arm_vstrhq_p_s32): Likewise.
(__arm_vstrhq_p_s16): Likewise.
(__arm_vstrhq_p_u32): Likewise.
(__arm_vstrhq_p_u16): Likewise.
(__arm_vstrwq_s32): Likewise.
(__arm_vstrwq_u32): Likewise.
(__arm_vstrwq_p_s32): Likewise.
(__arm_vstrwq_p_u32): Likewise.
(__arm_vstrwq_p_f32): Likewise.
(__arm_vstrwq_f32): Likewise.
(__arm_vst1q_f32): Likewise.
(__arm_vst1q_f16): Likewise.
(__arm_vstrhq_f16): Likewise.
(__arm_vstrhq_p_f16): Likewise.
(vst1q): Define polymorphic variant.
(vstrhq): Likewise.
(vstrhq_p): Likewise.
(vstrhq_scatter_offset_p): Likewise.
(vstrhq_scatter_offset): Likewise.
(vstrhq_scatter_shifted_offset_p): Likewise.
(vstrhq_scatter_shifted_offset): Likewise.
(vstrwq_p): Likewise.
(vstrwq): Likewise.
* config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
(STRS_P): Likewise.
(STRSS): Likewise.
(STRSS_P): Likewise.
(STRSU): Likewise.
(STRSU_P): Likewise.
(STRU): Likewise.
(STRU_P): Likewise.
* config/arm/mve.md (VST1Q): Define iterator.
(VSTRHSOQ): Likewise.
(VSTRHSSOQ): Likewise.
(VSTRHQ): Likewise.
(VSTRWQ): Likewise.
(mve_vstrhq_fv8hf): Define RTL pattern.
(mve_vstrhq_p_fv8hf): Likewise.
(mve_vstrhq_p_<supf><mode>): Likewise.
(mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
(mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
(mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
(mve_vstrhq_<supf><mode>): Likewise.
(mve_vstrwq_fv4sf): Likewise.
(mve_vstrwq_p_fv4sf): Likewise.
(mve_vstrwq_p_<supf>v4si): Likewise.
(mve_vstrwq_<supf>v4si): Likewise.
(mve_vst1q_f<mode>): Define expand.
(mve_vst1q_<supf><mode>): Likewise.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vld1q_s8): Define macro. * config/arm/arm_mve.h (vld1q_s8): Define macro.
(vld1q_s32): Likewise. (vld1q_s32): Likewise.
(vld1q_s16): Likewise. (vld1q_s16): Likewise.
......
gcc/config/arm/arm_mve_builtins.def
...@@ -762,3 +762,26 @@ VAR1 (LDRGU_Z, vldrdq_gather_offset_z_u, v2di) ...@@ -762,3 +762,26 @@ VAR1 (LDRGU_Z, vldrdq_gather_offset_z_u, v2di)
VAR1 (LDRGU_Z, vldrdq_gather_shifted_offset_z_u, v2di) VAR1 (LDRGU_Z, vldrdq_gather_shifted_offset_z_u, v2di)
VAR1 (LDRGU_Z, vldrwq_gather_offset_z_u, v4si) VAR1 (LDRGU_Z, vldrwq_gather_offset_z_u, v4si)
VAR1 (LDRGU_Z, vldrwq_gather_shifted_offset_z_u, v4si) VAR1 (LDRGU_Z, vldrwq_gather_shifted_offset_z_u, v4si)
VAR3 (STRU, vst1q_u, v16qi, v8hi, v4si)
VAR3 (STRS, vst1q_s, v16qi, v8hi, v4si)
VAR2 (STRU_P, vstrhq_p_u, v8hi, v4si)
VAR2 (STRU, vstrhq_u, v8hi, v4si)
VAR2 (STRS_P, vstrhq_p_s, v8hi, v4si)
VAR2 (STRS, vstrhq_s, v8hi, v4si)
VAR2 (STRS, vst1q_f, v8hf, v4sf)
VAR2 (STRSU_P, vstrhq_scatter_shifted_offset_p_u, v8hi, v4si)
VAR2 (STRSU_P, vstrhq_scatter_offset_p_u, v8hi, v4si)
VAR2 (STRSU, vstrhq_scatter_shifted_offset_u, v8hi, v4si)
VAR2 (STRSU, vstrhq_scatter_offset_u, v8hi, v4si)
VAR2 (STRSS_P, vstrhq_scatter_shifted_offset_p_s, v8hi, v4si)
VAR2 (STRSS_P, vstrhq_scatter_offset_p_s, v8hi, v4si)
VAR2 (STRSS, vstrhq_scatter_shifted_offset_s, v8hi, v4si)
VAR2 (STRSS, vstrhq_scatter_offset_s, v8hi, v4si)
VAR1 (STRS, vstrhq_f, v8hf)
VAR1 (STRS_P, vstrhq_p_f, v8hf)
VAR1 (STRS, vstrwq_f, v4sf)
VAR1 (STRS, vstrwq_s, v4si)
VAR1 (STRU, vstrwq_u, v4si)
VAR1 (STRS_P, vstrwq_p_f, v4sf)
VAR1 (STRS_P, vstrwq_p_s, v4si)
VAR1 (STRU_P, vstrwq_p_u, v4si)
gcc/config/arm/mve.md
...@@ -201,7 +201,9 @@ ...@@ -201,7 +201,9 @@
VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U
VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F
VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S
VLDRWQGSO_U]) VLDRWQGSO_U VSTRHQ_F VST1Q_S VST1Q_U VSTRHQSO_S
VSTRHQSO_U VSTRHQSSO_S VSTRHQSSO_U VSTRHQ_S
VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
(V4SF "V4SI")]) (V4SF "V4SI")])
...@@ -363,7 +365,10 @@ ...@@ -363,7 +365,10 @@
(VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u") (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u")
(VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s") (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s")
(VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u") (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u")
(VLDRWQGSO_S "s") (VLDRWQGSO_U "u")]) (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s")
(VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u")
(VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s")
(VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")])
(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
...@@ -602,6 +607,11 @@ ...@@ -602,6 +607,11 @@
(define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U]) (define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U])
(define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U]) (define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U])
(define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U]) (define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U])
(define_int_iterator VST1Q [VST1Q_S VST1Q_U])
(define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U])
(define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U])
(define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U])
(define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U])
(define_insn "*mve_mov<mode>" (define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
...@@ -8924,3 +8934,265 @@ ...@@ -8924,3 +8934,265 @@
return ""; return "";
} }
[(set_attr "length" "8")]) [(set_attr "length" "8")])
;;
;; [vstrhq_f]
;;
(define_insn "mve_vstrhq_fv8hf"
[(set (match_operand:V8HI 0 "memory_operand" "=Us")
(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")]
VSTRHQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vstrh.16\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "4")])
;;
;; [vstrhq_p_f]
;;
(define_insn "mve_vstrhq_p_fv8hf"
[(set (match_operand:V8HI 0 "memory_operand" "=Us")
(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VSTRHQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vpst\n\tvstrht.16\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "8")])
;;
;; [vstrhq_p_s vstrhq_p_u]
;;
(define_insn "mve_vstrhq_p_<supf><mode>"
[(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VSTRHQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "8")])
;;
;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u]
;;
(define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>"
[(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
(unspec:<MVE_H_ELEM>
[(match_operand:MVE_6 1 "s_register_operand" "w")
(match_operand:MVE_6 2 "s_register_operand" "w")
(match_operand:HI 3 "vpr_register_operand" "Up")]
VSTRHSOQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[3];
ops[0] = operands[0];
ops[1] = operands[1];
ops[2] = operands[2];
output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
return "";
}
[(set_attr "length" "8")])
;;
;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u]
;;
(define_insn "mve_vstrhq_scatter_offset_<supf><mode>"
[(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
(unspec:<MVE_H_ELEM>
[(match_operand:MVE_6 1 "s_register_operand" "w")
(match_operand:MVE_6 2 "s_register_operand" "w")]
VSTRHSOQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[3];
ops[0] = operands[0];
ops[1] = operands[1];
ops[2] = operands[2];
output_asm_insn ("vstrh.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
return "";
}
[(set_attr "length" "4")])
;;
;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u]
;;
(define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>"
[(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
(unspec:<MVE_H_ELEM>
[(match_operand:MVE_6 1 "s_register_operand" "w")
(match_operand:MVE_6 2 "s_register_operand" "w")
(match_operand:HI 3 "vpr_register_operand" "Up")]
VSTRHSSOQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[3];
ops[0] = operands[0];
ops[1] = operands[1];
ops[2] = operands[2];
output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q2, [%m0, %q1, uxtw #1]",ops);
return "";
}
[(set_attr "length" "8")])
;;
;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u]
;;
(define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>"
[(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
(unspec:<MVE_H_ELEM>
[(match_operand:MVE_6 1 "s_register_operand" "w")
(match_operand:MVE_6 2 "s_register_operand" "w")]
VSTRHSSOQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[3];
ops[0] = operands[0];
ops[1] = operands[1];
ops[2] = operands[2];
output_asm_insn ("vstrh.<V_sz_elem>\t%q2, [%m0, %q1, uxtw #1]",ops);
return "";
}
[(set_attr "length" "4")])
;;
;; [vstrhq_s, vstrhq_u]
;;
(define_insn "mve_vstrhq_<supf><mode>"
[(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")]
VSTRHQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "4")])
;;
;; [vstrwq_f]
;;
(define_insn "mve_vstrwq_fv4sf"
[(set (match_operand:V4SI 0 "memory_operand" "=Us")
(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")]
VSTRWQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vstrw.32\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "4")])
;;
;; [vstrwq_p_f]
;;
(define_insn "mve_vstrwq_p_fv4sf"
[(set (match_operand:V4SI 0 "memory_operand" "=Us")
(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VSTRWQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "8")])
;;
;; [vstrwq_p_s vstrwq_p_u]
;;
(define_insn "mve_vstrwq_p_<supf>v4si"
[(set (match_operand:V4SI 0 "memory_operand" "=Us")
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VSTRWQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "8")])
;;
;; [vstrwq_s vstrwq_u]
;;
(define_insn "mve_vstrwq_<supf>v4si"
[(set (match_operand:V4SI 0 "memory_operand" "=Us")
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")]
VSTRWQ))
]
"TARGET_HAVE_MVE"
{
rtx ops[2];
int regno = REGNO (operands[1]);
ops[1] = gen_rtx_REG (TImode, regno);
ops[0] = operands[0];
output_asm_insn ("vstrw.32\t%q1, %E0",ops);
return "";
}
[(set_attr "length" "4")])
(define_expand "mve_vst1q_f<mode>"
[(match_operand:<MVE_CNVT> 0 "memory_operand")
(unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F)
]
"TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
{
emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
DONE;
})
(define_expand "mve_vst1q_<supf><mode>"
[(match_operand:MVE_2 0 "memory_operand")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q)
]
"TARGET_HAVE_MVE"
{
emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
DONE;
})
gcc/testsuite/ChangeLog
...@@ -2,6 +2,59 @@ ...@@ -2,6 +2,59 @@
Mihail Ionescu <mihail.ionescu@arm.com> Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
/* { dg-do compile } */ /* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ /* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h" #include "arm_mve.h"
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float16_t * addr, float16x8_t value)
{
vst1q_f16 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (float16_t * addr, float16x8_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float32_t * addr, float32x4_t value)
{
vst1q_f32 (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (float32_t * addr, float32x4_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * addr, int16x8_t value)
{
vst1q_s16 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (int16_t * addr, int16x8_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int32_t * addr, int32x4_t value)
{
vst1q_s32 (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (int32_t * addr, int32x4_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int8_t * addr, int8x16_t value)
{
vst1q_s8 (addr, value);
}
/* { dg-final { scan-assembler "vstrb.8" } } */
void
foo1 (int8_t * addr, int8x16_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrb.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * addr, uint16x8_t value)
{
vst1q_u16 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (uint16_t * addr, uint16x8_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32_t * addr, uint32x4_t value)
{
vst1q_u32 (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (uint32_t * addr, uint32x4_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint8_t * addr, uint8x16_t value)
{
vst1q_u8 (addr, value);
}
/* { dg-final { scan-assembler "vstrb.8" } } */
void
foo1 (uint8_t * addr, uint8x16_t value)
{
vst1q (addr, value);
}
/* { dg-final { scan-assembler "vstrb.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float16_t * addr, float16x8_t value)
{
vstrhq_f16 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (float16_t * addr, float16x8_t value)
{
vstrhq (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
{
vstrhq_p_f16 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
{
vstrhq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
{
vstrhq_p_s16 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
{
vstrhq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * addr, int32x4_t value, mve_pred16_t p)
{
vstrhq_p_s32 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
void
foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p)
{
vstrhq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
{
vstrhq_p_u16 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
{
vstrhq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
{
vstrhq_p_u32 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
void
foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
{
vstrhq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * addr, int16x8_t value)
{
vstrhq_s16 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (int16_t * addr, int16x8_t value)
{
vstrhq (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * addr, int32x4_t value)
{
vstrhq_s32 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
void
foo1 (int16_t * addr, int32x4_t value)
{
vstrhq (addr, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p_s16 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p_s32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
void
foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p_u16 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p_u32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
void
foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint16x8_t offset, int16x8_t value)
{
vstrhq_scatter_offset_s16 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
{
vstrhq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint32x4_t offset, int32x4_t value)
{
vstrhq_scatter_offset_s32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
void
foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
{
vstrhq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
{
vstrhq_scatter_offset_u16 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
{
vstrhq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrhq_scatter_offset_u32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
void
foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrhq_scatter_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
void
foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
void
foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
void
foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
vstrhq_scatter_shifted_offset_p (base, offset, value, p);
}
/* { dg-final { scan-assembler "vstrht.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint16x8_t offset, int16x8_t value)
{
vstrhq_scatter_shifted_offset_s16 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
{
vstrhq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int16_t * base, uint32x4_t offset, int32x4_t value)
{
vstrhq_scatter_shifted_offset_s32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
void
foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
{
vstrhq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
{
vstrhq_scatter_shifted_offset_u16 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
{
vstrhq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrhq_scatter_shifted_offset_u32 (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
void
foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
{
vstrhq_scatter_shifted_offset (base, offset, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * addr, uint16x8_t value)
{
vstrhq_u16 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
void
foo1 (uint16_t * addr, uint16x8_t value)
{
vstrhq (addr, value);
}
/* { dg-final { scan-assembler "vstrh.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint16_t * addr, uint32x4_t value)
{
vstrhq_u32 (addr, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
void
foo1 (uint16_t * addr, uint32x4_t value)
{
vstrhq (addr, value);
}
/* { dg-final { scan-assembler "vstrh.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float32_t * addr, float32x4_t value)
{
vstrwq_f32 (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (float32_t * addr, float32x4_t value)
{
vstrwq (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
{
vstrwq_p_f32 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
{
vstrwq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
{
vstrwq_p_s32 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
{
vstrwq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
{
vstrwq_p_u32 (addr, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
void
foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
{
vstrwq_p (addr, value, p);
}
/* { dg-final { scan-assembler "vstrwt.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (int32_t * addr, int32x4_t value)
{
vstrwq_s32 (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (int32_t * addr, int32x4_t value)
{
vstrwq (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
void
foo (uint32_t * addr, uint32x4_t value)
{
vstrwq_u32 (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
void
foo1 (uint32_t * addr, uint32x4_t value)
{
vstrwq (addr, value);
}
/* { dg-final { scan-assembler "vstrw.32" } } */
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