Create new constraint "d" for PowerPC FPRs with 64-bit values.

Replace uses of "f" constraint with "d" as needed.

From-SVN: r148630

gcc/ChangeLog

+2009-06-17  Michael Eager  <eager@eagercon.com>
+
+	* config/rs6000/constraints.md: register_constraint "d": New.
+	* config/rs6000/dfp.md: movsd_store, extendsddd2, extendsdtd2,
+	truncddsd2, *negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr, *movdd_hardfloat32,
+	*movdd_hardfloat64_mfpgpr, *movdd_hardfloat64, *negtd2_fp,
+	*abstd2_fpr, *nabstd2_fpr, *movtd_internal, extendddtd2, trunctddd2,
+	adddd3, addtd3, subdd3, subtd3, muldd3, multd3, divdd3, divtd3,
+	internal1, *cmptd_internal1, floatditd2, ftruncdd2, fixdddi2,
+	ftrunctd2, fixtddi2: replace 'f' constraint with 'd'
+	* config/rs6000/ppu_intrinsics.h: __mffs, __mtfsf, __mtfsfi, __fabs,
+	__fnabs, __fmadd, __fmsub, __fnmadd, __fnmsub, __fsel, __frsqrte,
+	__fsqrt, __fmul, __fmuls, __frsp, __fcfid, __fctid, __fctidz, __fctiw,
+	__fctiwz: Same.
+	* config/rs6000/rs6000.md: *extendsfdf2_fpr, *truncdfsf2_fpr,
+	*fseldfsf4, *negdf2_fpr, *absdf2_fpr, *nabsdf2_fpr, *adddf3_fpr,
+	*subdf3_fpr, *muldf3_fpr, *divdf3_fpr, recipdf3, fred, sqrtdf2,
+	*fseldfdf4, *fselsfdf4, *floatsidf2_internal, *floatunssidf2_internal,
+	*fix_truncdfsi2_internal, fix_truncdfsi2_internal_gfxopt, fix_truncdfsi2_mfpgpr,
+	fctiwz, btruncdf2, ceildf2, floordf2, rounddf2, stfiwx, floatdidf2,
+	fix_truncdfdi2, floatdisf2_internal1, *movdf_hardfloat32,
+	*movdf_hardfloat64_mfpgpr, *movdf_hardfloat64, *movtf_internal,
+	*extenddftf2_internal, trunctfdf2_internal1, trunctfdf2_internal2,
+	trunctfsf2_fprs, fix_trunc_helper, *fix_trunctfsi2_internal,
+	negtf2_internal, *movdi_internal32, *movdi_mfpgpr, *movdi_internal64,
+	*movdf_update1, *movdf_update2, *cmpdf_internal1, *cmptf_internal1,
+	*cmptf_internal2: Same.
+	* doc/md.texi: Describe PowerPC 'd' constraint, update 'f' constraint.
+
 2009-06-16  Ian Lance Taylor  <iant@google.com>
 
 	* profile.c (total_num_never_executed): Don't define.

gcc/config/rs6000/constraints.md

@@ -23,6 +23,10 @@
 			 	 ? FLOAT_REGS : NO_REGS"
   "@internal")
 
+(define_register_constraint "d" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+			 	 ? FLOAT_REGS : NO_REGS"
+  "@internal")
+
 (define_register_constraint "b" "BASE_REGS"
   "@internal")
 

gcc/config/rs6000/ppu_intrinsics.h

@@ -385,11 +385,11 @@ typedef int __V4SI __attribute__((vector_size(16)));
 
 #define __mffs() __extension__			\
   ({double result;				\
-  __asm__ volatile ("mffs %0" : "=f" (result)); \
+  __asm__ volatile ("mffs %0" : "=d" (result)); \
   result; })
 
 #define __mtfsf(mask,value) \
-  __asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "f" ((double) (value)))
+  __asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "d" ((double) (value)))
   
 #define __mtfsfi(bits,field) \
   __asm__ volatile ("mtfsfi %0,%1" : : "n" (bits), "n" (field))
@@ -400,8 +400,8 @@ typedef int __V4SI __attribute__((vector_size(16)));
 #define __setflm(v) __extension__	      \
   ({double result;			      \
   __asm__ volatile ("mffs %0\n\tmtfsf 255,%1" \
-		    : "=&f" (result)	      \
-		    : "f" ((double) (v)));    \
+		    : "=&d" (result)	      \
+		    : "d" ((double) (v)));    \
   result; })
 
 /* __builtin_fabs may perform unnecessary rounding.  */
@@ -416,7 +416,7 @@ static __inline__ double
 __fabs(double x)
 {
   double r;
-  __asm__("fabs %0,%1" : "=f"(r) : "f"(x));
+  __asm__("fabs %0,%1" : "=d"(r) : "d"(x));
   return r;
 }
 
@@ -434,7 +434,7 @@ static __inline__ double
 __fnabs(double x)
 {
   double r;
-  __asm__("fnabs %0,%1" : "=f"(r) : "f"(x));
+  __asm__("fnabs %0,%1" : "=d"(r) : "d"(x));
   return r;
 }
 
@@ -453,7 +453,7 @@ static __inline__ double
 __fmadd(double x, double y, double z)
 {
   double r;
-  __asm__("fmadd %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
+  __asm__("fmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
   return r;
 }
 
@@ -463,7 +463,7 @@ static __inline__ double
 __fmsub(double x, double y, double z)
 {
   double r;
-  __asm__("fmsub %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
+  __asm__("fmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
   return r;
 }
 
@@ -473,7 +473,7 @@ static __inline__ double
 __fnmadd(double x, double y, double z)
 {
   double r;
-  __asm__("fnmadd %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
+  __asm__("fnmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
   return r;
 }
 
@@ -483,7 +483,7 @@ static __inline__ double
 __fnmsub(double x, double y, double z)
 {
   double r;
-  __asm__("fnmsub %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
+  __asm__("fnmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
   return r;
 }
 
@@ -533,7 +533,7 @@ static __inline__ double
 __fsel(double x, double y, double z)
 {
   double r;
-  __asm__("fsel %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
+  __asm__("fsel %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
   return r;
 }
 
@@ -552,7 +552,7 @@ static __inline__ double
 __frsqrte(double x)
 {
   double r;
-  __asm__("frsqrte %0,%1" : "=f" (r) : "f" (x));
+  __asm__("frsqrte %0,%1" : "=d" (r) : "d" (x));
   return r;
 }
 
@@ -570,7 +570,7 @@ static __inline__ double
 __fsqrt(double x)
 {
   double r;
-  __asm__("fsqrt %0,%1" : "=f"(r) : "f"(x));
+  __asm__("fsqrt %0,%1" : "=d"(r) : "d"(x));
   return r;
 }
 
@@ -588,7 +588,7 @@ static __inline__ double
 __fmul(double a, double b)
 {
   double d;
-  __asm__ ("fmul %0,%1,%2" : "=f" (d) : "f" (a), "f" (b));
+  __asm__ ("fmul %0,%1,%2" : "=d" (d) : "d" (a), "d" (b));
   return d;
 }
 
@@ -597,7 +597,7 @@ static __inline__ float
 __fmuls (float a, float b)
 {
   float d;
-  __asm__ ("fmuls %0,%1,%2" : "=f" (d) : "f" (a), "f" (b));
+  __asm__ ("fmuls %0,%1,%2" : "=d" (d) : "f" (a), "f" (b));
   return d;
 }
 
@@ -606,7 +606,7 @@ static __inline__ float
 __frsp (float a)
 {
   float d;
-  __asm__ ("frsp %0,%1" : "=f" (d) : "f" (a));
+  __asm__ ("frsp %0,%1" : "=d" (d) : "f" (a));
   return d;
 }
 
@@ -615,7 +615,7 @@ static __inline__ double
 __fcfid (long long a)
 {
   double d;
-  __asm__ ("fcfid %0,%1" : "=f" (d) : "f" (a));
+  __asm__ ("fcfid %0,%1" : "=d" (d) : "d" (a));
   return d;
 }
 
@@ -624,7 +624,7 @@ static __inline__ long long
 __fctid (double a)
 {
   long long d;
-  __asm__ ("fctid %0,%1" : "=f" (d) : "f" (a));
+  __asm__ ("fctid %0,%1" : "=d" (d) : "d" (a));
   return d;
 }
 
@@ -633,7 +633,7 @@ static __inline__ long long
 __fctidz (double a)
 {
   long long d;
-  __asm__ ("fctidz %0,%1" : "=f" (d) : "f" (a));
+  __asm__ ("fctidz %0,%1" : "=d" (d) : "d" (a));
   return d;
 }
 
@@ -642,7 +642,7 @@ static __inline__ int
 __fctiw (double a)
 {
   unsigned long long d;
-  __asm__ ("fctiw %0,%1" : "=f" (d) : "f" (a));
+  __asm__ ("fctiw %0,%1" : "=d" (d) : "d" (a));
   return (int) d;
 }
 
@@ -651,7 +651,7 @@ static __inline__ int
 __fctiwz (double a)
 {
   long long d;
-  __asm__ ("fctiwz %0,%1" : "=f" (d) : "f" (a));
+  __asm__ ("fctiwz %0,%1" : "=d" (d) : "d" (a));
   return (int) d;
 }
 

gcc/doc/md.texi

@@ -1909,8 +1909,11 @@ Any constant whose absolute value is no greater than 4-bits.
 @item b
 Address base register
 
+@item d
+Floating point register (containing 64-bit value)
+
 @item f
-Floating point register
+Floating point register (containing 32-bit value)
 
 @item v
 Vector register