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riscv-gcc-1
Commit 799dbb0f by Michael Eager Committed by Michael Eager
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Create new constraint "d" for PowerPC FPRs with 64-bit values. 

Replace uses of "f" constraint with "d" as needed.

From-SVN: r148630
parent 1469de3c
Showing with 264 additions and 228 deletions
gcc/ChangeLog
2009-06-17 Michael Eager <eager@eagercon.com>
* config/rs6000/constraints.md: register_constraint "d": New.
* config/rs6000/dfp.md: movsd_store, extendsddd2, extendsdtd2,
truncddsd2, *negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr, *movdd_hardfloat32,
*movdd_hardfloat64_mfpgpr, *movdd_hardfloat64, *negtd2_fp,
*abstd2_fpr, *nabstd2_fpr, *movtd_internal, extendddtd2, trunctddd2,
adddd3, addtd3, subdd3, subtd3, muldd3, multd3, divdd3, divtd3,
internal1, *cmptd_internal1, floatditd2, ftruncdd2, fixdddi2,
ftrunctd2, fixtddi2: replace 'f' constraint with 'd'
* config/rs6000/ppu_intrinsics.h: __mffs, __mtfsf, __mtfsfi, __fabs,
__fnabs, __fmadd, __fmsub, __fnmadd, __fnmsub, __fsel, __frsqrte,
__fsqrt, __fmul, __fmuls, __frsp, __fcfid, __fctid, __fctidz, __fctiw,
__fctiwz: Same.
* config/rs6000/rs6000.md: *extendsfdf2_fpr, *truncdfsf2_fpr,
*fseldfsf4, *negdf2_fpr, *absdf2_fpr, *nabsdf2_fpr, *adddf3_fpr,
*subdf3_fpr, *muldf3_fpr, *divdf3_fpr, recipdf3, fred, sqrtdf2,
*fseldfdf4, *fselsfdf4, *floatsidf2_internal, *floatunssidf2_internal,
*fix_truncdfsi2_internal, fix_truncdfsi2_internal_gfxopt, fix_truncdfsi2_mfpgpr,
fctiwz, btruncdf2, ceildf2, floordf2, rounddf2, stfiwx, floatdidf2,
fix_truncdfdi2, floatdisf2_internal1, *movdf_hardfloat32,
*movdf_hardfloat64_mfpgpr, *movdf_hardfloat64, *movtf_internal,
*extenddftf2_internal, trunctfdf2_internal1, trunctfdf2_internal2,
trunctfsf2_fprs, fix_trunc_helper, *fix_trunctfsi2_internal,
negtf2_internal, *movdi_internal32, *movdi_mfpgpr, *movdi_internal64,
*movdf_update1, *movdf_update2, *cmpdf_internal1, *cmptf_internal1,
*cmptf_internal2: Same.
* doc/md.texi: Describe PowerPC 'd' constraint, update 'f' constraint.
2009-06-16 Ian Lance Taylor <iant@google.com> 2009-06-16 Ian Lance Taylor <iant@google.com>
* profile.c (total_num_never_executed): Don't define. * profile.c (total_num_never_executed): Don't define.
......
gcc/config/rs6000/constraints.md
...@@ -23,6 +23,10 @@ ...@@ -23,6 +23,10 @@
? FLOAT_REGS : NO_REGS" ? FLOAT_REGS : NO_REGS"
"@internal") "@internal")
(define_register_constraint "d" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
? FLOAT_REGS : NO_REGS"
"@internal")
(define_register_constraint "b" "BASE_REGS" (define_register_constraint "b" "BASE_REGS"
"@internal") "@internal")
......
gcc/config/rs6000/dfp.md
...@@ -105,7 +105,7 @@ ...@@ -105,7 +105,7 @@
(define_insn "movsd_store" (define_insn "movsd_store"
[(set (match_operand:DD 0 "nonimmediate_operand" "=m") [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
(unspec:DD [(match_operand:SD 1 "input_operand" "f")] (unspec:DD [(match_operand:SD 1 "input_operand" "d")]
UNSPEC_MOVSD_STORE))] UNSPEC_MOVSD_STORE))]
"(gpc_reg_operand (operands[0], DDmode) "(gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], SDmode)) || gpc_reg_operand (operands[1], SDmode))
...@@ -128,15 +128,15 @@ ...@@ -128,15 +128,15 @@
;; Hardware support for decimal floating point operations. ;; Hardware support for decimal floating point operations.
(define_insn "extendsddd2" (define_insn "extendsddd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))] (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
"TARGET_DFP" "TARGET_DFP"
"dctdp %0,%1" "dctdp %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "extendsdtd2" (define_expand "extendsdtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "f")))] (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
{ {
rtx tmp = gen_reg_rtx (DDmode); rtx tmp = gen_reg_rtx (DDmode);
...@@ -147,7 +147,7 @@ ...@@ -147,7 +147,7 @@
(define_insn "truncddsd2" (define_insn "truncddsd2"
[(set (match_operand:SD 0 "gpc_reg_operand" "=f") [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
(float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "f")))] (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"drsp %0,%1" "drsp %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -159,8 +159,8 @@ ...@@ -159,8 +159,8 @@
"") "")
(define_insn "*negdd2_fpr" (define_insn "*negdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1" "fneg %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -172,15 +172,15 @@ ...@@ -172,15 +172,15 @@
"") "")
(define_insn "*absdd2_fpr" (define_insn "*absdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1" "fabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "*nabsdd2_fpr" (define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "f"))))] (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1" "fnabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -281,8 +281,8 @@ ...@@ -281,8 +281,8 @@
;; The "??" is a kludge until we can figure out a more reasonable way ;; The "??" is a kludge until we can figure out a more reasonable way
;; of handling these non-offsettable values. ;; of handling these non-offsettable values.
(define_insn "*movdd_hardfloat32" (define_insn "*movdd_hardfloat32"
[(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
(match_operand:DD 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DDmode) && (gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], DDmode))" || gpc_reg_operand (operands[1], DDmode))"
...@@ -417,8 +417,8 @@ ...@@ -417,8 +417,8 @@
; ld/std require word-aligned displacements -> 'Y' constraint. ; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload. ; List Y->r and r->Y before r->r for reload.
(define_insn "*movdd_hardfloat64_mfpgpr" (define_insn "*movdd_hardfloat64_mfpgpr"
[(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f") [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
(match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))] (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DDmode) && (gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], DDmode))" || gpc_reg_operand (operands[1], DDmode))"
...@@ -443,8 +443,8 @@ ...@@ -443,8 +443,8 @@
; ld/std require word-aligned displacements -> 'Y' constraint. ; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload. ; List Y->r and r->Y before r->r for reload.
(define_insn "*movdd_hardfloat64" (define_insn "*movdd_hardfloat64"
[(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
(match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
"TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DDmode) && (gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], DDmode))" || gpc_reg_operand (operands[1], DDmode))"
...@@ -490,8 +490,8 @@ ...@@ -490,8 +490,8 @@
"") "")
(define_insn "*negtd2_fpr" (define_insn "*negtd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] (neg:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1" "fneg %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -503,15 +503,15 @@ ...@@ -503,15 +503,15 @@
"") "")
(define_insn "*abstd2_fpr" (define_insn "*abstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1" "fabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "*nabstd2_fpr" (define_insn "*nabstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "f"))))] (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1" "fnabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -526,8 +526,8 @@ ...@@ -526,8 +526,8 @@
; otherwise reload, given m->f, will try to pick f->f and reload it, ; otherwise reload, given m->f, will try to pick f->f and reload it,
; which doesn't make progress. Likewise r->Y must be before r->r. ; which doesn't make progress. Likewise r->Y must be before r->r.
(define_insn_and_split "*movtd_internal" (define_insn_and_split "*movtd_internal"
[(set (match_operand:TD 0 "nonimmediate_operand" "=o,f,f,r,Y,r") [(set (match_operand:TD 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
(match_operand:TD 1 "input_operand" "f,o,f,YGHF,r,r"))] (match_operand:TD 1 "input_operand" "d,o,d,YGHF,r,r"))]
"TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], TDmode) && (gpc_reg_operand (operands[0], TDmode)
|| gpc_reg_operand (operands[1], TDmode))" || gpc_reg_operand (operands[1], TDmode))"
...@@ -540,8 +540,8 @@ ...@@ -540,8 +540,8 @@
;; Hardware support for decimal floating point operations. ;; Hardware support for decimal floating point operations.
(define_insn "extendddtd2" (define_insn "extendddtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "f")))] (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dctqpq %0,%1" "dctqpq %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -552,96 +552,96 @@ ...@@ -552,96 +552,96 @@
;; that the result is the first of the pair receiving the result of drdpq. ;; that the result is the first of the pair receiving the result of drdpq.
(define_insn "trunctddd2" (define_insn "trunctddd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "f"))) (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:TD 2 "=f"))] (clobber (match_scratch:TD 2 "=d"))]
"TARGET_DFP" "TARGET_DFP"
"drdpq %2,%1\;fmr %0,%2" "drdpq %2,%1\;fmr %0,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "adddd3" (define_insn "adddd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(plus:DD (match_operand:DD 1 "gpc_reg_operand" "%f") (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
(match_operand:DD 2 "gpc_reg_operand" "f")))] (match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dadd %0,%1,%2" "dadd %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "addtd3" (define_insn "addtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(plus:TD (match_operand:TD 1 "gpc_reg_operand" "%f") (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
(match_operand:TD 2 "gpc_reg_operand" "f")))] (match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"daddq %0,%1,%2" "daddq %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "subdd3" (define_insn "subdd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(minus:DD (match_operand:DD 1 "gpc_reg_operand" "f") (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d")
(match_operand:DD 2 "gpc_reg_operand" "f")))] (match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dsub %0,%1,%2" "dsub %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "subtd3" (define_insn "subtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(minus:TD (match_operand:TD 1 "gpc_reg_operand" "f") (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d")
(match_operand:TD 2 "gpc_reg_operand" "f")))] (match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dsubq %0,%1,%2" "dsubq %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "muldd3" (define_insn "muldd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(mult:DD (match_operand:DD 1 "gpc_reg_operand" "%f") (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
(match_operand:DD 2 "gpc_reg_operand" "f")))] (match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dmul %0,%1,%2" "dmul %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "multd3" (define_insn "multd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(mult:TD (match_operand:TD 1 "gpc_reg_operand" "%f") (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
(match_operand:TD 2 "gpc_reg_operand" "f")))] (match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dmulq %0,%1,%2" "dmulq %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "divdd3" (define_insn "divdd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(div:DD (match_operand:DD 1 "gpc_reg_operand" "f") (div:DD (match_operand:DD 1 "gpc_reg_operand" "d")
(match_operand:DD 2 "gpc_reg_operand" "f")))] (match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"ddiv %0,%1,%2" "ddiv %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "divtd3" (define_insn "divtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(div:TD (match_operand:TD 1 "gpc_reg_operand" "f") (div:TD (match_operand:TD 1 "gpc_reg_operand" "d")
(match_operand:TD 2 "gpc_reg_operand" "f")))] (match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"ddivq %0,%1,%2" "ddivq %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "*cmpdd_internal1" (define_insn "*cmpdd_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d")
(match_operand:DD 2 "gpc_reg_operand" "f")))] (match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dcmpu %0,%1,%2" "dcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")]) [(set_attr "type" "fpcompare")])
(define_insn "*cmptd_internal1" (define_insn "*cmptd_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d")
(match_operand:TD 2 "gpc_reg_operand" "f")))] (match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dcmpuq %0,%1,%2" "dcmpuq %0,%1,%2"
[(set_attr "type" "fpcompare")]) [(set_attr "type" "fpcompare")])
(define_insn "floatditd2" (define_insn "floatditd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float:TD (match_operand:DI 1 "gpc_reg_operand" "f")))] (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dcffixq %0,%1" "dcffixq %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -650,8 +650,8 @@ ...@@ -650,8 +650,8 @@
;; This is the first stage of converting it to an integer type. ;; This is the first stage of converting it to an integer type.
(define_insn "ftruncdd2" (define_insn "ftruncdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=f") [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(fix:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"drintn. 0,%0,%1,1" "drintn. 0,%0,%1,1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -660,8 +660,8 @@ ...@@ -660,8 +660,8 @@
;; This is the second stage of converting decimal float to integer type. ;; This is the second stage of converting decimal float to integer type.
(define_insn "fixdddi2" (define_insn "fixdddi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f") [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(fix:DI (match_operand:DD 1 "gpc_reg_operand" "f")))] (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dctfix %0,%1" "dctfix %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -670,8 +670,8 @@ ...@@ -670,8 +670,8 @@
;; This is the first stage of converting it to an integer type. ;; This is the first stage of converting it to an integer type.
(define_insn "ftrunctd2" (define_insn "ftrunctd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=f") [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(fix:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"drintnq. 0,%0,%1,1" "drintnq. 0,%0,%1,1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -680,8 +680,8 @@ ...@@ -680,8 +680,8 @@
;; This is the second stage of converting decimal float to integer type. ;; This is the second stage of converting decimal float to integer type.
(define_insn "fixtddi2" (define_insn "fixtddi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f") [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(fix:DI (match_operand:TD 1 "gpc_reg_operand" "f")))] (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dctfixq %0,%1" "dctfixq %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
gcc/config/rs6000/ppu_intrinsics.h
...@@ -385,11 +385,11 @@ typedef int __V4SI __attribute__((vector_size(16))); ...@@ -385,11 +385,11 @@ typedef int __V4SI __attribute__((vector_size(16)));
#define __mffs() __extension__ \ #define __mffs() __extension__ \
({double result; \ ({double result; \
__asm__ volatile ("mffs %0" : "=f" (result)); \ __asm__ volatile ("mffs %0" : "=d" (result)); \
result; }) result; })
#define __mtfsf(mask,value) \ #define __mtfsf(mask,value) \
__asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "f" ((double) (value))) __asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "d" ((double) (value)))
#define __mtfsfi(bits,field) \ #define __mtfsfi(bits,field) \
__asm__ volatile ("mtfsfi %0,%1" : : "n" (bits), "n" (field)) __asm__ volatile ("mtfsfi %0,%1" : : "n" (bits), "n" (field))
...@@ -400,8 +400,8 @@ typedef int __V4SI __attribute__((vector_size(16))); ...@@ -400,8 +400,8 @@ typedef int __V4SI __attribute__((vector_size(16)));
#define __setflm(v) __extension__ \ #define __setflm(v) __extension__ \
({double result; \ ({double result; \
__asm__ volatile ("mffs %0\n\tmtfsf 255,%1" \ __asm__ volatile ("mffs %0\n\tmtfsf 255,%1" \
: "=&f" (result) \ : "=&d" (result) \
: "f" ((double) (v))); \ : "d" ((double) (v))); \
result; }) result; })
/* __builtin_fabs may perform unnecessary rounding. */ /* __builtin_fabs may perform unnecessary rounding. */
...@@ -416,7 +416,7 @@ static __inline__ double ...@@ -416,7 +416,7 @@ static __inline__ double
__fabs(double x) __fabs(double x)
{ {
double r; double r;
__asm__("fabs %0,%1" : "=f"(r) : "f"(x)); __asm__("fabs %0,%1" : "=d"(r) : "d"(x));
return r; return r;
} }
...@@ -434,7 +434,7 @@ static __inline__ double ...@@ -434,7 +434,7 @@ static __inline__ double
__fnabs(double x) __fnabs(double x)
{ {
double r; double r;
__asm__("fnabs %0,%1" : "=f"(r) : "f"(x)); __asm__("fnabs %0,%1" : "=d"(r) : "d"(x));
return r; return r;
} }
...@@ -453,7 +453,7 @@ static __inline__ double ...@@ -453,7 +453,7 @@ static __inline__ double
__fmadd(double x, double y, double z) __fmadd(double x, double y, double z)
{ {
double r; double r;
__asm__("fmadd %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z)); __asm__("fmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r; return r;
} }
...@@ -463,7 +463,7 @@ static __inline__ double ...@@ -463,7 +463,7 @@ static __inline__ double
__fmsub(double x, double y, double z) __fmsub(double x, double y, double z)
{ {
double r; double r;
__asm__("fmsub %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z)); __asm__("fmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r; return r;
} }
...@@ -473,7 +473,7 @@ static __inline__ double ...@@ -473,7 +473,7 @@ static __inline__ double
__fnmadd(double x, double y, double z) __fnmadd(double x, double y, double z)
{ {
double r; double r;
__asm__("fnmadd %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z)); __asm__("fnmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r; return r;
} }
...@@ -483,7 +483,7 @@ static __inline__ double ...@@ -483,7 +483,7 @@ static __inline__ double
__fnmsub(double x, double y, double z) __fnmsub(double x, double y, double z)
{ {
double r; double r;
__asm__("fnmsub %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z)); __asm__("fnmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r; return r;
} }
...@@ -533,7 +533,7 @@ static __inline__ double ...@@ -533,7 +533,7 @@ static __inline__ double
__fsel(double x, double y, double z) __fsel(double x, double y, double z)
{ {
double r; double r;
__asm__("fsel %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z)); __asm__("fsel %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r; return r;
} }
...@@ -552,7 +552,7 @@ static __inline__ double ...@@ -552,7 +552,7 @@ static __inline__ double
__frsqrte(double x) __frsqrte(double x)
{ {
double r; double r;
__asm__("frsqrte %0,%1" : "=f" (r) : "f" (x)); __asm__("frsqrte %0,%1" : "=d" (r) : "d" (x));
return r; return r;
} }
...@@ -570,7 +570,7 @@ static __inline__ double ...@@ -570,7 +570,7 @@ static __inline__ double
__fsqrt(double x) __fsqrt(double x)
{ {
double r; double r;
__asm__("fsqrt %0,%1" : "=f"(r) : "f"(x)); __asm__("fsqrt %0,%1" : "=d"(r) : "d"(x));
return r; return r;
} }
...@@ -588,7 +588,7 @@ static __inline__ double ...@@ -588,7 +588,7 @@ static __inline__ double
__fmul(double a, double b) __fmul(double a, double b)
{ {
double d; double d;
__asm__ ("fmul %0,%1,%2" : "=f" (d) : "f" (a), "f" (b)); __asm__ ("fmul %0,%1,%2" : "=d" (d) : "d" (a), "d" (b));
return d; return d;
} }
...@@ -597,7 +597,7 @@ static __inline__ float ...@@ -597,7 +597,7 @@ static __inline__ float
__fmuls (float a, float b) __fmuls (float a, float b)
{ {
float d; float d;
__asm__ ("fmuls %0,%1,%2" : "=f" (d) : "f" (a), "f" (b)); __asm__ ("fmuls %0,%1,%2" : "=d" (d) : "f" (a), "f" (b));
return d; return d;
} }
...@@ -606,7 +606,7 @@ static __inline__ float ...@@ -606,7 +606,7 @@ static __inline__ float
__frsp (float a) __frsp (float a)
{ {
float d; float d;
__asm__ ("frsp %0,%1" : "=f" (d) : "f" (a)); __asm__ ("frsp %0,%1" : "=d" (d) : "f" (a));
return d; return d;
} }
...@@ -615,7 +615,7 @@ static __inline__ double ...@@ -615,7 +615,7 @@ static __inline__ double
__fcfid (long long a) __fcfid (long long a)
{ {
double d; double d;
__asm__ ("fcfid %0,%1" : "=f" (d) : "f" (a)); __asm__ ("fcfid %0,%1" : "=d" (d) : "d" (a));
return d; return d;
} }
...@@ -624,7 +624,7 @@ static __inline__ long long ...@@ -624,7 +624,7 @@ static __inline__ long long
__fctid (double a) __fctid (double a)
{ {
long long d; long long d;
__asm__ ("fctid %0,%1" : "=f" (d) : "f" (a)); __asm__ ("fctid %0,%1" : "=d" (d) : "d" (a));
return d; return d;
} }
...@@ -633,7 +633,7 @@ static __inline__ long long ...@@ -633,7 +633,7 @@ static __inline__ long long
__fctidz (double a) __fctidz (double a)
{ {
long long d; long long d;
__asm__ ("fctidz %0,%1" : "=f" (d) : "f" (a)); __asm__ ("fctidz %0,%1" : "=d" (d) : "d" (a));
return d; return d;
} }
...@@ -642,7 +642,7 @@ static __inline__ int ...@@ -642,7 +642,7 @@ static __inline__ int
__fctiw (double a) __fctiw (double a)
{ {
unsigned long long d; unsigned long long d;
__asm__ ("fctiw %0,%1" : "=f" (d) : "f" (a)); __asm__ ("fctiw %0,%1" : "=d" (d) : "d" (a));
return (int) d; return (int) d;
} }
...@@ -651,7 +651,7 @@ static __inline__ int ...@@ -651,7 +651,7 @@ static __inline__ int
__fctiwz (double a) __fctiwz (double a)
{ {
long long d; long long d;
__asm__ ("fctiwz %0,%1" : "=f" (d) : "f" (a)); __asm__ ("fctiwz %0,%1" : "=d" (d) : "d" (a));
return (int) d; return (int) d;
} }
......
gcc/config/rs6000/rs6000.md
...@@ -5119,7 +5119,7 @@ ...@@ -5119,7 +5119,7 @@
"") "")
(define_insn_and_split "*extendsfdf2_fpr" (define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"@ "@
...@@ -5142,7 +5142,7 @@ ...@@ -5142,7 +5142,7 @@
(define_insn "*truncdfsf2_fpr" (define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"frsp %0,%1" "frsp %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -5616,7 +5616,7 @@ ...@@ -5616,7 +5616,7 @@
(define_insn "*fseldfsf4" (define_insn "*fseldfsf4"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
(match_operand:DF 4 "zero_fp_constant" "F")) (match_operand:DF 4 "zero_fp_constant" "F"))
(match_operand:SF 2 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
...@@ -5631,8 +5631,8 @@ ...@@ -5631,8 +5631,8 @@
"") "")
(define_insn "*negdf2_fpr" (define_insn "*negdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"fneg %0,%1" "fneg %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -5644,15 +5644,15 @@ ...@@ -5644,15 +5644,15 @@
"") "")
(define_insn "*absdf2_fpr" (define_insn "*absdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"fabs %0,%1" "fabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "*nabsdf2_fpr" (define_insn "*nabsdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"fnabs %0,%1" "fnabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -5665,9 +5665,9 @@ ...@@ -5665,9 +5665,9 @@
"") "")
(define_insn "*adddf3_fpr" (define_insn "*adddf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"{fa|fadd} %0,%1,%2" "{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp") [(set_attr "type" "fp")
...@@ -5681,9 +5681,9 @@ ...@@ -5681,9 +5681,9 @@
"") "")
(define_insn "*subdf3_fpr" (define_insn "*subdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"{fs|fsub} %0,%1,%2" "{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp") [(set_attr "type" "fp")
...@@ -5697,9 +5697,9 @@ ...@@ -5697,9 +5697,9 @@
"") "")
(define_insn "*muldf3_fpr" (define_insn "*muldf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"{fm|fmul} %0,%1,%2" "{fm|fmul} %0,%1,%2"
[(set_attr "type" "dmul") [(set_attr "type" "dmul")
...@@ -5715,17 +5715,17 @@ ...@@ -5715,17 +5715,17 @@
"") "")
(define_insn "*divdf3_fpr" (define_insn "*divdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f") (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
"{fd|fdiv} %0,%1,%2" "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "ddiv")]) [(set_attr "type" "ddiv")])
(define_expand "recipdf3" (define_expand "recipdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f") (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
(match_operand:DF 2 "gpc_reg_operand" "f")] (match_operand:DF 2 "gpc_reg_operand" "d")]
UNSPEC_FRES))] UNSPEC_FRES))]
"TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
&& flag_finite_math_only && !flag_trapping_math" && flag_finite_math_only && !flag_trapping_math"
...@@ -5735,37 +5735,37 @@ ...@@ -5735,37 +5735,37 @@
}) })
(define_insn "fred" (define_insn "fred"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
"TARGET_POPCNTB && flag_finite_math_only" "TARGET_POPCNTB && flag_finite_math_only"
"fre %0,%1" "fre %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "d"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
"{fma|fmadd} %0,%1,%2,%3" "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul") [(set_attr "type" "dmul")
(set_attr "fp_type" "fp_maddsub_d")]) (set_attr "fp_type" "fp_maddsub_d")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "d"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
"{fms|fmsub} %0,%1,%2,%3" "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul") [(set_attr "type" "dmul")
(set_attr "fp_type" "fp_maddsub_d")]) (set_attr "fp_type" "fp_maddsub_d")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "d"))
(match_operand:DF 3 "gpc_reg_operand" "f"))))] (match_operand:DF 3 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
&& HONOR_SIGNED_ZEROS (DFmode)" && HONOR_SIGNED_ZEROS (DFmode)"
"{fnma|fnmadd} %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
...@@ -5773,10 +5773,10 @@ ...@@ -5773,10 +5773,10 @@
(set_attr "fp_type" "fp_maddsub_d")]) (set_attr "fp_type" "fp_maddsub_d")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "d"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
&& ! HONOR_SIGNED_ZEROS (DFmode)" && ! HONOR_SIGNED_ZEROS (DFmode)"
"{fnma|fnmadd} %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
...@@ -5784,10 +5784,10 @@ ...@@ -5784,10 +5784,10 @@
(set_attr "fp_type" "fp_maddsub_d")]) (set_attr "fp_type" "fp_maddsub_d")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "d"))
(match_operand:DF 3 "gpc_reg_operand" "f"))))] (match_operand:DF 3 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
&& HONOR_SIGNED_ZEROS (DFmode)" && HONOR_SIGNED_ZEROS (DFmode)"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
...@@ -5795,10 +5795,10 @@ ...@@ -5795,10 +5795,10 @@
(set_attr "fp_type" "fp_maddsub_d")]) (set_attr "fp_type" "fp_maddsub_d")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
(match_operand:DF 2 "gpc_reg_operand" "f"))))] (match_operand:DF 2 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
&& ! HONOR_SIGNED_ZEROS (DFmode)" && ! HONOR_SIGNED_ZEROS (DFmode)"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
...@@ -5806,8 +5806,8 @@ ...@@ -5806,8 +5806,8 @@
(set_attr "fp_type" "fp_maddsub_d")]) (set_attr "fp_type" "fp_maddsub_d")])
(define_insn "sqrtdf2" (define_insn "sqrtdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
"(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT" && TARGET_DOUBLE_FLOAT"
"fsqrt %0,%1" "fsqrt %0,%1"
...@@ -5865,21 +5865,21 @@ ...@@ -5865,21 +5865,21 @@
}") }")
(define_insn "*fseldfdf4" (define_insn "*fseldfdf4"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
(match_operand:DF 4 "zero_fp_constant" "F")) (match_operand:DF 4 "zero_fp_constant" "F"))
(match_operand:DF 2 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "d")
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "d")))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"fsel %0,%1,%2,%3" "fsel %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "*fselsfdf4" (define_insn "*fselsfdf4"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 4 "zero_fp_constant" "F")) (match_operand:SF 4 "zero_fp_constant" "F"))
(match_operand:DF 2 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "d")
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "d")))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
"fsel %0,%1,%2,%3" "fsel %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -5935,12 +5935,12 @@ ...@@ -5935,12 +5935,12 @@
}") }")
(define_insn_and_split "*floatsidf2_internal" (define_insn_and_split "*floatsidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&f") [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r")) (use (match_operand:SI 2 "gpc_reg_operand" "r"))
(use (match_operand:DF 3 "gpc_reg_operand" "f")) (use (match_operand:DF 3 "gpc_reg_operand" "d"))
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"#" "#"
...@@ -6003,12 +6003,12 @@ ...@@ -6003,12 +6003,12 @@
}") }")
(define_insn_and_split "*floatunssidf2_internal" (define_insn_and_split "*floatunssidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&f") [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r")) (use (match_operand:SI 2 "gpc_reg_operand" "r"))
(use (match_operand:DF 3 "gpc_reg_operand" "f")) (use (match_operand:DF 3 "gpc_reg_operand" "d"))
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"#" "#"
"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))" "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
...@@ -6072,8 +6072,8 @@ ...@@ -6072,8 +6072,8 @@
(define_insn_and_split "*fix_truncdfsi2_internal" (define_insn_and_split "*fix_truncdfsi2_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))] (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT" && TARGET_DOUBLE_FLOAT"
...@@ -6095,8 +6095,8 @@ ...@@ -6095,8 +6095,8 @@
(define_insn_and_split "fix_truncdfsi2_internal_gfxopt" (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
[(set (match_operand:SI 0 "memory_operand" "=Z") [(set (match_operand:SI 0 "memory_operand" "=Z")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT && TARGET_DOUBLE_FLOAT
&& TARGET_PPC_GFXOPT" && TARGET_PPC_GFXOPT"
...@@ -6113,8 +6113,8 @@ ...@@ -6113,8 +6113,8 @@
(define_insn_and_split "fix_truncdfsi2_mfpgpr" (define_insn_and_split "fix_truncdfsi2_mfpgpr"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
(clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))] (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT" && TARGET_DOUBLE_FLOAT"
...@@ -6131,8 +6131,8 @@ ...@@ -6131,8 +6131,8 @@
; because the first makes it clear that operand 0 is not live ; because the first makes it clear that operand 0 is not live
; before the instruction. ; before the instruction.
(define_insn "fctiwz" (define_insn "fctiwz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f") [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
UNSPEC_FCTIWZ))] UNSPEC_FCTIWZ))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT" && TARGET_DOUBLE_FLOAT"
...@@ -6140,8 +6140,8 @@ ...@@ -6140,8 +6140,8 @@
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "btruncdf2" (define_insn "btruncdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"friz %0,%1" "friz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -6154,8 +6154,8 @@ ...@@ -6154,8 +6154,8 @@
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "ceildf2" (define_insn "ceildf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"frip %0,%1" "frip %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -6168,8 +6168,8 @@ ...@@ -6168,8 +6168,8 @@
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "floordf2" (define_insn "floordf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"frim %0,%1" "frim %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -6182,8 +6182,8 @@ ...@@ -6182,8 +6182,8 @@
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "rounddf2" (define_insn "rounddf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"frin %0,%1" "frin %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -6198,7 +6198,7 @@ ...@@ -6198,7 +6198,7 @@
; An UNSPEC is used so we don't have to support SImode in FP registers. ; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx" (define_insn "stfiwx"
[(set (match_operand:SI 0 "memory_operand" "=Z") [(set (match_operand:SI 0 "memory_operand" "=Z")
(unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")] (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
UNSPEC_STFIWX))] UNSPEC_STFIWX))]
"TARGET_PPC_GFXOPT" "TARGET_PPC_GFXOPT"
"stfiwx %1,%y0" "stfiwx %1,%y0"
...@@ -6211,15 +6211,15 @@ ...@@ -6211,15 +6211,15 @@
"") "")
(define_insn "floatdidf2" (define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))] (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
"(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
"fcfid %0,%1" "fcfid %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "fix_truncdfdi2" (define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r") [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
"(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
"fctidz %0,%1" "fctidz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
...@@ -6247,8 +6247,8 @@ ...@@ -6247,8 +6247,8 @@
;; from double rounding. ;; from double rounding.
(define_insn_and_split "floatdisf2_internal1" (define_insn_and_split "floatdisf2_internal1"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r"))) (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
(clobber (match_scratch:DF 2 "=f"))] (clobber (match_scratch:DF 2 "=d"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
"#" "#"
"&& reload_completed" "&& reload_completed"
...@@ -8497,8 +8497,8 @@ ...@@ -8497,8 +8497,8 @@
;; The "??" is a kludge until we can figure out a more reasonable way ;; The "??" is a kludge until we can figure out a more reasonable way
;; of handling these non-offsettable values. ;; of handling these non-offsettable values.
(define_insn "*movdf_hardfloat32" (define_insn "*movdf_hardfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
(match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] (match_operand:DF 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], DFmode) && (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))" || gpc_reg_operand (operands[1], DFmode))"
...@@ -8637,8 +8637,8 @@ ...@@ -8637,8 +8637,8 @@
; ld/std require word-aligned displacements -> 'Y' constraint. ; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload. ; List Y->r and r->Y before r->r for reload.
(define_insn "*movdf_hardfloat64_mfpgpr" (define_insn "*movdf_hardfloat64_mfpgpr"
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f") [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))] (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], DFmode) && (gpc_reg_operand (operands[0], DFmode)
...@@ -8664,8 +8664,8 @@ ...@@ -8664,8 +8664,8 @@
; ld/std require word-aligned displacements -> 'Y' constraint. ; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload. ; List Y->r and r->Y before r->r for reload.
(define_insn "*movdf_hardfloat64" (define_insn "*movdf_hardfloat64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
"TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], DFmode) && (gpc_reg_operand (operands[0], DFmode)
...@@ -8715,8 +8715,8 @@ ...@@ -8715,8 +8715,8 @@
; otherwise reload, given m->f, will try to pick f->f and reload it, ; otherwise reload, given m->f, will try to pick f->f and reload it,
; which doesn't make progress. Likewise r->Y must be before r->r. ; which doesn't make progress. Likewise r->Y must be before r->r.
(define_insn_and_split "*movtf_internal" (define_insn_and_split "*movtf_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
(match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
&& (gpc_reg_operand (operands[0], TFmode) && (gpc_reg_operand (operands[0], TFmode)
...@@ -8770,9 +8770,9 @@ ...@@ -8770,9 +8770,9 @@
}) })
(define_insn_and_split "*extenddftf2_internal" (define_insn_and_split "*extenddftf2_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
(float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
(use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
...@@ -8813,8 +8813,8 @@ ...@@ -8813,8 +8813,8 @@
"") "")
(define_insn_and_split "trunctfdf2_internal1" (define_insn_and_split "trunctfdf2_internal1"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
"!TARGET_IEEEQUAD && !TARGET_XL_COMPAT "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"@ "@
...@@ -8829,8 +8829,8 @@ ...@@ -8829,8 +8829,8 @@
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "trunctfdf2_internal2" (define_insn "trunctfdf2_internal2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
...@@ -8855,8 +8855,8 @@ ...@@ -8855,8 +8855,8 @@
(define_insn_and_split "trunctfsf2_fprs" (define_insn_and_split "trunctfsf2_fprs"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 2 "=f"))] (clobber (match_scratch:DF 2 "=d"))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
...@@ -8885,10 +8885,10 @@ ...@@ -8885,10 +8885,10 @@
; fadd, but rounding towards zero. ; fadd, but rounding towards zero.
; This is probably not the optimal code sequence. ; This is probably not the optimal code sequence.
(define_insn "fix_trunc_helper" (define_insn "fix_trunc_helper"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
UNSPEC_FIX_TRUNC_TF)) UNSPEC_FIX_TRUNC_TF))
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
[(set_attr "type" "fp") [(set_attr "type" "fp")
...@@ -8929,10 +8929,10 @@ ...@@ -8929,10 +8929,10 @@
(define_insn_and_split "*fix_trunctfsi2_internal" (define_insn_and_split "*fix_trunctfsi2_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
(clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
(clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
(clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
(clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))] (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
...@@ -8962,8 +8962,8 @@ ...@@ -8962,8 +8962,8 @@
"") "")
(define_insn "negtf2_internal" (define_insn "negtf2_internal"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f") [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
(neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"* "*
...@@ -9028,8 +9028,8 @@ ...@@ -9028,8 +9028,8 @@
; List r->r after r->"o<>", otherwise reload will try to reload a ; List r->r after r->"o<>", otherwise reload will try to reload a
; non-offsettable address by using r->r which won't make progress. ; non-offsettable address by using r->r which won't make progress.
(define_insn "*movdi_internal32" (define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
(match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
"! TARGET_POWERPC64 "! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode) && (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))" || gpc_reg_operand (operands[1], DImode))"
...@@ -9073,8 +9073,8 @@ ...@@ -9073,8 +9073,8 @@
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "*movdi_mfpgpr" (define_insn "*movdi_mfpgpr"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f") [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
(match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))] (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DImode) && (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))" || gpc_reg_operand (operands[1], DImode))"
...@@ -9098,8 +9098,8 @@ ...@@ -9098,8 +9098,8 @@
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")]) (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
(define_insn "*movdi_internal64" (define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
(match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
"TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS) "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
&& (gpc_reg_operand (operands[0], DImode) && (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))" || gpc_reg_operand (operands[1], DImode))"
...@@ -10293,7 +10293,7 @@ ...@@ -10293,7 +10293,7 @@
[(set_attr "type" "store_ux,store_u")]) [(set_attr "type" "store_ux,store_u")])
(define_insn "*movdf_update1" (define_insn "*movdf_update1"
[(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
(mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))) (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
...@@ -10309,7 +10309,7 @@ ...@@ -10309,7 +10309,7 @@
(define_insn "*movdf_update2" (define_insn "*movdf_update2"
[(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))) (match_operand:SI 2 "reg_or_short_operand" "r,I")))
(match_operand:DF 3 "gpc_reg_operand" "f,f")) (match_operand:DF 3 "gpc_reg_operand" "d,d"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
...@@ -12186,8 +12186,8 @@ ...@@ -12186,8 +12186,8 @@
(define_insn "*cmpdf_internal1" (define_insn "*cmpdf_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"fcmpu %0,%1,%2" "fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")]) [(set_attr "type" "fpcompare")])
...@@ -12195,8 +12195,8 @@ ...@@ -12195,8 +12195,8 @@
;; Only need to compare second words if first words equal ;; Only need to compare second words if first words equal
(define_insn "*cmptf_internal1" (define_insn "*cmptf_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
(match_operand:TF 2 "gpc_reg_operand" "f")))] (match_operand:TF 2 "gpc_reg_operand" "d")))]
"!TARGET_IEEEQUAD && !TARGET_XL_COMPAT "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
...@@ -12205,16 +12205,16 @@ ...@@ -12205,16 +12205,16 @@
(define_insn_and_split "*cmptf_internal2" (define_insn_and_split "*cmptf_internal2"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
(match_operand:TF 2 "gpc_reg_operand" "f"))) (match_operand:TF 2 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 3 "=f")) (clobber (match_scratch:DF 3 "=d"))
(clobber (match_scratch:DF 4 "=f")) (clobber (match_scratch:DF 4 "=d"))
(clobber (match_scratch:DF 5 "=f")) (clobber (match_scratch:DF 5 "=d"))
(clobber (match_scratch:DF 6 "=f")) (clobber (match_scratch:DF 6 "=d"))
(clobber (match_scratch:DF 7 "=f")) (clobber (match_scratch:DF 7 "=d"))
(clobber (match_scratch:DF 8 "=f")) (clobber (match_scratch:DF 8 "=d"))
(clobber (match_scratch:DF 9 "=f")) (clobber (match_scratch:DF 9 "=d"))
(clobber (match_scratch:DF 10 "=f"))] (clobber (match_scratch:DF 10 "=d"))]
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"#" "#"
...@@ -14689,7 +14689,7 @@ ...@@ -14689,7 +14689,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s")) (use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (match_operand:P 2 "gpc_reg_operand" "r")) (use (match_operand:P 2 "gpc_reg_operand" "r"))
(set (match_operand:DF 3 "memory_operand" "=m") (set (match_operand:DF 3 "memory_operand" "=m")
(match_operand:DF 4 "gpc_reg_operand" "f"))])] (match_operand:DF 4 "gpc_reg_operand" "d"))])]
"" ""
"bl %z1" "bl %z1"
[(set_attr "type" "branch") [(set_attr "type" "branch")
...@@ -14809,7 +14809,7 @@ ...@@ -14809,7 +14809,7 @@
(clobber (match_operand:P 1 "register_operand" "=l")) (clobber (match_operand:P 1 "register_operand" "=l"))
(use (match_operand:P 2 "symbol_ref_operand" "s")) (use (match_operand:P 2 "symbol_ref_operand" "s"))
(use (match_operand:P 3 "gpc_reg_operand" "r")) (use (match_operand:P 3 "gpc_reg_operand" "r"))
(set (match_operand:DF 4 "gpc_reg_operand" "=f") (set (match_operand:DF 4 "gpc_reg_operand" "=d")
(match_operand:DF 5 "memory_operand" "m"))])] (match_operand:DF 5 "memory_operand" "m"))])]
"" ""
"b %z2" "b %z2"
......
gcc/doc/md.texi
...@@ -1909,8 +1909,11 @@ Any constant whose absolute value is no greater than 4-bits. ...@@ -1909,8 +1909,11 @@ Any constant whose absolute value is no greater than 4-bits.
@item b @item b
Address base register Address base register
@item d
Floating point register (containing 64-bit value)
@item f @item f
Floating point register Floating point register (containing 32-bit value)
@item v @item v
Vector register Vector register
......
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