Commit 786872fd by Jan Hubicka

invoke.texi (generic): Document (i686) Update.

	* invoke.texi (generic): Document
	(i686) Update.
	* config.gcc: Make x86_64-* and i686-* default to generic tunning.
	* i386.h (TARGET_GENERIC32, TARGET_GENERIC64, TARGET_GENERIC,
	TARGET_USE_INCDEC, TARGET_PAD_RETURNS): New macros.
	(x86_use_incdec, x86_pad_returns): New variables
	(TARGET_CPU_DEFAULT_generic): New constant
	(TARGET_CPU_DEFAULT_NAMES): Add generic.
	(enum processor_type): Add generic32 and generic64.
	* i386.md (cpu attribute): Add generic32/generic64
	(movhi splitter): Behave sanely when both partial_reg_dependency and
	partial_reg_stall are set.
	(K8 splitters): Enable for generic as well.
	* predicates.md (incdec_operand): Use TARGET_INCDEC
	(aligned_operand): Avoid memory mismatch stalls.
	* athlon.md: Enable for generic64, new patterns for 128bit moves.
	* ppro.md: Enable for generic32
	* i386.c (generic64_cost, generic32_cost): New.
	(m_GENERIC32, m_GENERIC64, m_GENERIC): New macros.
	(x86_use_leave): Enable for generic64.  (x86_use_sahf,
	x86_ext_80387_constants): Enable for generic32.  (x86_push_memory,
	x86_movx, x86_unroll_strlen, x86_deep_branch, x86_use_simode_fiop,
	x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
	x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
	x86_partial_reg_dependency, x86_memory_mismatch_stall,
	x86_accumulate_outgoing_args, x86_prologue_using_move,
	x86_epilogue_using_move, x86_arch_always_fancy_math_387,
	x86_sse_partial_reg_dependency, x86_four_jump_limit, x86_schedule):
	Enable for generic.
	(x86_use_incdec, x86_pad_returns): New.
	(override_options): Add generic32 and generic64, translate "generic"
	to generic32/generic64 and "i686" to "generic32", refuse
	"generic32"/"generic64" as arch target.
	(ix86_issue_rate, ix86_adjust_cost): Handle generic as athlon.
	(ix86_reorg): Honor PAD_RETURNS.

From-SVN: r109972
parent d326eaf0
......@@ -9062,6 +9062,23 @@ Tune to @var{cpu-type} everything applicable about the generated code, except
for the ABI and the set of available instructions. The choices for
@var{cpu-type} are:
@table @emph
@item generic
Produce code optimized for the most common IA32/AMD64/EM64T processors.
If you know the CPU on which your code will run, then you should use
the corresponding @option{-mtune} option instead of
@option{-mtune=generic}. But, if you do not know exactly what CPU users
of your application will have, then you should use this option.
As new processors are deployed in the marketplace, the behavior of this
option will change. Therefore, if you upgrade to a newer version of
GCC, the code generated option will change to reflect the processors
that were most common when that version of GCC was released.
There is no @option{-march=generic} option because @option{-march}
indicates the instruction set the compiler can use, and there is no
generic instruction set applicable to all processors. In contrast,
@option{-mtune} indicates the processor (or, in this case, collection of
processors) for which the code is optimized.
@item i386
Original Intel's i386 CPU@.
@item i486
......@@ -9070,8 +9087,11 @@ Intel's i486 CPU@. (No scheduling is implemented for this chip.)
Intel Pentium CPU with no MMX support.
@item pentium-mmx
Intel PentiumMMX CPU based on Pentium core with MMX instruction set support.
@item i686, pentiumpro
@item pentiumpro
Intel PentiumPro CPU@.
@item i686
Same as @code{generic}, but when used as @code{march} option, PentiumPro
instruction set will be used, so the code will run on all i686 familly chips.
@item pentium2
Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
@item pentium3, pentium3m
......
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