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Commit d326eaf0 by Jan Hubicka Committed by Jan Hubicka
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invoke.texi (generic): Document (i686) Update. 

	* invoke.texi (generic): Document
	(i686) Update.
	* config.gcc: Make x86_64-* and i686-* default to generic tunning.
	* i386.h (TARGET_GENERIC32, TARGET_GENERIC64, TARGET_GENERIC,
	TARGET_USE_INCDEC, TARGET_PAD_RETURNS): New macros.
	(x86_use_incdec, x86_pad_returns): New variables
	(TARGET_CPU_DEFAULT_generic): New constant
	(TARGET_CPU_DEFAULT_NAMES): Add generic.
	(enum processor_type): Add generic32 and generic64.
	* i386.md (cpu attribute): Add generic32/generic64
	(movhi splitter): Behave sanely when both partial_reg_dependency and
	partial_reg_stall are set.
	(K8 splitters): Enable for generic as well.
	* predicates.md (incdec_operand): Use TARGET_INCDEC
	(aligned_operand): Avoid memory mismatch stalls.
	* athlon.md: Enable for generic64, new patterns for 128bit moves.
	* ppro.md: Enable for generic32
	* i386.c (generic64_cost, generic32_cost): New.
	(m_GENERIC32, m_GENERIC64, m_GENERIC): New macros.
	(x86_use_leave): Enable for generic64.  (x86_use_sahf,
	x86_ext_80387_constants): Enable for generic32.  (x86_push_memory,
	x86_movx, x86_unroll_strlen, x86_deep_branch, x86_use_simode_fiop,
	x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
	x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
	x86_partial_reg_dependency, x86_memory_mismatch_stall,
	x86_accumulate_outgoing_args, x86_prologue_using_move,
	x86_epilogue_using_move, x86_arch_always_fancy_math_387,
	x86_sse_partial_reg_dependency, x86_four_jump_limit, x86_schedule):
	Enable for generic.
	(x86_use_incdec, x86_pad_returns): New.
	(override_options): Add generic32 and generic64, translate "generic"
	to generic32/generic64 and "i686" to "generic32", refuse
	"generic32"/"generic64" as arch target.
	(ix86_issue_rate, ix86_adjust_cost): Handle generic as athlon.
	(ix86_reorg): Honor PAD_RETURNS.

Co-Authored-By: Evandro Menezes <evandro.menezes@amd.com>
Co-Authored-By: H.J. Lu <hongjiu.lu@intel.com>

From-SVN: r109971
parent d103fa24
Showing with 104 additions and 24 deletions
gcc/ChangeLog
2006-01-19 Jan Hubicka <jh@suse.cz>
H.J. Lu <hongjiu.lu@intel.com>
Evandro Menezes <evandro.menezes@amd.com>
* invoke.texi (generic): Document
(i686) Update.
* config.gcc: Make x86_64-* and i686-* default to generic tunning.
* i386.h (TARGET_GENERIC32, TARGET_GENERIC64, TARGET_GENERIC,
TARGET_USE_INCDEC, TARGET_PAD_RETURNS): New macros.
(x86_use_incdec, x86_pad_returns): New variables
(TARGET_CPU_DEFAULT_generic): New constant
(TARGET_CPU_DEFAULT_NAMES): Add generic.
(enum processor_type): Add generic32 and generic64.
* i386.md (cpu attribute): Add generic32/generic64
(movhi splitter): Behave sanely when both partial_reg_dependency and
partial_reg_stall are set.
(K8 splitters): Enable for generic as well.
* predicates.md (incdec_operand): Use TARGET_INCDEC
(aligned_operand): Avoid memory mismatch stalls.
* athlon.md: Enable for generic64, new patterns for 128bit moves.
* ppro.md: Enable for generic32
* i386.c (generic64_cost, generic32_cost): New.
(m_GENERIC32, m_GENERIC64, m_GENERIC): New macros.
(x86_use_leave): Enable for generic64. (x86_use_sahf,
x86_ext_80387_constants): Enable for generic32. (x86_push_memory,
x86_movx, x86_unroll_strlen, x86_deep_branch, x86_use_simode_fiop,
x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
x86_partial_reg_dependency, x86_memory_mismatch_stall,
x86_accumulate_outgoing_args, x86_prologue_using_move,
x86_epilogue_using_move, x86_arch_always_fancy_math_387,
x86_sse_partial_reg_dependency, x86_four_jump_limit, x86_schedule):
Enable for generic.
(x86_use_incdec, x86_pad_returns): New.
(override_options): Add generic32 and generic64, translate "generic"
to generic32/generic64 and "i686" to "generic32", refuse
"generic32"/"generic64" as arch target.
(ix86_issue_rate, ix86_adjust_cost): Handle generic as athlon.
(ix86_reorg): Honor PAD_RETURNS.
2006-01-19 Diego Novillo <dnovillo@redhat.com>
* tree-pretty-print.c (dump_generic_node): Handle
......
gcc/config.gcc
......@@ -2366,6 +2366,9 @@ if test x$with_cpu = x ; then
# A Cirrus ARM variant.
with_cpu="ep9312"
;;
i386-*-*)
with_cpu=i386
;;
i486-*-*)
with_cpu=i486
;;
......@@ -2417,13 +2420,26 @@ if test x$with_cpu = x ; then
pentium_m-*)
with_cpu=pentium-m
;;
*)
pentiumpro-*)
with_cpu=pentiumpro
;;
*)
with_cpu=generic
;;
esac
;;
x86_64-*-*)
with_cpu=k8
case ${target_noncanonical} in
k8-*|opteron-*|athlon_64-*)
with_cpu=k8
;;
nocona-*)
with_cpu=nocona
;;
*)
with_cpu=generic
;;
esac
;;
alphaev6[78]*-*-*)
with_cpu=ev67
......@@ -2629,13 +2645,21 @@ case "${target}" in
for which in arch cpu tune; do
eval "val=\$with_$which"
case ${val} in
"" | i386 | i486 \
i386 | i486 \
| i586 | pentium | pentium-mmx | winchip-c6 | winchip2 \
| c3 | c3-2 | i686 | pentiumpro | pentium2 | pentium3 \
| pentium4 | k6 | k6-2 | k6-3 | athlon | athlon-tbird \
| athlon-4 | athlon-xp | athlon-mp | k8 | opteron \
| athlon64 | athlon-fx | prescott | pentium-m \
| pentium4m | pentium3m| nocona)
| athlon-4 | athlon-xp | athlon-mp \
| prescott | pentium-m | pentium4m | pentium3m)
case "${target}" in
x86_64-*-*)
echo "CPU given in --with-$which=$val doesn't support 64bit mode." 1>&2
exit 1
;;
esac
# OK
;;
"" | k8 | opteron | athlon64 | athlon-fx | nocona | generic)
# OK
;;
*)
......
gcc/config/i386/i386.h
......@@ -93,11 +93,7 @@ extern const struct processor_costs *ix86_cost;
/* configure can arrange to make this 2, to force a 486. */
#ifndef TARGET_CPU_DEFAULT
#ifdef TARGET_64BIT_DEFAULT
#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8
#else
#define TARGET_CPU_DEFAULT 0
#endif
#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
#endif
#ifndef TARGET_FPMATH_DEFAULT
......@@ -140,6 +136,9 @@ extern const struct processor_costs *ix86_cost;
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
#define TUNEMASK (1 << ix86_tune)
extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
......@@ -163,6 +162,8 @@ extern const int x86_use_ffreep;
extern const int x86_inter_unit_moves, x86_schedule;
extern const int x86_use_bt;
extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
extern const int x86_use_incdec;
extern const int x86_pad_returns;
extern int x86_prefetch_sse;
#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
......@@ -217,6 +218,8 @@ extern int x86_prefetch_sse;
#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
#define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
#define TARGET_USE_BT (x86_use_bt & TUNEMASK)
#define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
#define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
#define ASSEMBLER_DIALECT (ix86_asm_dialect)
......@@ -464,12 +467,14 @@ extern int x86_prefetch_sse;
#define TARGET_CPU_DEFAULT_pentium_m 14
#define TARGET_CPU_DEFAULT_prescott 15
#define TARGET_CPU_DEFAULT_nocona 16
#define TARGET_CPU_DEFAULT_generic 17
#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
"pentiumpro", "pentium2", "pentium3", \
"pentium4", "k6", "k6-2", "k6-3",\
"athlon", "athlon-4", "k8", \
"pentium-m", "prescott", "nocona"}
"pentium-m", "prescott", "nocona", \
"generic"}
#ifndef CC1_SPEC
#define CC1_SPEC "%(cc1_cpu) "
......@@ -2119,6 +2124,8 @@ enum processor_type
PROCESSOR_PENTIUM4,
PROCESSOR_K8,
PROCESSOR_NOCONA,
PROCESSOR_GENERIC32,
PROCESSOR_GENERIC64,
PROCESSOR_max
};
......
gcc/config/i386/i386.md
......@@ -187,7 +187,7 @@
;; Processor type. This attribute must exactly match the processor_type
;; enumeration in i386.h.
(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona,generic32,generic64"
(const (symbol_ref "ix86_tune")))
;; A basic instruction type. Refinements due to arguments to be
......@@ -1511,8 +1511,12 @@
(const_string "SI")
(and (eq_attr "type" "imov")
(and (eq_attr "alternative" "0,1")
(ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
(const_int 0))))
(and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
(const_int 0))
(and (eq (symbol_ref "optimize_size")
(const_int 0))
(eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(const_int 0))))))
(const_string "SI")
;; Avoid partial register stalls when not using QImode arithmetic
(and (eq_attr "type" "imov")
......@@ -4145,7 +4149,7 @@
[(match_scratch:DF 2 "Y")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
"TARGET_K8 && !optimize_size"
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
......@@ -4154,7 +4158,7 @@
[(match_scratch:SF 2 "x")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
"TARGET_K8 && !optimize_size"
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
......@@ -19896,7 +19900,7 @@
(mult:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_K8 && !optimize_size
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
......@@ -19910,7 +19914,7 @@
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_K8 && !optimize_size
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
......@@ -19925,7 +19929,7 @@
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_K8 && !optimize_size
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
......@@ -19943,7 +19947,7 @@
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:DI 3 "r")]
"TARGET_K8 && !optimize_size
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
......@@ -19959,7 +19963,7 @@
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:SI 3 "r")]
"TARGET_K8 && !optimize_size
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
......@@ -19975,7 +19979,7 @@
(match_operand:HI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:HI 3 "r")]
"TARGET_K8 && !optimize_size"
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]
......
gcc/config/i386/predicates.md
......@@ -628,7 +628,7 @@
{
/* On Pentium4, the inc and dec operations causes extra dependency on flag
registers, since carry flag is not set. */
if ((TARGET_PENTIUM4 || TARGET_NOCONA) && !optimize_size)
if (!TARGET_USE_INCDEC && !optimize_size)
return 0;
return op == const1_rtx || op == constm1_rtx;
})
......@@ -707,6 +707,11 @@
if (GET_CODE (op) != MEM)
return 1;
/* All patterns using aligned_operand on memory operands ends up
in promoting memory operand to 64bit and thus causing memory mismatch. */
if (TARGET_MEMORY_MISMATCH_STALL && !optimize_size)
return 0;
/* Don't even try to do any aligned optimizations with volatiles. */
if (MEM_VOLATILE_P (op))
return 0;
......
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