[AArch64] PR rtl-optimization/68796 Add compare-of-zero_extract pattern

	PR rtl-optimization/68796
	* config/aarch64/aarch64.md (*and<mode>3nr_compare0_zextract):
	New pattern.
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Handle
	ZERO_EXTRACT comparison with zero.
	(aarch64_mask_from_zextract_ops): New function.
	* config/aarch64/aarch64-protos.h (aarch64_mask_from_zextract_ops):
	New prototype.

	* gcc.target/aarch64/tst_3.c: New test.
	* gcc.target/aarch64/tst_4.c: Likewise.

From-SVN: r231810

gcc/ChangeLog

+2015-12-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR rtl-optimization/68796
+	* config/aarch64/aarch64.md (*and<mode>3nr_compare0_zextract):
+	New pattern.
+	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Handle
+	ZERO_EXTRACT comparison with zero.
+	(aarch64_mask_from_zextract_ops): New function.
+	* config/aarch64/aarch64-protos.h (aarch64_mask_from_zextract_ops):
+	New prototype.
+
 2015-12-18 Robin Dapp <rdapp@linux.vnet.ibm.com>
 
 	* config/s390/predicates.md: Change and rename

gcc/config/aarch64/aarch64-protos.h

@@ -329,6 +329,7 @@ int aarch64_uxt_size (int, HOST_WIDE_INT);
 int aarch64_vec_fpconst_pow_of_2 (rtx);
 rtx aarch64_final_eh_return_addr (void);
 rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int);
+rtx aarch64_mask_from_zextract_ops (rtx, rtx);
 const char *aarch64_output_move_struct (rtx *operands);
 rtx aarch64_return_addr (int, rtx);
 rtx aarch64_simd_gen_const_vector_dup (machine_mode, int);

gcc/config/aarch64/aarch64.c

@@ -4146,7 +4146,9 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
       && y == const0_rtx
       && (code == EQ || code == NE || code == LT || code == GE)
       && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS || GET_CODE (x) == AND
-	  || GET_CODE (x) == NEG))
+	  || GET_CODE (x) == NEG
+	  || (GET_CODE (x) == ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1))
+	      && CONST_INT_P (XEXP (x, 2)))))
     return CC_NZmode;
 
   /* A compare with a shifted operand.  Because of canonicalization,
@@ -10728,6 +10730,21 @@ aarch64_simd_imm_zero_p (rtx x, machine_mode mode)
   return x == CONST0_RTX (mode);
 }
 
+
+/* Return the bitmask CONST_INT to select the bits required by a zero extract
+   operation of width WIDTH at bit position POS.  */
+
+rtx
+aarch64_mask_from_zextract_ops (rtx width, rtx pos)
+{
+  gcc_assert (CONST_INT_P (width));
+  gcc_assert (CONST_INT_P (pos));
+
+  unsigned HOST_WIDE_INT mask
+    = ((unsigned HOST_WIDE_INT) 1 << UINTVAL (width)) - 1;
+  return GEN_INT (mask << UINTVAL (pos));
+}
+
 bool
 aarch64_simd_imm_scalar_p (rtx x, machine_mode mode ATTRIBUTE_UNUSED)
 {

gcc/config/aarch64/aarch64.md

@@ -3683,6 +3683,28 @@
   [(set_attr "type" "logics_reg,logics_imm")]
 )
 
+(define_insn "*and<mode>3nr_compare0_zextract"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (zero_extract:GPI (match_operand:GPI 0 "register_operand" "r")
+		  (match_operand:GPI 1 "const_int_operand" "n")
+		  (match_operand:GPI 2 "const_int_operand" "n"))
+	 (const_int 0)))]
+  "INTVAL (operands[1]) > 0
+   && ((INTVAL (operands[1]) + INTVAL (operands[2]))
+	<= GET_MODE_BITSIZE (<MODE>mode))
+   && aarch64_bitmask_imm (
+	UINTVAL (aarch64_mask_from_zextract_ops (operands[1],
+						 operands[2])),
+	<MODE>mode)"
+  {
+    operands[1]
+      = aarch64_mask_from_zextract_ops (operands[1], operands[2]);
+    return "tst\\t%<w>0, %1";
+  }
+  [(set_attr "type" "logics_shift_imm")]
+)
+
 (define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
 	(compare:CC_NZ

gcc/testsuite/ChangeLog

+2015-12-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR rtl-optimization/68796
+	* gcc.target/aarch64/tst_3.c: New test.
+	* gcc.target/aarch64/tst_4.c: Likewise.
+
 2015-12-18  Robin Dapp  <rdapp@linux.vnet.ibm.com>
 
 	* gcc.target/s390/vcond-shift.c: New test to check vcond

gcc/testsuite/gcc.target/aarch64/tst_3.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+f1 (int x)
+{
+  if (x & 1)
+    return 1;
+  return x;
+}
+
+/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]*.*1" } } */

gcc/testsuite/gcc.target/aarch64/tst_4.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+f1 (long x)
+{
+   return ((short) x >= 0) ? x : 0;
+}
+
+/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]*.*32768\n" } } */