Commit 916c0f6a by Robin Dapp Committed by Andreas Krebbel

S/390: Turn constm1_operand into all_ones_operand

gcc/ChangeLog:

2015-12-18 Robin Dapp <rdapp@linux.vnet.ibm.com>

	* config/s390/predicates.md: Change and rename
	constm1_operand to all_ones_operand
	* config/s390/s390.c (s390_expand_vcond): Use all_ones_operand
	* config/s390/vector.md: Likewise

From-SVN: r231809
parent d958ae79
2015-12-18 Robin Dapp <rdapp@linux.vnet.ibm.com>
* config/s390/predicates.md: Change and rename
constm1_operand to all_ones_operand
* config/s390/s390.c (s390_expand_vcond): Use all_ones_operand
* config/s390/vector.md: Likewise
2015-12-18 Robin Dapp <rdapp@linux.vnet.ibm.com> 2015-12-18 Robin Dapp <rdapp@linux.vnet.ibm.com>
* config/s390/s390.c (s390_expand_vcond): Convert vector * config/s390/s390.c (s390_expand_vcond): Convert vector
...@@ -29,9 +29,10 @@ ...@@ -29,9 +29,10 @@
(and (match_code "const_int,const_wide_int,const_double,const_vector") (and (match_code "const_int,const_wide_int,const_double,const_vector")
(match_test "op == CONST0_RTX (mode)"))) (match_test "op == CONST0_RTX (mode)")))
;; Return true if OP an all ones operand (int/float/vector). ;; Return true if OP an all ones operand (int/vector).
(define_predicate "constm1_operand" (define_predicate "all_ones_operand"
(and (match_code "const_int,const_wide_int,const_double,const_vector") (and (match_code "const_int, const_wide_int, const_vector")
(match_test "INTEGRAL_MODE_P (GET_MODE (op))")
(match_test "op == CONSTM1_RTX (mode)"))) (match_test "op == CONSTM1_RTX (mode)")))
;; Return true if OP is a 4 bit mask operand ;; Return true if OP is a 4 bit mask operand
......
...@@ -6169,7 +6169,7 @@ s390_expand_vcond (rtx target, rtx then, rtx els, ...@@ -6169,7 +6169,7 @@ s390_expand_vcond (rtx target, rtx then, rtx els,
} }
/* if x < 0 ? -1 : 0 or if x >= 0 ? 0 : -1 */ /* if x < 0 ? -1 : 0 or if x >= 0 ? 0 : -1 */
else if (constm1_operand (negop, target_mode)) else if (all_ones_operand (negop, target_mode))
{ {
rtx res = expand_simple_binop (cmp_mode, ASHIFTRT, cmp_op1, rtx res = expand_simple_binop (cmp_mode, ASHIFTRT, cmp_op1,
GEN_INT (shift), target, GEN_INT (shift), target,
...@@ -6199,7 +6199,7 @@ s390_expand_vcond (rtx target, rtx then, rtx els, ...@@ -6199,7 +6199,7 @@ s390_expand_vcond (rtx target, rtx then, rtx els,
/* If the results are supposed to be either -1 or 0 we are done /* If the results are supposed to be either -1 or 0 we are done
since this is what our compare instructions generate anyway. */ since this is what our compare instructions generate anyway. */
if (constm1_operand (then, GET_MODE (then)) if (all_ones_operand (then, GET_MODE (then))
&& const0_operand (els, GET_MODE (els))) && const0_operand (els, GET_MODE (els)))
{ {
emit_move_insn (target, gen_rtx_SUBREG (target_mode, emit_move_insn (target, gen_rtx_SUBREG (target_mode,
......
...@@ -1107,7 +1107,7 @@ ...@@ -1107,7 +1107,7 @@
(eq (match_operand:<tointvec> 3 "register_operand" "") (eq (match_operand:<tointvec> 3 "register_operand" "")
(match_operand:V 4 "const0_operand" "")) (match_operand:V 4 "const0_operand" ""))
(match_operand:V 1 "const0_operand" "") (match_operand:V 1 "const0_operand" "")
(match_operand:V 2 "constm1_operand" "")))] (match_operand:V 2 "all_ones_operand" "")))]
"TARGET_VX" "TARGET_VX"
[(set (match_dup 0) (match_dup 3))] [(set (match_dup 0) (match_dup 3))]
{ {
...@@ -1120,7 +1120,7 @@ ...@@ -1120,7 +1120,7 @@
(if_then_else:V (if_then_else:V
(eq (match_operand:<tointvec> 3 "register_operand" "") (eq (match_operand:<tointvec> 3 "register_operand" "")
(match_operand:V 4 "const0_operand" "")) (match_operand:V 4 "const0_operand" ""))
(match_operand:V 1 "constm1_operand" "") (match_operand:V 1 "all_ones_operand" "")
(match_operand:V 2 "const0_operand" "")))] (match_operand:V 2 "const0_operand" "")))]
"TARGET_VX" "TARGET_VX"
[(set (match_dup 0) (not:V (match_dup 3)))] [(set (match_dup 0) (not:V (match_dup 3)))]
...@@ -1134,7 +1134,7 @@ ...@@ -1134,7 +1134,7 @@
(if_then_else:V (if_then_else:V
(ne (match_operand:<tointvec> 3 "register_operand" "") (ne (match_operand:<tointvec> 3 "register_operand" "")
(match_operand:V 4 "const0_operand" "")) (match_operand:V 4 "const0_operand" ""))
(match_operand:V 1 "constm1_operand" "") (match_operand:V 1 "all_ones_operand" "")
(match_operand:V 2 "const0_operand" "")))] (match_operand:V 2 "const0_operand" "")))]
"TARGET_VX" "TARGET_VX"
[(set (match_dup 0) (match_dup 3))] [(set (match_dup 0) (match_dup 3))]
...@@ -1149,7 +1149,7 @@ ...@@ -1149,7 +1149,7 @@
(ne (match_operand:<tointvec> 3 "register_operand" "") (ne (match_operand:<tointvec> 3 "register_operand" "")
(match_operand:V 4 "const0_operand" "")) (match_operand:V 4 "const0_operand" ""))
(match_operand:V 1 "const0_operand" "") (match_operand:V 1 "const0_operand" "")
(match_operand:V 2 "constm1_operand" "")))] (match_operand:V 2 "all_ones_operand" "")))]
"TARGET_VX" "TARGET_VX"
[(set (match_dup 0) (not:V (match_dup 3)))] [(set (match_dup 0) (not:V (match_dup 3)))]
{ {
...@@ -1185,7 +1185,7 @@ ...@@ -1185,7 +1185,7 @@
[(set (match_operand:V 0 "register_operand" "=v") [(set (match_operand:V 0 "register_operand" "=v")
(if_then_else:V (if_then_else:V
(eq (match_operand:<tointvec> 3 "register_operand" "v") (eq (match_operand:<tointvec> 3 "register_operand" "v")
(match_operand:<tointvec> 4 "constm1_operand" "")) (match_operand:<tointvec> 4 "all_ones_operand" ""))
(match_operand:V 1 "register_operand" "v") (match_operand:V 1 "register_operand" "v")
(match_operand:V 2 "register_operand" "v")))] (match_operand:V 2 "register_operand" "v")))]
"TARGET_VX" "TARGET_VX"
...@@ -1197,7 +1197,7 @@ ...@@ -1197,7 +1197,7 @@
[(set (match_operand:V 0 "register_operand" "=v") [(set (match_operand:V 0 "register_operand" "=v")
(if_then_else:V (if_then_else:V
(eq (not:<tointvec> (match_operand:<tointvec> 3 "register_operand" "v")) (eq (not:<tointvec> (match_operand:<tointvec> 3 "register_operand" "v"))
(match_operand:<tointvec> 4 "constm1_operand" "")) (match_operand:<tointvec> 4 "all_ones_operand" ""))
(match_operand:V 1 "register_operand" "v") (match_operand:V 1 "register_operand" "v")
(match_operand:V 2 "register_operand" "v")))] (match_operand:V 2 "register_operand" "v")))]
"TARGET_VX" "TARGET_VX"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment