rs6000: Use brace blocks in define_insn

This patch changes the remaining cases in our machine description files
to use brace blocks instead of double-quoted strings as the output
control string.  This increases readability by making the blocks look
more like normal C code, mostly because backslash quoting is no longer
needed.  It also removes such quoting where it was still there (usually
harmless but always confusing). and it writes "\n\t" as "\;" in one
place where we didn't already.


	* config/rs6000/altivec.md: Write output control strings as braced
	blocks instead of double-quoted strings.
	* config/rs6000/darwin.md: Ditto.
	* config/rs6000/rs6000.md: Ditto.
	* config/rs6000/vector.md: Ditto.
	* config/rs6000/vsx.md: Ditto.

From-SVN: r257889

gcc/ChangeLog

+2018-02-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/altivec.md: Write output control strings as braced
+	blocks instead of double-quoted strings.
+	* config/rs6000/darwin.md: Ditto.
+	* config/rs6000/rs6000.md: Ditto.
+	* config/rs6000/vector.md: Ditto.
+	* config/rs6000/vsx.md: Ditto.
+
 2018-02-21  Jason Merrill  <jason@redhat.com>
 
 	PR c++/84314 - ICE with templates and fastcall attribute.

gcc/config/rs6000/darwin.md

@@ -31,28 +31,27 @@ You should have received a copy of the GNU General Public License
         (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                            (match_operand 2 "" ""))))]
   "TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"lfd %0,lo16(%2)(%1)\";
+	return "lfd %0,lo16(%2)(%1)";
       case 1:
 	{
 	  if (TARGET_POWERPC64 && TARGET_32BIT)
 	    /* Note, old assemblers didn't support relocation here.  */
-	    return \"ld %0,lo16(%2)(%1)\";
+	    return "ld %0,lo16(%2)(%1)";
 	  else
 	    {
-	      output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
-	      output_asm_insn (\"lwz %L0,4(%0)\", operands);
-	      return (\"lwz %0,0(%0)\");
+	      output_asm_insn ("la %0,lo16(%2)(%1)", operands);
+	      output_asm_insn ("lwz %L0,4(%0)", operands);
+	      return ("lwz %0,0(%0)");
 	    }
 	}
       default:
 	gcc_unreachable ();
     }
-}"
+}
   [(set_attr "type" "load")
    (set_attr "length" "4,12")])
 
@@ -62,18 +61,17 @@ You should have received a copy of the GNU General Public License
         (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                            (match_operand 2 "" ""))))]
   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"lfd %0,lo16(%2)(%1)\";
+	return "lfd %0,lo16(%2)(%1)";
       case 1:
-	return \"ld %0,lo16(%2)(%1)\";
+	return "ld %0,lo16(%2)(%1)";
       default:
 	gcc_unreachable ();
     }
-}"
+}
   [(set_attr "type" "load")
    (set_attr "length" "4,4")])
 
@@ -262,7 +260,7 @@ You should have received a copy of the GNU General Public License
 #else
   gcc_unreachable ();
 #endif
-  return "bcl 20,31,%0\\n%0:";
+  return "bcl 20,31,%0\n%0:";
 }
   [(set_attr "type" "branch")
    (set_attr "cannot_copy" "yes")
@@ -279,7 +277,7 @@ You should have received a copy of the GNU General Public License
 #else
   gcc_unreachable ();
 #endif
-  return "bcl 20,31,%0\\n%0:";
+  return "bcl 20,31,%0\n%0:";
 }
   [(set_attr "type" "branch")
    (set_attr "cannot_copy" "yes")
@@ -408,14 +406,14 @@ You should have received a copy of the GNU General Public License
     {
       static char tmp[64];
       const char *cnam = machopic_get_function_picbase ();
-      snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
+      snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
       return tmp;
     }
   else
 #else
   gcc_unreachable ();
 #endif
-    return "bcl 20,31,%0\\n%0:";
+    return "bcl 20,31,%0\n%0:";
 }
   [(set_attr "type" "branch")
    (set_attr "cannot_copy" "yes")
@@ -432,14 +430,14 @@ You should have received a copy of the GNU General Public License
     {
       static char tmp[64];
       const char *cnam = machopic_get_function_picbase ();
-      snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
+      snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
       return tmp;
     }
   else
 #else
   gcc_unreachable ();
 #endif
-    return "bcl 20,31,%0\\n%0:";
+    return "bcl 20,31,%0\n%0:";
 }
   [(set_attr "type" "branch")
    (set_attr "cannot_copy" "yes")

gcc/config/rs6000/vector.md

@@ -181,7 +181,6 @@
   [(set (match_operand:VEC_M 0 "vfloat_operand" "")
 	(match_operand:VEC_M 1 "memory_operand" ""))]
   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 
@@ -198,13 +197,12 @@
         emit_insn (gen_altivec_lvx_<mode>_1op (operands[0], operands[1]));
       DONE;
     }
-}")
+})
 
 (define_expand "vector_altivec_store_<mode>"
   [(set (match_operand:VEC_M 0 "memory_operand" "")
 	(match_operand:VEC_M 1 "vfloat_operand" ""))]
   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 
@@ -221,7 +219,7 @@
         emit_insn (gen_altivec_stvx_<mode>_1op (operands[1], operands[0]));
       DONE;
     }
-}")
+})
 
 
 
@@ -272,27 +270,25 @@
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 	(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
     {
       emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
       DONE;
     }
-}")
+})
 
 (define_expand "abs<mode>2"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 	(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
     {
       emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
       DONE;
     }
-}")
+})
 
 (define_expand "smin<mode>3"
   [(set (match_operand:VEC_F 0 "register_operand" "")
@@ -369,7 +365,6 @@
 	(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
 		       (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
     {
@@ -377,7 +372,7 @@
 					     operands[2]));
       DONE;
     }
-}")
+})
 
 
 ;; Vector comparisons
@@ -390,14 +385,13 @@
 	 (match_operand:VEC_F 1 "vfloat_operand" "")
 	 (match_operand:VEC_F 2 "vfloat_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 				    operands[3], operands[4], operands[5]))
     DONE;
   else
     FAIL;
-}")
+})
 
 (define_expand "vcond<mode><mode>"
   [(set (match_operand:VEC_I 0 "vint_operand")
@@ -408,14 +402,13 @@
 	 (match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
 	 (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 				    operands[3], operands[4], operands[5]))
     DONE;
   else
     FAIL;
-}")
+})
 
 (define_expand "vcondv4sfv4si"
   [(set (match_operand:V4SF 0 "vfloat_operand" "")
@@ -427,14 +420,13 @@
 	 (match_operand:V4SF 2 "vfloat_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
-  "
 {
   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 				    operands[3], operands[4], operands[5]))
     DONE;
   else
     FAIL;
-}")
+})
 
 (define_expand "vcondv4siv4sf"
   [(set (match_operand:V4SI 0 "vint_operand" "")
@@ -446,14 +438,13 @@
 	 (match_operand:V4SI 2 "vint_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
-  "
 {
   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 				    operands[3], operands[4], operands[5]))
     DONE;
   else
     FAIL;
-}")
+})
 
 (define_expand "vcondv2dfv2di"
   [(set (match_operand:V2DF 0 "vfloat_operand")
@@ -500,14 +491,13 @@
 	 (match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
 	 (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 				    operands[3], operands[4], operands[5]))
     DONE;
   else
     FAIL;
-}")
+})
 
 (define_expand "vconduv4sfv4si"
   [(set (match_operand:V4SF 0 "vfloat_operand" "")
@@ -519,14 +509,13 @@
 	 (match_operand:V4SF 2 "vfloat_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
-  "
 {
   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 				    operands[3], operands[4], operands[5]))
     DONE;
   else
     FAIL;
-}")
+})
 
 (define_expand "vconduv2dfv2di"
   [(set (match_operand:V2DF 0 "vfloat_operand")
@@ -575,10 +564,9 @@
    (set (match_operand:VEC_I 0 "vlogical_operand" "")
         (not:VEC_I (match_dup 3)))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
 
 (define_expand "vector_gtu<mode>"
   [(set (match_operand:VEC_I 0 "vint_operand" "")
@@ -595,10 +583,9 @@
    (set (match_operand:VEC_I 0 "vlogical_operand" "")
         (not:VEC_I (match_dup 3)))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
 
 (define_expand "vector_geu<mode>"
   [(set (match_operand:VEC_I 0 "vint_operand" "")
@@ -615,10 +602,9 @@
    (set (match_operand:VEC_I 0 "vlogical_operand" "")
         (not:VEC_I (match_dup 3)))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
 
 (define_expand "vector_ngtu<mode>"
   [(set (match_operand:VEC_I 3 "vlogical_operand" "")
@@ -627,10 +613,9 @@
    (set (match_operand:VEC_I 0 "vlogical_operand" "")
         (not:VEC_I (match_dup 3)))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
 
 (define_insn_and_split "*vector_uneq<mode>"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
@@ -669,11 +654,10 @@
    (set (match_dup 0)
 	(ior:VEC_F (match_dup 3)
 		   (match_dup 4)))]
-  "
 {
   operands[3] = gen_reg_rtx (<MODE>mode);
   operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
 
 (define_insn_and_split "*vector_ordered<mode>"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
@@ -691,11 +675,10 @@
    (set (match_dup 0)
 	(ior:VEC_F (match_dup 3)
 		   (match_dup 4)))]
-  "
 {
   operands[3] = gen_reg_rtx (<MODE>mode);
   operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
 
 (define_insn_and_split "*vector_unordered<mode>"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
@@ -713,11 +696,10 @@
    (set (match_dup 0)
         (and:VEC_F (not:VEC_F (match_dup 3))
                    (not:VEC_F (match_dup 4))))]
-  "
 {
   operands[3] = gen_reg_rtx (<MODE>mode);
   operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
 
 ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
 ;; which is in the reverse order that we want
@@ -1030,53 +1012,49 @@
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 	(float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
     {
       emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
       DONE;
     }
-}")
+})
 
 (define_expand "floatuns<VEC_int><mode>2"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 	(unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
     {
       emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
       DONE;
     }
-}")
+})
 
 (define_expand "fix_trunc<mode><VEC_int>2"
   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 	(fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
     {
       emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
       DONE;
     }
-}")
+})
 
 (define_expand "fixuns_trunc<mode><VEC_int>2"
   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 	(unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
     {
       emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
       DONE;
     }
-}")
+})
 
 
 ;; Vector initialization, set, extract
@@ -1273,7 +1251,6 @@
    (match_operand:VEC_L 1 "vlogical_operand" "")
    (match_operand:QI 2 "reg_or_short_operand" "")]
   "TARGET_ALTIVEC"
-  "
 {
   rtx bitshift = operands[2];
   rtx shift;
@@ -1315,7 +1292,7 @@
 
   emit_insn (insn);
   DONE;
-}")
+})
 
 ;; Expanders for rotate each element in a vector
 (define_expand "vrotl<mode>3"

gcc/config/rs6000/vsx.md

@@ -443,7 +443,6 @@
         (vec_select:<MODE>
           (match_dup 2)
           (parallel [(const_int 1) (const_int 0)])))]
-  "
 {
   rtx mem = operands[1];
 
@@ -475,7 +474,6 @@
   operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
                                        : operands[0];
 }
-  "
   [(set_attr "type" "vecload")
    (set_attr "length" "8")])
 
@@ -495,7 +493,6 @@
           (match_dup 2)
           (parallel [(const_int 2) (const_int 3)
                      (const_int 0) (const_int 1)])))]
-  "
 {
   rtx mem = operands[1];
 
@@ -527,7 +524,6 @@
   operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
                                        : operands[0];
 }
-  "
   [(set_attr "type" "vecload")
    (set_attr "length" "8")])
 
@@ -551,7 +547,6 @@
                      (const_int 6) (const_int 7)
                      (const_int 0) (const_int 1)
                      (const_int 2) (const_int 3)])))]
-  "
 {
   rtx mem = operands[1];
 
@@ -583,7 +578,6 @@
   operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
                                        : operands[0];
 }
-  "
   [(set_attr "type" "vecload")
    (set_attr "length" "8")])
 
@@ -615,7 +609,6 @@
                      (const_int 2) (const_int 3)
                      (const_int 4) (const_int 5)
                      (const_int 6) (const_int 7)])))]
-  "
 {
   rtx mem = operands[1];
 
@@ -647,7 +640,6 @@
   operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
                                        : operands[0];
 }
-  "
   [(set_attr "type" "vecload")
    (set_attr "length" "8")])
 
@@ -1037,7 +1029,6 @@
    #"
   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
   [(const_int 0)]
-  "
 {
   rtx tmp = (can_create_pseudo_p ()
 	     ? gen_reg_rtx_and_attrs (operands[0])
@@ -1046,7 +1037,6 @@
   rs6000_emit_le_vsx_permute (operands[0], tmp, <MODE>mode);
   DONE;
 }
-  "
   [(set_attr "type" "vecload,load")
    (set_attr "length" "8,8")])
 
@@ -1640,7 +1630,6 @@
   "#"
   "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
   [(const_int 0)]
-  "
 {
   rtx op0 = operands[0];
   rtx op1 = operands[1];
@@ -1668,7 +1657,7 @@
     }
   emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
   DONE;
-}"
+}
   [(set_attr "type" "mul")])
 
 (define_insn "*vsx_div<mode>3"
@@ -1690,7 +1679,6 @@
   "#"
   "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
   [(const_int 0)]
-  "
 {
   rtx op0 = operands[0];
   rtx op1 = operands[1];
@@ -1726,7 +1714,7 @@
     }
   emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
   DONE;
-}"
+}
   [(set_attr "type" "div")])
 
 (define_insn_and_split "vsx_udiv_v2di"
@@ -1738,7 +1726,6 @@
   "#"
   "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
   [(const_int 0)]
-  "
 {
   rtx op0 = operands[0];
   rtx op1 = operands[1];
@@ -1774,7 +1761,7 @@
     }
   emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
   DONE;
-}"
+}
   [(set_attr "type" "div")])
 
 ;; *tdiv* instruction returning the FG flag
@@ -4328,7 +4315,6 @@
   "#"
   ""
   [(const_int 0)]
-  "
 {
   rtx tmp = (GET_CODE (operands[2]) == SCRATCH)
 	     ? gen_reg_rtx (V2DFmode)
@@ -4336,7 +4322,7 @@
   emit_insn (gen_vsx_xxsldwi_v2df (tmp, operands[1], operands[1], const2_rtx));
   emit_insn (gen_<VEC_reduc_rtx>v2df3 (operands[0], tmp, operands[1]));
   DONE;
-}"
+}
   [(set_attr "length" "8")
    (set_attr "type" "veccomplex")])
 
@@ -4351,7 +4337,6 @@
   "#"
   ""
   [(const_int 0)]
-  "
 {
   rtx op0 = operands[0];
   rtx op1 = operands[1];
@@ -4375,7 +4360,7 @@
   emit_insn (gen_vsx_xxsldwi_v4sf (tmp4, tmp3, tmp3, GEN_INT (3)));
   emit_insn (gen_<VEC_reduc_rtx>v4sf3 (op0, tmp4, tmp3));
   DONE;
-}"
+}
   [(set_attr "length" "16")
    (set_attr "type" "veccomplex")])
 
@@ -4400,7 +4385,6 @@
   "#"
   ""
   [(const_int 0)]
-  "
 {
   rtx hi = gen_highpart (DFmode, operands[1]);
   rtx lo = (GET_CODE (operands[2]) == SCRATCH)
@@ -4410,7 +4394,7 @@
   emit_insn (gen_vsx_extract_v2df (lo, operands[1], const1_rtx));
   emit_insn (gen_<VEC_reduc_rtx>df3 (operands[0], hi, lo));
   DONE;
-}"
+}
   [(set_attr "length" "8")
    (set_attr "type" "veccomplex")])
 
@@ -4428,7 +4412,6 @@
   "#"
   ""
   [(const_int 0)]
-  "
 {
   rtx op0 = operands[0];
   rtx op1 = operands[1];
@@ -4455,7 +4438,7 @@
   emit_insn (gen_<VEC_reduc_rtx>v4sf3 (tmp5, tmp4, tmp3));
   emit_insn (gen_vsx_xscvspdp_scalar2 (op0, tmp5));
   DONE;
-}"
+}
   [(set_attr "length" "20")
    (set_attr "type" "veccomplex")])