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riscv-gcc-1
Commit 6c332313 by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: Use brace blocks in define_insn 

This patch changes the remaining cases in our machine description files
to use brace blocks instead of double-quoted strings as the output
control string.  This increases readability by making the blocks look
more like normal C code, mostly because backslash quoting is no longer
needed.  It also removes such quoting where it was still there (usually
harmless but always confusing). and it writes "\n\t" as "\;" in one
place where we didn't already.


	* config/rs6000/altivec.md: Write output control strings as braced
	blocks instead of double-quoted strings.
	* config/rs6000/darwin.md: Ditto.
	* config/rs6000/rs6000.md: Ditto.
	* config/rs6000/vector.md: Ditto.
	* config/rs6000/vsx.md: Ditto.

From-SVN: r257889
parent 78a85122
Showing with 258 additions and 388 deletions
gcc/ChangeLog
2018-02-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Write output control strings as braced
blocks instead of double-quoted strings.
* config/rs6000/darwin.md: Ditto.
* config/rs6000/rs6000.md: Ditto.
* config/rs6000/vector.md: Ditto.
* config/rs6000/vsx.md: Ditto.
2018-02-21 Jason Merrill <jason@redhat.com>
PR c++/84314 - ICE with templates and fastcall attribute.
......
gcc/config/rs6000/altivec.md
......@@ -1680,13 +1680,12 @@
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VPKPX))]
"TARGET_ALTIVEC"
"*
{
if (VECTOR_ELT_ORDER_BIG)
return \"vpkpx %0,%1,%2\";
else
return \"vpkpx %0,%2,%1\";
}"
{
if (VECTOR_ELT_ORDER_BIG)
return "vpkpx %0,%1,%2";
else
return "vpkpx %0,%2,%1";
}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>ss"
......@@ -1695,13 +1694,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_SIGN_SAT))]
"<VI_unit>"
"*
{
if (VECTOR_ELT_ORDER_BIG)
return \"vpks<VI_char>ss %0,%1,%2\";
else
return \"vpks<VI_char>ss %0,%2,%1\";
}"
{
if (VECTOR_ELT_ORDER_BIG)
return "vpks<VI_char>ss %0,%1,%2";
else
return "vpks<VI_char>ss %0,%2,%1";
}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>us"
......@@ -1710,13 +1708,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_UNS_SAT))]
"<VI_unit>"
"*
{
if (VECTOR_ELT_ORDER_BIG)
return \"vpks<VI_char>us %0,%1,%2\";
else
return \"vpks<VI_char>us %0,%2,%1\";
}"
{
if (VECTOR_ELT_ORDER_BIG)
return "vpks<VI_char>us %0,%1,%2";
else
return "vpks<VI_char>us %0,%2,%1";
}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>us"
......@@ -1725,13 +1722,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_SAT))]
"<VI_unit>"
"*
{
if (VECTOR_ELT_ORDER_BIG)
return \"vpku<VI_char>us %0,%1,%2\";
else
return \"vpku<VI_char>us %0,%2,%1\";
}"
{
if (VECTOR_ELT_ORDER_BIG)
return "vpku<VI_char>us %0,%1,%2";
else
return "vpku<VI_char>us %0,%2,%1";
}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um"
......@@ -1740,13 +1736,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD))]
"<VI_unit>"
"*
{
if (VECTOR_ELT_ORDER_BIG)
return \"vpku<VI_char>um %0,%1,%2\";
else
return \"vpku<VI_char>um %0,%2,%1\";
}"
{
if (VECTOR_ELT_ORDER_BIG)
return "vpku<VI_char>um %0,%1,%2";
else
return "vpku<VI_char>um %0,%2,%1";
}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um_direct"
......@@ -1755,13 +1750,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))]
"<VI_unit>"
"*
{
if (BYTES_BIG_ENDIAN)
return \"vpku<VI_char>um %0,%1,%2\";
else
return \"vpku<VI_char>um %0,%2,%1\";
}"
{
if (BYTES_BIG_ENDIAN)
return "vpku<VI_char>um %0,%1,%2";
else
return "vpku<VI_char>um %0,%2,%1";
}
[(set_attr "type" "vecperm")])
(define_insn "*altivec_vrl<VI_char>"
......@@ -2348,7 +2342,6 @@
(use (match_operand:V4SF 1 "register_operand" ""))
(use (match_operand:V4SF 2 "register_operand" ""))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
"
{
rtx mask = gen_reg_rtx (V4SImode);
rtvec v = rtvec_alloc (4);
......@@ -2363,7 +2356,7 @@
emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],
gen_lowpart (V4SFmode, mask)));
DONE;
}")
})
(define_insn "altivec_vsldoi_<mode>"
[(set (match_operand:VM 0 "register_operand" "=v")
......@@ -2670,8 +2663,7 @@
[(set (match_operand:V16QI 0 "register_operand" "")
(unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
"TARGET_ALTIVEC"
"
{
{
rtx addr;
rtx temp;
......@@ -2683,7 +2675,7 @@
emit_insn (gen_altivec_lvsr (operands[0],
replace_equiv_address (operands[1], temp)));
DONE;
}")
})
;; Parallel some of the LVE* and STV*'s with unspecs because some have
;; identical rtl but different instructions-- and gcc gets confused.
......@@ -3361,12 +3353,11 @@
(match_operand:VIshort 2 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
"
{
{
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
DONE;
}")
})
(define_expand "sdot_prodv8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
......@@ -3374,11 +3365,10 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
"
{
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
DONE;
}")
})
(define_expand "widen_usum<mode>3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
......@@ -3386,14 +3376,13 @@
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
"
{
rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
DONE;
}")
})
(define_expand "widen_ssumv16qi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
......@@ -3401,14 +3390,13 @@
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VMSUMM)))]
"TARGET_ALTIVEC"
"
{
rtx vones = gen_reg_rtx (V16QImode);
emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
DONE;
}")
})
(define_expand "widen_ssumv8hi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
......@@ -3416,14 +3404,13 @@
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
"
{
rtx vones = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vspltish (vones, const1_rtx));
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
DONE;
}")
})
(define_expand "vec_unpacks_hi_<VP_small_lc>"
[(set (match_operand:VP 0 "register_operand" "=v")
......@@ -3471,7 +3458,6 @@
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKHUB))]
"TARGET_ALTIVEC"
"
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
......@@ -3500,14 +3486,13 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
}")
})
(define_expand "vec_unpacku_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKHUH))]
"TARGET_ALTIVEC"
"
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
......@@ -3536,14 +3521,13 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
}")
})
(define_expand "vec_unpacku_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKLUB))]
"TARGET_ALTIVEC"
"
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
......@@ -3572,14 +3556,13 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
}")
})
(define_expand "vec_unpacku_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKLUH))]
"TARGET_ALTIVEC"
"
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
......@@ -3608,7 +3591,7 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
}")
})
(define_expand "vec_widen_umult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
......@@ -3616,7 +3599,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHUB))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
......@@ -3634,7 +3616,7 @@
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_widen_umult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
......@@ -3642,7 +3624,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLUB))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
......@@ -3660,7 +3641,7 @@
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_widen_smult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
......@@ -3668,7 +3649,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHSB))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
......@@ -3686,7 +3666,7 @@
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_widen_smult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
......@@ -3694,7 +3674,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLSB))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
......@@ -3712,7 +3691,7 @@
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_widen_umult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
......@@ -3720,7 +3699,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHUH))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
......@@ -3738,7 +3716,7 @@
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_widen_umult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
......@@ -3746,7 +3724,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLUH))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
......@@ -3764,7 +3741,7 @@
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_widen_smult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
......@@ -3772,7 +3749,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHSH))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
......@@ -3790,7 +3766,7 @@
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_widen_smult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
......@@ -3798,7 +3774,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLSH))]
"TARGET_ALTIVEC"
"
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
......@@ -3816,7 +3791,7 @@
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
}")
})
(define_expand "vec_pack_trunc_<mode>"
[(set (match_operand:<VP_small> 0 "register_operand" "=v")
......@@ -3831,7 +3806,6 @@
(mult:V16QI (match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"
{
rtx even = gen_reg_rtx (V8HImode);
rtx odd = gen_reg_rtx (V8HImode);
......@@ -3851,13 +3825,12 @@
emit_insn (gen_altivec_vmulosb (odd, operands[1], operands[2]));
emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], even, odd, mask));
DONE;
}")
})
(define_expand "altivec_negv4sf2"
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))]
"TARGET_ALTIVEC"
"
{
rtx neg0;
......@@ -3871,7 +3844,7 @@
gen_lowpart (V4SFmode, neg0), operands[1]));
DONE;
}")
})
;; Vector reverse elements
(define_expand "altivec_vreve<mode>2"
......@@ -3973,56 +3946,52 @@
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
}")
})
(define_expand "vec_unpacks_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
}")
})
(define_expand "vec_unpacku_float_hi_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
}")
})
(define_expand "vec_unpacku_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
}")
})
;; Power8/power9 vector instructions encoded as Altivec instructions
......
gcc/config/rs6000/darwin.md
......@@ -31,28 +31,27 @@ You should have received a copy of the GNU General Public License
(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
"*
{
switch (which_alternative)
{
case 0:
return \"lfd %0,lo16(%2)(%1)\";
return "lfd %0,lo16(%2)(%1)";
case 1:
{
if (TARGET_POWERPC64 && TARGET_32BIT)
/* Note, old assemblers didn't support relocation here. */
return \"ld %0,lo16(%2)(%1)\";
return "ld %0,lo16(%2)(%1)";
else
{
output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
output_asm_insn (\"lwz %L0,4(%0)\", operands);
return (\"lwz %0,0(%0)\");
output_asm_insn ("la %0,lo16(%2)(%1)", operands);
output_asm_insn ("lwz %L0,4(%0)", operands);
return ("lwz %0,0(%0)");
}
}
default:
gcc_unreachable ();
}
}"
}
[(set_attr "type" "load")
(set_attr "length" "4,12")])
......@@ -62,18 +61,17 @@ You should have received a copy of the GNU General Public License
(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"*
{
switch (which_alternative)
{
case 0:
return \"lfd %0,lo16(%2)(%1)\";
return "lfd %0,lo16(%2)(%1)";
case 1:
return \"ld %0,lo16(%2)(%1)\";
return "ld %0,lo16(%2)(%1)";
default:
gcc_unreachable ();
}
}"
}
[(set_attr "type" "load")
(set_attr "length" "4,4")])
......@@ -262,7 +260,7 @@ You should have received a copy of the GNU General Public License
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
......@@ -279,7 +277,7 @@ You should have received a copy of the GNU General Public License
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
......@@ -408,14 +406,14 @@ You should have received a copy of the GNU General Public License
{
static char tmp[64];
const char *cnam = machopic_get_function_picbase ();
snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
return tmp;
}
else
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
......@@ -432,14 +430,14 @@ You should have received a copy of the GNU General Public License
{
static char tmp[64];
const char *cnam = machopic_get_function_picbase ();
snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
return tmp;
}
else
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
......
gcc/config/rs6000/rs6000.md
......@@ -2595,7 +2595,6 @@
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -2650,7 +2649,7 @@
emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32)));
emit_insn (gen_iordi3 (dest, dest, op3));
DONE;
}")
})
(define_split
[(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
......@@ -2659,7 +2658,6 @@
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -2713,7 +2711,7 @@
emit_insn (gen_bswapsi2 (word1, op3_si));
}
DONE;
}")
})
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
......@@ -2722,7 +2720,6 @@
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -2740,7 +2737,7 @@
emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
emit_insn (gen_iordi3 (dest, dest, op3));
DONE;
}")
})
(define_insn "bswapdi2_32bit"
[(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,?&r")
......@@ -2756,7 +2753,6 @@
(clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -2801,7 +2797,7 @@
thus allowing us to omit an early clobber on the output. */
emit_insn (gen_bswapsi2 (dest1, word2));
DONE;
}")
})
(define_split
[(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
......@@ -2809,7 +2805,6 @@
(clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -2850,7 +2845,7 @@
emit_insn (gen_bswapsi2 (word2, src1));
emit_insn (gen_bswapsi2 (word1, src2));
DONE;
}")
})
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
......@@ -2858,7 +2853,6 @@
(clobber (match_operand:SI 2 "" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -2870,7 +2864,7 @@
emit_insn (gen_bswapsi2 (dest1, src2));
emit_insn (gen_bswapsi2 (dest2, src1));
DONE;
}")
})
(define_insn "mul<mode>3"
......@@ -4972,13 +4966,12 @@
(match_operand:GPR 2 "gpc_reg_operand" "")
(match_operand:GPR 3 "gpc_reg_operand" "")))]
"TARGET_ISEL"
"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
}")
})
;; We use the BASE_REGS for the isel input operands because, if rA is
;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
......@@ -5053,13 +5046,12 @@
(match_operand:SFDF 2 "gpc_reg_operand" "")
(match_operand:SFDF 3 "gpc_reg_operand" "")))]
"TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
}")
})
(define_insn "*fsel<SFDF:mode><SFDF2:mode>4"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=&<SFDF:rreg2>")
......@@ -5193,7 +5185,6 @@
"#"
""
[(pc)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -5221,7 +5212,7 @@
}
emit_insn (gen_floatdi<mode>2 (dest, tmp));
DONE;
}"
}
[(set_attr "length" "12")
(set_attr "type" "fpload")])
......@@ -5235,7 +5226,6 @@
"#"
""
[(pc)]
"
{
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
......@@ -5246,7 +5236,7 @@
emit_insn (gen_lfiwax (operands[2], operands[1]));
emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
DONE;
}"
}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
......@@ -5270,7 +5260,6 @@
"#"
""
[(pc)]
"
{
rtx dest = operands[0];
rtx src = operands[1];
......@@ -5298,7 +5287,7 @@
}
emit_insn (gen_floatdi<mode>2 (dest, tmp));
DONE;
}"
}
[(set_attr "length" "12")
(set_attr "type" "fpload")])
......@@ -5312,7 +5301,6 @@
"#"
""
[(pc)]
"
{
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
......@@ -5323,7 +5311,7 @@
emit_insn (gen_lfiwzx (operands[2], operands[1]));
emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
DONE;
}"
}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
......@@ -5341,7 +5329,6 @@
(clobber (match_dup 5))
(clobber (match_dup 6))])]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
......@@ -5365,7 +5352,7 @@
operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
operands[5] = gen_reg_rtx (DFmode);
operands[6] = gen_reg_rtx (SImode);
}")
})
(define_insn_and_split "*floatsidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
......@@ -5379,7 +5366,6 @@
"#"
""
[(pc)]
"
{
rtx lowword, highword;
gcc_assert (MEM_P (operands[4]));
......@@ -5395,7 +5381,7 @@
emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE;
}"
}
[(set_attr "length" "24")
(set_attr "type" "fp")])
......@@ -5409,7 +5395,6 @@
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
"
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
......@@ -5425,7 +5410,7 @@
emit_insn (gen_floatdisf2 (operands[0], dreg));
DONE;
}
}")
})
(define_expand "floatunssidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
......@@ -5435,7 +5420,6 @@
(clobber (match_dup 4))
(clobber (match_dup 5))])]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
......@@ -5458,7 +5442,7 @@
operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
operands[5] = gen_reg_rtx (DFmode);
}")
})
(define_insn_and_split "*floatunssidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
......@@ -5472,7 +5456,6 @@
"#"
""
[(pc)]
"
{
rtx lowword, highword;
gcc_assert (MEM_P (operands[4]));
......@@ -5486,7 +5469,7 @@
emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE;
}"
}
[(set_attr "length" "20")
(set_attr "type" "fp")])
......@@ -5597,7 +5580,6 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
"
{
if (!TARGET_P8_VECTOR)
{
......@@ -5614,7 +5596,7 @@
}
DONE;
}
}")
})
; Like the convert to float patterns, this insn must be split before
; register allocation so that it can allocate the memory slot if it
......@@ -5671,7 +5653,6 @@
"#"
""
[(pc)]
"
{
rtx lowword;
gcc_assert (MEM_P (operands[3]));
......@@ -5681,7 +5662,7 @@
emit_move_insn (operands[3], operands[2]);
emit_move_insn (operands[0], lowword);
DONE;
}"
}
[(set_attr "length" "16")
(set_attr "type" "fp")])
......@@ -5759,14 +5740,13 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
"
{
if (!TARGET_P8_VECTOR)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
}
}")
})
(define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
......@@ -6034,7 +6014,6 @@
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
"
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
......@@ -6057,7 +6036,7 @@
emit_insn (gen_floatdisf2 (operands[0], dreg));
DONE;
}
}")
})
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
......@@ -6121,7 +6100,6 @@
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
"
{
if (!TARGET_FCFIDS)
{
......@@ -6136,7 +6114,7 @@
emit_insn (gen_floatdisf2_internal1 (operands[0], val));
DONE;
}
}")
})
(define_insn "floatdisf2_fcfids"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
......@@ -6157,12 +6135,11 @@
"#"
"&& reload_completed"
[(pc)]
"
{
emit_move_insn (operands[2], operands[1]);
emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
DONE;
}"
}
[(set_attr "length" "8")])
;; This is not IEEE compliant if rounding mode is "round to nearest".
......@@ -6210,11 +6187,10 @@
(set (match_dup 0) (match_dup 1))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& !TARGET_FCFIDS"
"
{
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (CCUNSmode);
}")
})
(define_expand "floatunsdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
......@@ -6242,12 +6218,11 @@
"#"
"&& reload_completed"
[(pc)]
"
{
emit_move_insn (operands[2], operands[1]);
emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
DONE;
}"
}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
......@@ -6670,7 +6645,6 @@
(unspec:SI [(match_operand:SI 1 "got_operand" "")
(match_dup 2)] UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1"
"
{
if (GET_CODE (operands[1]) == CONST)
{
......@@ -6691,7 +6665,7 @@
}
operands[2] = rs6000_got_register (operands[1]);
}")
})
(define_insn "*movsi_got_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
......@@ -6975,13 +6949,12 @@
(set (match_dup 0)
(ior:SI (match_dup 0)
(match_dup 3)))]
"
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
}")
})
;; Split loading -128..127 to use XXSPLITB and VEXTSW2D
(define_split
......@@ -7030,7 +7003,10 @@
[(set (match_operand:INT 0 "general_operand" "")
(match_operand:INT 1 "any_operand" ""))]
""
"{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
DONE;
})
;; MR LHZ/LBZ LXSI*ZX STH/STB STXSI*X LI
;; XXLOR load 0 load -1 VSPLTI* # MFVSRWZ
......@@ -7137,7 +7113,10 @@
[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
(match_operand:FMOVE32 1 "any_operand" ""))]
"<fmove_ok>"
"{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
DONE;
})
(define_split
[(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
......@@ -7148,7 +7127,6 @@
&& GET_CODE (SUBREG_REG (operands[0])) == REG
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 3))]
"
{
long l;
......@@ -7160,7 +7138,7 @@
operands[2] = gen_lowpart (SImode, operands[0]);
operands[3] = gen_int_mode (l, SImode);
}")
})
;; Originally, we tried to keep movsf and movsd common, but the differences
;; addressing was making it rather difficult to hide with mode attributes. In
......@@ -7334,7 +7312,10 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
(match_operand:FMOVE64 1 "any_operand" ""))]
""
"{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
DONE;
})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
......@@ -7346,7 +7327,6 @@
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 1))]
"
{
int endian = (WORDS_BIG_ENDIAN == 0);
HOST_WIDE_INT value = INTVAL (operands[1]);
......@@ -7355,7 +7335,7 @@
operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
operands[4] = GEN_INT (value >> 32);
operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
}")
})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
......@@ -7367,7 +7347,6 @@
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
"
{
int endian = (WORDS_BIG_ENDIAN == 0);
long l[2];
......@@ -7378,7 +7357,7 @@
operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
operands[4] = gen_int_mode (l[endian], SImode);
operands[5] = gen_int_mode (l[1 - endian], SImode);
}")
})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
......@@ -7389,7 +7368,6 @@
&& GET_CODE (SUBREG_REG (operands[0])) == REG
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 3))]
"
{
int endian = (WORDS_BIG_ENDIAN == 0);
long l[2];
......@@ -7403,7 +7381,7 @@
| ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
operands[3] = gen_int_mode (val, DImode);
}")
})
;; Don't have reload use general registers to load a constant. It is
;; less efficient than loading the constant into an FP register, since
......@@ -7511,7 +7489,10 @@
[(set (match_operand:FMOVE128 0 "general_operand" "")
(match_operand:FMOVE128 1 "any_operand" ""))]
""
"{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
DONE;
})
;; It's important to list Y->r and r->Y before r->r because otherwise
;; reload, given m->r, will try to pick r->r and reload it, which
......@@ -7897,7 +7878,6 @@
(neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
"
{
if (FLOAT128_IEEE_P (<MODE>mode))
{
......@@ -7931,19 +7911,18 @@
}
DONE;
}
}")
})
(define_insn "neg<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d")
(neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
"*
{
if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
return \"fneg %L0,%L1\;fneg %0,%1\";
return "fneg %L0,%L1\;fneg %0,%1";
else
return \"fneg %0,%1\;fneg %L0,%L1\";
}"
return "fneg %0,%1\;fneg %L0,%L1";
}
[(set_attr "type" "fpsimple")
(set_attr "length" "8")])
......@@ -7952,7 +7931,6 @@
(abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
"
{
rtx label;
......@@ -7991,7 +7969,7 @@
FAIL;
emit_label (label);
DONE;
}")
})
(define_expand "abs<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "")
......@@ -8004,7 +7982,6 @@
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"
{
const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
......@@ -8012,7 +7989,7 @@
operands[4] = gen_reg_rtx (CCFPmode);
operands[5] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word);
operands[6] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word);
}")
})
;; Generate IEEE 128-bit -0.0 (0x80000000000000000000000000000000) in a vector
......@@ -8546,7 +8523,6 @@
&& !direct_move_p (operands[0], operands[1])"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 1))]
"
{
HOST_WIDE_INT value = INTVAL (operands[1]);
operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
......@@ -8555,7 +8531,7 @@
DImode);
operands[4] = GEN_INT (value >> 32);
operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
}")
})
(define_split
[(set (match_operand:DIFD 0 "nonimmediate_operand" "")
......@@ -8659,13 +8635,12 @@
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
}")
})
(define_split
[(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
......@@ -8673,13 +8648,12 @@
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
}")
})
(define_split
[(set (match_operand:DI 0 "altivec_register_operand" "")
......@@ -8764,7 +8738,6 @@
|| (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
"
{
operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
<MODE>mode);
......@@ -8782,7 +8755,7 @@
}
else
FAIL;
}")
})
(define_split
[(set (match_operand:TI2 0 "nonimmediate_operand" "")
......@@ -8800,7 +8773,6 @@
(use (match_operand:SI 1 "" ""))
(use (match_operand:SI 3 "" ""))])]
""
"
{
/* If value to set is not zero, use the library routine. */
if (operands[2] != const0_rtx)
......@@ -8810,7 +8782,7 @@
DONE;
else
FAIL;
}")
})
;; String compare N insn.
;; Argument 0 is the target (result)
......@@ -8891,13 +8863,12 @@
(use (match_operand:SI 2 "" ""))
(use (match_operand:SI 3 "" ""))])]
""
"
{
if (expand_block_move (operands))
DONE;
else
FAIL;
}")
})
;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also
......@@ -9352,10 +9323,9 @@
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
"
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
}"
}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
......@@ -9489,10 +9459,9 @@
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 2)
(unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
"
{
operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
}"
}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
......@@ -9587,10 +9556,9 @@
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
"
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
}"
}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
......@@ -9657,10 +9625,9 @@
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
"
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
}"
}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
......@@ -9698,12 +9665,11 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
"
{
emit_insn (gen_tls_get_tpointer_internal ());
emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
DONE;
}")
})
(define_insn "tls_get_tpointer_internal"
[(set (reg:SI 3)
......@@ -9717,14 +9683,13 @@
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
(match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
"
{
emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
emit_insn (gen_tls_get_addr_internal<mode> ());
emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
DONE;
}")
})
(define_insn "tls_get_addr_internal<mode>"
[(set (reg:P 3)
......@@ -9759,8 +9724,8 @@
(set (reg 1)
(minus (reg 1) (match_dup 1)))]
""
"
{ rtx chain = gen_reg_rtx (Pmode);
{
rtx chain = gen_reg_rtx (Pmode);
rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
rtx neg_op0;
rtx insn, par, set, mem;
......@@ -9864,7 +9829,7 @@
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE;
}")
})
;; These patterns say how to save and restore the stack pointer. We need not
;; save the stack pointer at function level since we are careful to
......@@ -9897,7 +9862,6 @@
(set (match_operand 0 "register_operand" "")
(match_operand 1 "register_operand" ""))]
""
"
{
rtvec p;
......@@ -9909,14 +9873,13 @@
RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
const0_rtx);
operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
}")
})
(define_expand "save_stack_nonlocal"
[(set (match_dup 3) (match_dup 4))
(set (match_operand 0 "memory_operand" "") (match_dup 3))
(set (match_dup 2) (match_operand 1 "register_operand" ""))]
""
"
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
......@@ -9925,7 +9888,7 @@
operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
operands[3] = gen_reg_rtx (Pmode);
operands[4] = gen_frame_mem (Pmode, operands[1]);
}")
})
(define_expand "restore_stack_nonlocal"
[(set (match_dup 2) (match_operand 1 "memory_operand" ""))
......@@ -9934,7 +9897,6 @@
(match_dup 6)
(set (match_operand 0 "register_operand" "") (match_dup 3))]
""
"
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
rtvec p;
......@@ -9949,7 +9911,7 @@
RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
const0_rtx);
operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
}")
})
;; TOC register handling.
......@@ -9960,16 +9922,15 @@
(unspec:SI [(const_int 0)] UNSPEC_TOC))
(use (reg:SI 2))])]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
"*
{
char buf[30];
extern int need_toc_init;
need_toc_init = 1;
ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
operands[2] = gen_rtx_REG (Pmode, 2);
return \"lwz %0,%1(%2)\";
}"
return "lwz %0,%1(%2)";
}
[(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
......@@ -9979,19 +9940,18 @@
(unspec:DI [(const_int 0)] UNSPEC_TOC))
(use (reg:DI 2))])]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
"*
{
char buf[30];
extern int need_toc_init;
need_toc_init = 1;
ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC",
!TARGET_ELF || !TARGET_MINIMAL_TOC);
if (TARGET_ELF)
strcat (buf, \"@toc\");
strcat (buf, "@toc");
operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
operands[2] = gen_rtx_REG (Pmode, 2);
return \"ld %0,%1(%2)\";
}"
return "ld %0,%1(%2)";
}
[(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
......@@ -10018,7 +9978,7 @@
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
"bcl 20,31,%0\\n%0:"
"bcl 20,31,%0\n%0:"
[(set_attr "type" "branch")
(set_attr "length" "4")
(set_attr "cannot_copy" "yes")])
......@@ -10029,15 +9989,14 @@
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
"*
{
char name[32];
static char templ[32];
get_ppc476_thunk_name (name);
sprintf (templ, \"bl %s\\n%%0:\", name);
sprintf (templ, "bl %s\n%%0:", name);
return templ;
}"
}
[(set_attr "type" "branch")
(set_attr "length" "4")
(set_attr "cannot_copy" "yes")])
......@@ -10069,15 +10028,14 @@
UNSPEC_TOCPTR))
(match_dup 1)]
"TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
"*
{
char name[32];
static char templ[32];
get_ppc476_thunk_name (name);
sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
sprintf (templ, "bl %s\;b $+8\;.long %%0-$", name);
return templ;
}"
}
[(set_attr "type" "branch")
(set_attr "length" "16")])
......@@ -10123,7 +10081,6 @@
"(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
|| (TARGET_TOC && TARGET_MINIMAL_TOC)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
"
{
#if TARGET_MACHO
if (DEFAULT_ABI == ABI_DARWIN)
......@@ -10134,7 +10091,7 @@
char tmplab[20];
crtl->uses_pic_offset_table = 1;
ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
ASM_GENERATE_INTERNAL_LABEL(tmplab, "LSJR",
CODE_LABEL_NUMBER (operands[0]));
tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
......@@ -10146,7 +10103,7 @@
#endif
rs6000_emit_load_toc_table (FALSE);
DONE;
}")
})
;; Largetoc support
(define_insn "*largetoc_high"
......@@ -10236,7 +10193,6 @@
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNO))])]
""
"
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
......@@ -10271,7 +10227,7 @@
gcc_unreachable ();
}
}
}")
})
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
......@@ -10280,7 +10236,6 @@
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNO))])]
""
"
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
......@@ -10315,7 +10270,7 @@
gcc_unreachable ();
}
}
}")
})
;; Call to function in current module. No TOC pointer reload needed.
;; Operand2 is nonzero if we are using the V.4 calling sequence and
......@@ -10329,16 +10284,15 @@
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -10348,16 +10302,15 @@
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -10368,16 +10321,15 @@
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -10389,16 +10341,15 @@
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -10772,7 +10723,6 @@
(match_operand 1 "" "")
(match_operand 2 "" "")])]
""
"
{
int i;
......@@ -10791,7 +10741,7 @@
emit_insn (gen_blockage ());
DONE;
}")
})
;; sibling call patterns
(define_expand "sibcall"
......@@ -10800,7 +10750,6 @@
(use (match_operand 2 "" ""))
(simple_return)])]
""
"
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
......@@ -10817,7 +10766,7 @@
rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
DONE;
}
}")
})
(define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "register_operand" "")
......@@ -10826,7 +10775,6 @@
(use (match_operand 3 "" ""))
(simple_return)])]
""
"
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
......@@ -10843,7 +10791,7 @@
rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
DONE;
}
}")
})
(define_insn "*sibcall_local32"
[(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
......@@ -10851,16 +10799,15 @@
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(simple_return)]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -10870,16 +10817,15 @@
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(simple_return)]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -10890,16 +10836,15 @@
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(simple_return)]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -10910,16 +10855,15 @@
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(simple_return)]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
output_asm_insn (\"crxor 6,6,6\", operands);
output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
output_asm_insn (\"creqv 6,6,6\", operands);
output_asm_insn ("creqv 6,6,6", operands);
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
}"
return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1";
}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
......@@ -11121,7 +11065,6 @@
(match_operand:GPR 2 "reg_or_short_operand" "")]))
(use (match_operand 3 ""))]
""
"
{
/* Take care of the possibility that operands[2] might be negative but
this might be a logical operation. That insn doesn't exist. */
......@@ -11136,7 +11079,7 @@
rs6000_emit_cbranch (<MODE>mode, operands);
DONE;
}")
})
(define_expand "cbranch<mode>4"
[(use (match_operator 0 "comparison_operator"
......@@ -11144,11 +11087,10 @@
(match_operand:FP 2 "gpc_reg_operand" "")]))
(use (match_operand 3 ""))]
""
"
{
rs6000_emit_cbranch (<MODE>mode, operands);
DONE;
}")
})
(define_expand "cstore<mode>4_signed"
[(use (match_operator 1 "signed_comparison_operator"
......@@ -11795,7 +11737,6 @@
(const_int 0)])
(match_operand:SI 3 "const_int_operand" "n")))]
""
"*
{
int is_bit = ccr_bit (operands[1], 1);
int put_bit = 31 - (INTVAL (operands[3]) & 31);
......@@ -11809,8 +11750,8 @@
operands[4] = GEN_INT (count);
operands[5] = GEN_INT (put_bit);
return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
}"
return "mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5";
}
[(set (attr "type")
(cond [(match_test "TARGET_MFCRF")
(const_string "mfcrf")
......@@ -11830,7 +11771,6 @@
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))]
""
"*
{
int is_bit = ccr_bit (operands[1], 1);
int put_bit = 31 - (INTVAL (operands[3]) & 31);
......@@ -11838,7 +11778,7 @@
/* Force split for non-cc0 compare. */
if (which_alternative == 1)
return \"#\";
return "#";
if (is_bit >= put_bit)
count = is_bit - put_bit;
......@@ -11848,8 +11788,8 @@
operands[5] = GEN_INT (count);
operands[6] = GEN_INT (put_bit);
return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
}"
return "mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6";
}
[(set_attr "type" "shift")
(set_attr "dot" "yes")
(set_attr "length" "8,16")])
......@@ -12433,7 +12373,6 @@
""
[(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
(match_dup 5)))]
"
{
int positive_1, positive_2;
......@@ -12469,7 +12408,7 @@
{
operands[5] = const1_rtx;
}
}")
})
;; Unconditional branch and return.
......@@ -12894,7 +12833,6 @@
(match_operand 3 "immediate_operand" "n")]
UNSPEC_MOVESI_FROM_CR))])]
"TARGET_MFCRF"
"*
{
int mask = 0;
int i;
......@@ -12902,10 +12840,10 @@
{
mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
operands[4] = GEN_INT (mask);
output_asm_insn (\"mfcr %1,%4\", operands);
output_asm_insn ("mfcr %1,%4", operands);
}
return \"\";
}"
return "";
}
[(set_attr "type" "mfcrf")])
;; Don't include the volatile CRs since their values are not used wrt CR save
......@@ -13077,15 +13015,14 @@
(match_operand 3 "immediate_operand" "n")]
UNSPEC_MOVESI_TO_CR))])]
""
"*
{
int mask = 0;
int i;
for (i = 0; i < XVECLEN (operands[0], 0); i++)
mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
operands[4] = GEN_INT (mask);
return \"mtcrf %4,%2\";
}"
return "mtcrf %4,%2";
}
[(set_attr "type" "mtcr")])
(define_insn "*mtcrfsi"
......@@ -13275,14 +13212,13 @@
(define_expand "eh_return"
[(use (match_operand 0 "general_operand" ""))]
""
"
{
if (TARGET_32BIT)
emit_insn (gen_eh_set_lr_si (operands[0]));
else
emit_insn (gen_eh_set_lr_di (operands[0]));
DONE;
}")
})
; We can't expand this before we know where the link register is stored.
(define_insn "eh_set_lr_<mode>"
......@@ -13297,23 +13233,21 @@
(clobber (match_scratch 1 ""))]
"reload_completed"
[(const_int 0)]
"
{
rs6000_emit_eh_reg_restore (operands[0], operands[1]);
DONE;
}")
})
(define_insn "prefetch"
[(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
""
"*
{
if (GET_CODE (operands[0]) == REG)
return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
}"
return INTVAL (operands[1]) ? "dcbtst 0,%0" : "dcbt 0,%0";
return INTVAL (operands[1]) ? "dcbtst %a0" : "dcbt %a0";
}
[(set_attr "type" "load")])
;; Handle -fsplit-stack.
......
gcc/config/rs6000/vector.md
......@@ -181,7 +181,6 @@
[(set (match_operand:VEC_M 0 "vfloat_operand" "")
(match_operand:VEC_M 1 "memory_operand" ""))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
......@@ -198,13 +197,12 @@
emit_insn (gen_altivec_lvx_<mode>_1op (operands[0], operands[1]));
DONE;
}
}")
})
(define_expand "vector_altivec_store_<mode>"
[(set (match_operand:VEC_M 0 "memory_operand" "")
(match_operand:VEC_M 1 "vfloat_operand" ""))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
......@@ -221,7 +219,7 @@
emit_insn (gen_altivec_stvx_<mode>_1op (operands[1], operands[0]));
DONE;
}
}")
})
......@@ -272,27 +270,25 @@
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
DONE;
}
}")
})
(define_expand "abs<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
DONE;
}
}")
})
(define_expand "smin<mode>3"
[(set (match_operand:VEC_F 0 "register_operand" "")
......@@ -369,7 +365,6 @@
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
......@@ -377,7 +372,7 @@
operands[2]));
DONE;
}
}")
})
;; Vector comparisons
......@@ -390,14 +385,13 @@
(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
}")
})
(define_expand "vcond<mode><mode>"
[(set (match_operand:VEC_I 0 "vint_operand")
......@@ -408,14 +402,13 @@
(match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
(match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
}")
})
(define_expand "vcondv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
......@@ -427,14 +420,13 @@
(match_operand:V4SF 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
}")
})
(define_expand "vcondv4siv4sf"
[(set (match_operand:V4SI 0 "vint_operand" "")
......@@ -446,14 +438,13 @@
(match_operand:V4SI 2 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
}")
})
(define_expand "vcondv2dfv2di"
[(set (match_operand:V2DF 0 "vfloat_operand")
......@@ -500,14 +491,13 @@
(match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
(match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
}")
})
(define_expand "vconduv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
......@@ -519,14 +509,13 @@
(match_operand:V4SF 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
}")
})
(define_expand "vconduv2dfv2di"
[(set (match_operand:V2DF 0 "vfloat_operand")
......@@ -575,10 +564,9 @@
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
}")
})
(define_expand "vector_gtu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
......@@ -595,10 +583,9 @@
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
}")
})
(define_expand "vector_geu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
......@@ -615,10 +602,9 @@
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
}")
})
(define_expand "vector_ngtu<mode>"
[(set (match_operand:VEC_I 3 "vlogical_operand" "")
......@@ -627,10 +613,9 @@
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
}")
})
(define_insn_and_split "*vector_uneq<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
......@@ -669,11 +654,10 @@
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
"
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
}")
})
(define_insn_and_split "*vector_ordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
......@@ -691,11 +675,10 @@
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
"
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
}")
})
(define_insn_and_split "*vector_unordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
......@@ -713,11 +696,10 @@
(set (match_dup 0)
(and:VEC_F (not:VEC_F (match_dup 3))
(not:VEC_F (match_dup 4))))]
"
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
}")
})
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
;; which is in the reverse order that we want
......@@ -1030,53 +1012,49 @@
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
DONE;
}
}")
})
(define_expand "floatuns<VEC_int><mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
DONE;
}
}")
})
(define_expand "fix_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
DONE;
}
}")
})
(define_expand "fixuns_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
DONE;
}
}")
})
;; Vector initialization, set, extract
......@@ -1273,7 +1251,6 @@
(match_operand:VEC_L 1 "vlogical_operand" "")
(match_operand:QI 2 "reg_or_short_operand" "")]
"TARGET_ALTIVEC"
"
{
rtx bitshift = operands[2];
rtx shift;
......@@ -1315,7 +1292,7 @@
emit_insn (insn);
DONE;
}")
})
;; Expanders for rotate each element in a vector
(define_expand "vrotl<mode>3"
......
gcc/config/rs6000/vsx.md
......@@ -443,7 +443,6 @@
(vec_select:<MODE>
(match_dup 2)
(parallel [(const_int 1) (const_int 0)])))]
"
{
rtx mem = operands[1];
......@@ -475,7 +474,6 @@
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
"
[(set_attr "type" "vecload")
(set_attr "length" "8")])
......@@ -495,7 +493,6 @@
(match_dup 2)
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
"
{
rtx mem = operands[1];
......@@ -527,7 +524,6 @@
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
"
[(set_attr "type" "vecload")
(set_attr "length" "8")])
......@@ -551,7 +547,6 @@
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"
{
rtx mem = operands[1];
......@@ -583,7 +578,6 @@
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
"
[(set_attr "type" "vecload")
(set_attr "length" "8")])
......@@ -615,7 +609,6 @@
(const_int 2) (const_int 3)
(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
"
{
rtx mem = operands[1];
......@@ -647,7 +640,6 @@
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
"
[(set_attr "type" "vecload")
(set_attr "length" "8")])
......@@ -1037,7 +1029,6 @@
#"
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
[(const_int 0)]
"
{
rtx tmp = (can_create_pseudo_p ()
? gen_reg_rtx_and_attrs (operands[0])
......@@ -1046,7 +1037,6 @@
rs6000_emit_le_vsx_permute (operands[0], tmp, <MODE>mode);
DONE;
}
"
[(set_attr "type" "vecload,load")
(set_attr "length" "8,8")])
......@@ -1640,7 +1630,6 @@
"#"
"VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
......@@ -1668,7 +1657,7 @@
}
emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
DONE;
}"
}
[(set_attr "type" "mul")])
(define_insn "*vsx_div<mode>3"
......@@ -1690,7 +1679,6 @@
"#"
"VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
......@@ -1726,7 +1714,7 @@
}
emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
DONE;
}"
}
[(set_attr "type" "div")])
(define_insn_and_split "vsx_udiv_v2di"
......@@ -1738,7 +1726,6 @@
"#"
"VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
......@@ -1774,7 +1761,7 @@
}
emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
DONE;
}"
}
[(set_attr "type" "div")])
;; *tdiv* instruction returning the FG flag
......@@ -4328,7 +4315,6 @@
"#"
""
[(const_int 0)]
"
{
rtx tmp = (GET_CODE (operands[2]) == SCRATCH)
? gen_reg_rtx (V2DFmode)
......@@ -4336,7 +4322,7 @@
emit_insn (gen_vsx_xxsldwi_v2df (tmp, operands[1], operands[1], const2_rtx));
emit_insn (gen_<VEC_reduc_rtx>v2df3 (operands[0], tmp, operands[1]));
DONE;
}"
}
[(set_attr "length" "8")
(set_attr "type" "veccomplex")])
......@@ -4351,7 +4337,6 @@
"#"
""
[(const_int 0)]
"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
......@@ -4375,7 +4360,7 @@
emit_insn (gen_vsx_xxsldwi_v4sf (tmp4, tmp3, tmp3, GEN_INT (3)));
emit_insn (gen_<VEC_reduc_rtx>v4sf3 (op0, tmp4, tmp3));
DONE;
}"
}
[(set_attr "length" "16")
(set_attr "type" "veccomplex")])
......@@ -4400,7 +4385,6 @@
"#"
""
[(const_int 0)]
"
{
rtx hi = gen_highpart (DFmode, operands[1]);
rtx lo = (GET_CODE (operands[2]) == SCRATCH)
......@@ -4410,7 +4394,7 @@
emit_insn (gen_vsx_extract_v2df (lo, operands[1], const1_rtx));
emit_insn (gen_<VEC_reduc_rtx>df3 (operands[0], hi, lo));
DONE;
}"
}
[(set_attr "length" "8")
(set_attr "type" "veccomplex")])
......@@ -4428,7 +4412,6 @@
"#"
""
[(const_int 0)]
"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
......@@ -4455,7 +4438,7 @@
emit_insn (gen_<VEC_reduc_rtx>v4sf3 (tmp5, tmp4, tmp3));
emit_insn (gen_vsx_xscvspdp_scalar2 (op0, tmp5));
DONE;
}"
}
[(set_attr "length" "20")
(set_attr "type" "veccomplex")])
......
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