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Commit 4cc23303 by Srinath Parvathaneni Committed by Kyrylo Tkachov
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[ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads half word and word… 

[ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads half word and word or double word from memory.

This patch supports the following Remaining MVE ACLE load intrinsics which load an halfword,
word or double word from memory.

vldrdq_gather_base_s64, vldrdq_gather_base_u64, vldrdq_gather_base_z_s64,
vldrdq_gather_base_z_u64, vldrdq_gather_offset_s64, vldrdq_gather_offset_u64,
vldrdq_gather_offset_z_s64, vldrdq_gather_offset_z_u64, vldrdq_gather_shifted_offset_s64,
vldrdq_gather_shifted_offset_u64, vldrdq_gather_shifted_offset_z_s64,
vldrdq_gather_shifted_offset_z_u64, vldrhq_gather_offset_f16, vldrhq_gather_offset_z_f16,
vldrhq_gather_shifted_offset_f16, vldrhq_gather_shifted_offset_z_f16, vldrwq_gather_base_f32,
vldrwq_gather_base_z_f32, vldrwq_gather_offset_f32, vldrwq_gather_offset_s32,
vldrwq_gather_offset_u32, vldrwq_gather_offset_z_f32, vldrwq_gather_offset_z_s32,
vldrwq_gather_offset_z_u32, vldrwq_gather_shifted_offset_f32, vldrwq_gather_shifted_offset_s32,
vldrwq_gather_shifted_offset_u32, vldrwq_gather_shifted_offset_z_f32,
vldrwq_gather_shifted_offset_z_s32, vldrwq_gather_shifted_offset_z_u32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1]  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vld1q_s8): Define macro.
	(vld1q_s32): Likewise.
	(vld1q_s16): Likewise.
	(vld1q_u8): Likewise.
	(vld1q_u32): Likewise.
	(vld1q_u16): Likewise.
	(vldrhq_gather_offset_s32): Likewise.
	(vldrhq_gather_offset_s16): Likewise.
	(vldrhq_gather_offset_u32): Likewise.
	(vldrhq_gather_offset_u16): Likewise.
	(vldrhq_gather_offset_z_s32): Likewise.
	(vldrhq_gather_offset_z_s16): Likewise.
	(vldrhq_gather_offset_z_u32): Likewise.
	(vldrhq_gather_offset_z_u16): Likewise.
	(vldrhq_gather_shifted_offset_s32): Likewise.
	(vldrhq_gather_shifted_offset_s16): Likewise.
	(vldrhq_gather_shifted_offset_u32): Likewise.
	(vldrhq_gather_shifted_offset_u16): Likewise.
	(vldrhq_gather_shifted_offset_z_s32): Likewise.
	(vldrhq_gather_shifted_offset_z_s16): Likewise.
	(vldrhq_gather_shifted_offset_z_u32): Likewise.
	(vldrhq_gather_shifted_offset_z_u16): Likewise.
	(vldrhq_s32): Likewise.
	(vldrhq_s16): Likewise.
	(vldrhq_u32): Likewise.
	(vldrhq_u16): Likewise.
	(vldrhq_z_s32): Likewise.
	(vldrhq_z_s16): Likewise.
	(vldrhq_z_u32): Likewise.
	(vldrhq_z_u16): Likewise.
	(vldrwq_s32): Likewise.
	(vldrwq_u32): Likewise.
	(vldrwq_z_s32): Likewise.
	(vldrwq_z_u32): Likewise.
	(vld1q_f32): Likewise.
	(vld1q_f16): Likewise.
	(vldrhq_f16): Likewise.
	(vldrhq_z_f16): Likewise.
	(vldrwq_f32): Likewise.
	(vldrwq_z_f32): Likewise.
	(__arm_vld1q_s8): Define intrinsic.
	(__arm_vld1q_s32): Likewise.
	(__arm_vld1q_s16): Likewise.
	(__arm_vld1q_u8): Likewise.
	(__arm_vld1q_u32): Likewise.
	(__arm_vld1q_u16): Likewise.
	(__arm_vldrhq_gather_offset_s32): Likewise.
	(__arm_vldrhq_gather_offset_s16): Likewise.
	(__arm_vldrhq_gather_offset_u32): Likewise.
	(__arm_vldrhq_gather_offset_u16): Likewise.
	(__arm_vldrhq_gather_offset_z_s32): Likewise.
	(__arm_vldrhq_gather_offset_z_s16): Likewise.
	(__arm_vldrhq_gather_offset_z_u32): Likewise.
	(__arm_vldrhq_gather_offset_z_u16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_s32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_s16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_u32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_u16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
	(__arm_vldrhq_s32): Likewise.
	(__arm_vldrhq_s16): Likewise.
	(__arm_vldrhq_u32): Likewise.
	(__arm_vldrhq_u16): Likewise.
	(__arm_vldrhq_z_s32): Likewise.
	(__arm_vldrhq_z_s16): Likewise.
	(__arm_vldrhq_z_u32): Likewise.
	(__arm_vldrhq_z_u16): Likewise.
	(__arm_vldrwq_s32): Likewise.
	(__arm_vldrwq_u32): Likewise.
	(__arm_vldrwq_z_s32): Likewise.
	(__arm_vldrwq_z_u32): Likewise.
	(__arm_vld1q_f32): Likewise.
	(__arm_vld1q_f16): Likewise.
	(__arm_vldrwq_f32): Likewise.
	(__arm_vldrwq_z_f32): Likewise.
	(__arm_vldrhq_z_f16): Likewise.
	(__arm_vldrhq_f16): Likewise.
	(vld1q): Define polymorphic variant.
	(vldrhq_gather_offset): Likewise.
	(vldrhq_gather_offset_z): Likewise.
	(vldrhq_gather_shifted_offset): Likewise.
	(vldrhq_gather_shifted_offset_z): Likewise.
	* config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
	(LDRS): Likewise.
	(LDRU_Z): Likewise.
	(LDRS_Z): Likewise.
	(LDRGU_Z): Likewise.
	(LDRGU): Likewise.
	(LDRGS_Z): Likewise.
	(LDRGS): Likewise.
	* config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
	(V_sz_elem1): Likewise.
	(VLD1Q): Define iterator.
	(VLDRHGOQ): Likewise.
	(VLDRHGSOQ): Likewise.
	(VLDRHQ): Likewise.
	(VLDRWQ): Likewise.
	(mve_vldrhq_fv8hf): Define RTL pattern.
	(mve_vldrhq_gather_offset_<supf><mode>): Likewise.
	(mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
	(mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
	(mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
	(mve_vldrhq_<supf><mode>): Likewise.
	(mve_vldrhq_z_fv8hf): Likewise.
	(mve_vldrhq_z_<supf><mode>): Likewise.
	(mve_vldrwq_fv4sf): Likewise.
	(mve_vldrwq_<supf>v4si): Likewise.
	(mve_vldrwq_z_fv4sf): Likewise.
	(mve_vldrwq_z_<supf>v4si): Likewise.
	(mve_vld1q_f<mode>): Define RTL expand pattern.
	(mve_vld1q_<supf><mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
parent bf1e3d5a
Showing with 776 additions and 0 deletions
gcc/ChangeLog
...@@ -121,6 +121,125 @@ ...@@ -121,6 +121,125 @@
Mihail Ionescu <mihail.ionescu@arm.com> Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vld1q_s8): Define macro.
(vld1q_s32): Likewise.
(vld1q_s16): Likewise.
(vld1q_u8): Likewise.
(vld1q_u32): Likewise.
(vld1q_u16): Likewise.
(vldrhq_gather_offset_s32): Likewise.
(vldrhq_gather_offset_s16): Likewise.
(vldrhq_gather_offset_u32): Likewise.
(vldrhq_gather_offset_u16): Likewise.
(vldrhq_gather_offset_z_s32): Likewise.
(vldrhq_gather_offset_z_s16): Likewise.
(vldrhq_gather_offset_z_u32): Likewise.
(vldrhq_gather_offset_z_u16): Likewise.
(vldrhq_gather_shifted_offset_s32): Likewise.
(vldrhq_gather_shifted_offset_s16): Likewise.
(vldrhq_gather_shifted_offset_u32): Likewise.
(vldrhq_gather_shifted_offset_u16): Likewise.
(vldrhq_gather_shifted_offset_z_s32): Likewise.
(vldrhq_gather_shifted_offset_z_s16): Likewise.
(vldrhq_gather_shifted_offset_z_u32): Likewise.
(vldrhq_gather_shifted_offset_z_u16): Likewise.
(vldrhq_s32): Likewise.
(vldrhq_s16): Likewise.
(vldrhq_u32): Likewise.
(vldrhq_u16): Likewise.
(vldrhq_z_s32): Likewise.
(vldrhq_z_s16): Likewise.
(vldrhq_z_u32): Likewise.
(vldrhq_z_u16): Likewise.
(vldrwq_s32): Likewise.
(vldrwq_u32): Likewise.
(vldrwq_z_s32): Likewise.
(vldrwq_z_u32): Likewise.
(vld1q_f32): Likewise.
(vld1q_f16): Likewise.
(vldrhq_f16): Likewise.
(vldrhq_z_f16): Likewise.
(vldrwq_f32): Likewise.
(vldrwq_z_f32): Likewise.
(__arm_vld1q_s8): Define intrinsic.
(__arm_vld1q_s32): Likewise.
(__arm_vld1q_s16): Likewise.
(__arm_vld1q_u8): Likewise.
(__arm_vld1q_u32): Likewise.
(__arm_vld1q_u16): Likewise.
(__arm_vldrhq_gather_offset_s32): Likewise.
(__arm_vldrhq_gather_offset_s16): Likewise.
(__arm_vldrhq_gather_offset_u32): Likewise.
(__arm_vldrhq_gather_offset_u16): Likewise.
(__arm_vldrhq_gather_offset_z_s32): Likewise.
(__arm_vldrhq_gather_offset_z_s16): Likewise.
(__arm_vldrhq_gather_offset_z_u32): Likewise.
(__arm_vldrhq_gather_offset_z_u16): Likewise.
(__arm_vldrhq_gather_shifted_offset_s32): Likewise.
(__arm_vldrhq_gather_shifted_offset_s16): Likewise.
(__arm_vldrhq_gather_shifted_offset_u32): Likewise.
(__arm_vldrhq_gather_shifted_offset_u16): Likewise.
(__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
(__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
(__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
(__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
(__arm_vldrhq_s32): Likewise.
(__arm_vldrhq_s16): Likewise.
(__arm_vldrhq_u32): Likewise.
(__arm_vldrhq_u16): Likewise.
(__arm_vldrhq_z_s32): Likewise.
(__arm_vldrhq_z_s16): Likewise.
(__arm_vldrhq_z_u32): Likewise.
(__arm_vldrhq_z_u16): Likewise.
(__arm_vldrwq_s32): Likewise.
(__arm_vldrwq_u32): Likewise.
(__arm_vldrwq_z_s32): Likewise.
(__arm_vldrwq_z_u32): Likewise.
(__arm_vld1q_f32): Likewise.
(__arm_vld1q_f16): Likewise.
(__arm_vldrwq_f32): Likewise.
(__arm_vldrwq_z_f32): Likewise.
(__arm_vldrhq_z_f16): Likewise.
(__arm_vldrhq_f16): Likewise.
(vld1q): Define polymorphic variant.
(vldrhq_gather_offset): Likewise.
(vldrhq_gather_offset_z): Likewise.
(vldrhq_gather_shifted_offset): Likewise.
(vldrhq_gather_shifted_offset_z): Likewise.
* config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
(LDRS): Likewise.
(LDRU_Z): Likewise.
(LDRS_Z): Likewise.
(LDRGU_Z): Likewise.
(LDRGU): Likewise.
(LDRGS_Z): Likewise.
(LDRGS): Likewise.
* config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
(V_sz_elem1): Likewise.
(VLD1Q): Define iterator.
(VLDRHGOQ): Likewise.
(VLDRHGSOQ): Likewise.
(VLDRHQ): Likewise.
(VLDRWQ): Likewise.
(mve_vldrhq_fv8hf): Define RTL pattern.
(mve_vldrhq_gather_offset_<supf><mode>): Likewise.
(mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
(mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
(mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
(mve_vldrhq_<supf><mode>): Likewise.
(mve_vldrhq_z_fv8hf): Likewise.
(mve_vldrhq_z_<supf><mode>): Likewise.
(mve_vldrwq_fv4sf): Likewise.
(mve_vldrwq_<supf>v4si): Likewise.
(mve_vldrwq_z_fv4sf): Likewise.
(mve_vldrwq_z_<supf>v4si): Likewise.
(mve_vld1q_f<mode>): Define RTL expand pattern.
(mve_vld1q_<supf><mode>): Likewise.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
qualifier. qualifier.
(LDRGBU_Z_QUALIFIERS): Likewise. (LDRGBU_Z_QUALIFIERS): Likewise.
......
gcc/config/arm/arm_mve_builtins.def
...@@ -732,3 +732,33 @@ VAR1 (LDRU, vldrwq_u, v4si) ...@@ -732,3 +732,33 @@ VAR1 (LDRU, vldrwq_u, v4si)
VAR1 (LDRS_Z, vldrwq_z_f, v4sf) VAR1 (LDRS_Z, vldrwq_z_f, v4sf)
VAR1 (LDRS_Z, vldrwq_z_s, v4si) VAR1 (LDRS_Z, vldrwq_z_s, v4si)
VAR1 (LDRU_Z, vldrwq_z_u, v4si) VAR1 (LDRU_Z, vldrwq_z_u, v4si)
VAR1 (LDRGBS, vldrdq_gather_base_s, v2di)
VAR1 (LDRGBS, vldrwq_gather_base_f, v4sf)
VAR1 (LDRGBS_Z, vldrdq_gather_base_z_s, v2di)
VAR1 (LDRGBS_Z, vldrwq_gather_base_z_f, v4sf)
VAR1 (LDRGBU, vldrdq_gather_base_u, v2di)
VAR1 (LDRGBU_Z, vldrdq_gather_base_z_u, v2di)
VAR1 (LDRGS, vldrdq_gather_offset_s, v2di)
VAR1 (LDRGS, vldrdq_gather_shifted_offset_s, v2di)
VAR1 (LDRGS, vldrhq_gather_offset_f, v8hf)
VAR1 (LDRGS, vldrhq_gather_shifted_offset_f, v8hf)
VAR1 (LDRGS, vldrwq_gather_offset_f, v4sf)
VAR1 (LDRGS, vldrwq_gather_offset_s, v4si)
VAR1 (LDRGS, vldrwq_gather_shifted_offset_f, v4sf)
VAR1 (LDRGS, vldrwq_gather_shifted_offset_s, v4si)
VAR1 (LDRGS_Z, vldrdq_gather_offset_z_s, v2di)
VAR1 (LDRGS_Z, vldrdq_gather_shifted_offset_z_s, v2di)
VAR1 (LDRGS_Z, vldrhq_gather_offset_z_f, v8hf)
VAR1 (LDRGS_Z, vldrhq_gather_shifted_offset_z_f, v8hf)
VAR1 (LDRGS_Z, vldrwq_gather_offset_z_f, v4sf)
VAR1 (LDRGS_Z, vldrwq_gather_offset_z_s, v4si)
VAR1 (LDRGS_Z, vldrwq_gather_shifted_offset_z_f, v4sf)
VAR1 (LDRGS_Z, vldrwq_gather_shifted_offset_z_s, v4si)
VAR1 (LDRGU, vldrdq_gather_offset_u, v2di)
VAR1 (LDRGU, vldrdq_gather_shifted_offset_u, v2di)
VAR1 (LDRGU, vldrwq_gather_offset_u, v4si)
VAR1 (LDRGU, vldrwq_gather_shifted_offset_u, v4si)
VAR1 (LDRGU_Z, vldrdq_gather_offset_z_u, v2di)
VAR1 (LDRGU_Z, vldrdq_gather_shifted_offset_z_u, v2di)
VAR1 (LDRGU_Z, vldrwq_gather_offset_z_u, v4si)
VAR1 (LDRGU_Z, vldrwq_gather_shifted_offset_z_u, v4si)
gcc/testsuite/ChangeLog
...@@ -47,6 +47,51 @@ ...@@ -47,6 +47,51 @@
Mihail Ionescu <mihail.ionescu@arm.com> Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise.
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int64x2_t
foo (uint64x2_t addr)
{
return vldrdq_gather_base_s64 (addr, 8);
}
/* { dg-final { scan-assembler "vldrd.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint64x2_t
foo (uint64x2_t addr)
{
return vldrdq_gather_base_u64 (addr, 8);
}
/* { dg-final { scan-assembler "vldrd.64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int64x2_t
foo (uint64x2_t addr, mve_pred16_t p)
{
return vldrdq_gather_base_z_s64 (addr, 8, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint64x2_t
foo (uint64x2_t addr, mve_pred16_t p)
{
return vldrdq_gather_base_z_u64 (addr, 8, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int64x2_t
foo (int64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_offset_s64 (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
int64x2_t
foo1 (int64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint64x2_t
foo (uint64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_offset_u64 (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
uint64x2_t
foo1 (uint64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int64x2_t
foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z_s64 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
int64x2_t
foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint64x2_t
foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z_u64 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
uint64x2_t
foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int64x2_t
foo (int64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset_s64 (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
int64x2_t
foo1 (int64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint64x2_t
foo (uint64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset_u64 (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
uint64x2_t
foo1 (uint64_t const * base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrd.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int64x2_t
foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z_s64 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
int64x2_t
foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint64x2_t
foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z_u64 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
uint64x2_t
foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrdt.u64" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float16x8_t
foo (float16_t const * base, uint16x8_t offset)
{
return vldrhq_gather_offset_f16 (base, offset);
}
/* { dg-final { scan-assembler "vldrh.f16" } } */
float16x8_t
foo1 (float16_t const * base, uint16x8_t offset)
{
return vldrhq_gather_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrh.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float16x8_t
foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z_f16 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrht.f16" } } */
float16x8_t
foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrht.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float16x8_t
foo (float16_t const * base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset_f16 (base, offset);
}
/* { dg-final { scan-assembler "vldrh.f16" } } */
float16x8_t
foo1 (float16_t const * base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrh.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float16x8_t
foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z_f16 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrht.f16" } } */
float16x8_t
foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrht.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float32x4_t
foo (uint32x4_t addr)
{
return vldrwq_gather_base_f32 (addr, 4);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float32x4_t
foo (uint32x4_t addr, mve_pred16_t p)
{
return vldrwq_gather_base_z_f32 (addr, 4, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float32x4_t
foo (float32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_offset_f32 (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
float32x4_t
foo1 (float32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int32x4_t
foo (int32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_offset_s32 (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
int32x4_t
foo1 (int32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint32x4_t
foo (uint32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_offset_u32 (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
uint32x4_t
foo1 (uint32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float32x4_t
foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z_f32 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
float32x4_t
foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int32x4_t
foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z_s32 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
int32x4_t
foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint32x4_t
foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z_u32 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
uint32x4_t
foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float32x4_t
foo (float32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset_f32 (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
float32x4_t
foo1 (float32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int32x4_t
foo (int32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset_s32 (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
int32x4_t
foo1 (int32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint32x4_t
foo (uint32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset_u32 (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
uint32x4_t
foo1 (uint32_t const * base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset (base, offset);
}
/* { dg-final { scan-assembler "vldrw.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
float32x4_t
foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z_f32 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
float32x4_t
foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
int32x4_t
foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z_s32 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
int32x4_t
foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
#include "arm_mve.h"
uint32x4_t
foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z_u32 (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
uint32x4_t
foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z (base, offset, p);
}
/* { dg-final { scan-assembler "vldrwt.u32" } } */
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