[aarch64] Correct architecture for tsv110.

For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but
some mandatory features are not implemented.

2018-12-19  Shaokun Zhang  <zhangshaokun@hisilicon.com>

	* config/aarch64/aarch64-cores.def (tsv110): Fix architecture.  This
	part is really Armv8.2 with some permitted Armv8.4 extensions.

From-SVN: r267255

gcc/ChangeLog

+2018-12-19  Shaokun Zhang  <zhangshaokun@hisilicon.com>
+
+	* config/aarch64/aarch64-cores.def (tsv110): Fix architecture.  This
+	part is really Armv8.2 with some permitted Armv8.4 extensions.
+
 2018-12-19  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/88541

gcc/config/aarch64/aarch64-cores.def

@@ -96,10 +96,10 @@ AARCH64_CORE("cortex-a75",  cortexa75, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2
 AARCH64_CORE("cortex-a76",  cortexa76, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1)
 AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1)
 
-/* ARMv8.4-A Architecture Processors.  */
-
 /* HiSilicon ('H') cores. */
-AARCH64_CORE("tsv110",     tsv110,    cortexa57,    8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
+AARCH64_CORE("tsv110",  tsv110, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
+
+/* ARMv8.4-A Architecture Processors.  */
 
 /* Qualcomm ('Q') cores. */
 AARCH64_CORE("saphira",     saphira,    saphira,    8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   0x51, 0xC01, -1)