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riscv-gcc-1
Commit 54ae50ac by Jakub Jelinek Committed by Jakub Jelinek
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re PR rtl-optimization/89865 (FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45) 

	PR rtl-optimization/89865
	* gcc.target/i386/pr49095.c: Include in scan-assembler-times patterns
	the first argument register, so that occassional spills/fills are
	ignored.

From-SVN: r270025
parent 2b53407e
Showing with 7 additions and 2 deletions
gcc/testsuite/ChangeLog
2019-03-29 Jakub Jelinek <jakub@redhat.com> 2019-03-29 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/89865
* gcc.target/i386/pr49095.c: Include in scan-assembler-times patterns
the first argument register, so that occassional spills/fills are
ignored.
PR sanitizer/89869 PR sanitizer/89869
* g++.dg/ubsan/vptr-14.C: New test. * g++.dg/ubsan/vptr-14.C: New test.
......
gcc/testsuite/gcc.target/i386/pr49095.c
...@@ -73,5 +73,5 @@ G (long) ...@@ -73,5 +73,5 @@ G (long)
/* { dg-final { scan-assembler-not "test\[lq\]" } } */ /* { dg-final { scan-assembler-not "test\[lq\]" } } */
/* The {f,h}{char,short,int,long}xor functions aren't optimized into /* The {f,h}{char,short,int,long}xor functions aren't optimized into
a RMW instruction, so need load, modify and store. FIXME eventually. */ a RMW instruction, so need load, modify and store. FIXME eventually. */
/* { dg-final { scan-assembler-times "\\), %" 57 { target { ia32 } } } } */ /* { dg-final { scan-assembler-times "\\(%eax\\), %" 12 { target { ia32 } } } } */
/* { dg-final { scan-assembler-times "\\), %" 45 { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "\\(%\[re\]di\\), %" 8 { target { ! ia32 } } } } */
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