Commit 4272cd33 by Kyrylo Tkachov Committed by Kyrylo Tkachov

[ARM] Use proper output modifier for DImode register in store exclusive patterns

	* config/arm/sync.md (arm_store_exclusive<mode>):
	Use 'H' output modifier on operands[2] rather than creating a new
	entry in out-of-bounds memory of the operands array.
	(arm_store_release_exclusivedi): Likewise.

From-SVN: r236984
parent 39fa4aec
2016-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 2016-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/sync.md (arm_store_exclusive<mode>):
Use 'H' output modifier on operands[2] rather than creating a new
entry in out-of-bounds memory of the operands array.
(arm_store_release_exclusivedi): Likewise.
2016-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_fusion_enabled_p): New function. * config/arm/arm.c (arm_fusion_enabled_p): New function.
* config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype. * config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype.
* config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY): * config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY):
......
...@@ -452,14 +452,13 @@ ...@@ -452,14 +452,13 @@
{ {
if (<MODE>mode == DImode) if (<MODE>mode == DImode)
{ {
rtx value = operands[2];
/* The restrictions on target registers in ARM mode are that the two /* The restrictions on target registers in ARM mode are that the two
registers are consecutive and the first one is even; Thumb is registers are consecutive and the first one is even; Thumb is
actually more flexible, but DI should give us this anyway. actually more flexible, but DI should give us this anyway.
Note that the 1st register always gets the lowest word in memory. */ Note that the 1st register always gets the
gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); lowest word in memory. */
operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
return "strexd%?\t%0, %2, %3, %C1"; return "strexd%?\t%0, %2, %H2, %C1";
} }
return "strex<sync_sfx>%?\t%0, %2, %C1"; return "strex<sync_sfx>%?\t%0, %2, %C1";
} }
...@@ -475,11 +474,9 @@ ...@@ -475,11 +474,9 @@
VUNSPEC_SLX))] VUNSPEC_SLX))]
"TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
{ {
rtx value = operands[2];
/* See comment in arm_store_exclusive<mode> above. */ /* See comment in arm_store_exclusive<mode> above. */
gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); return "stlexd%?\t%0, %2, %H2, %C1";
return "stlexd%?\t%0, %2, %3, %C1";
} }
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]) (set_attr "predicable_short_it" "no")])
......
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