Commit 39fa4aec by Kyrylo Tkachov Committed by Kyrylo Tkachov

[ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC

	* config/arm/arm.c (arm_fusion_enabled_p): New function.
	* config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype.
	* config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY):
	Add "=w,0" alternative.  Enable it when AES/AESMC fusion is enabled.

From-SVN: r236982
parent a0dfeef5
2016-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_fusion_enabled_p): New function.
* config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype.
* config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY):
Add "=w,0" alternative. Enable it when AES/AESMC fusion is enabled.
2016-06-01 Eric Botcazou <ebotcazou@adacore.com> 2016-06-01 Eric Botcazou <ebotcazou@adacore.com>
* tree-vect-loop.c (vect_determine_vectorization_factor): Also take * tree-vect-loop.c (vect_determine_vectorization_factor): Also take
......
...@@ -321,6 +321,7 @@ extern int vfp3_const_double_for_bits (rtx); ...@@ -321,6 +321,7 @@ extern int vfp3_const_double_for_bits (rtx);
extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx, extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
rtx); rtx);
extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
extern bool arm_valid_symbolic_address_p (rtx); extern bool arm_valid_symbolic_address_p (rtx);
extern bool arm_validize_comparison (rtx *, rtx *, rtx *); extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
#endif /* RTX_CODE */ #endif /* RTX_CODE */
......
...@@ -29858,6 +29858,13 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr) ...@@ -29858,6 +29858,13 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
return false; return false;
} }
/* Return true iff the instruction fusion described by OP is enabled. */
bool
arm_fusion_enabled_p (tune_params::fuse_ops op)
{
return current_tune->fusible_ops & op;
}
/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
static unsigned HOST_WIDE_INT static unsigned HOST_WIDE_INT
......
...@@ -18,14 +18,27 @@ ...@@ -18,14 +18,27 @@
;; along with GCC; see the file COPYING3. If not see ;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. ;; <http://www.gnu.org/licenses/>.
;; When AES/AESMC fusion is enabled we want the register allocation to
;; look like:
;; AESE Vn, _
;; AESMC Vn, Vn
;; So prefer to tie operand 1 to operand 0 when fusing.
(define_insn "crypto_<crypto_pattern>" (define_insn "crypto_<crypto_pattern>"
[(set (match_operand:<crypto_mode> 0 "register_operand" "=w") [(set (match_operand:<crypto_mode> 0 "register_operand" "=w,w")
(unspec:<crypto_mode> [(match_operand:<crypto_mode> 1 (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1
"register_operand" "w")] "register_operand" "0,w")]
CRYPTO_UNARY))] CRYPTO_UNARY))]
"TARGET_CRYPTO" "TARGET_CRYPTO"
"<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1" "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1"
[(set_attr "type" "<crypto_type>")] [(set_attr "type" "<crypto_type>")
(set_attr_alternative "enabled"
[(if_then_else (match_test
"arm_fusion_enabled_p (tune_params::FUSE_AES_AESMC)")
(const_string "yes" )
(const_string "no"))
(const_string "yes")])]
) )
(define_insn "crypto_<crypto_pattern>" (define_insn "crypto_<crypto_pattern>"
......
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