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Commit 3965b35f by Stafford Horne Committed by Stafford Horne
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or1k: gcc: initial support for openrisc 

2018-11-09  Stafford Horne  <shorne@gmail.com>
	    Richard Henderson  <rth@twiddle.net>
	    Joel Sherrill  <joel@rtems.org>

	* common/config/or1k/or1k-common.c: New file.
	* config/or1k/*: New.
	* config.gcc (or1k*-*-*): New.
	* configure.ac (or1k*-*-*): New test for openrisc tls.
	* configure: Regenerated.
	* doc/install.texi: Document OpenRISC triplets.
	* doc/invoke.texi: Document OpenRISC arguments.
	* doc/md.texi: Document OpenRISC.


Co-Authored-By: Joel Sherrill <joel@rtems.org>
Co-Authored-By: Richard Henderson <rth@twiddle.net>

From-SVN: r265963
parent 1d6ff150
Showing with 654 additions and 0 deletions
gcc/ChangeLog
2018-11-09 Stafford Horne <shorne@gmail.com>
Richard Henderson <rth@twiddle.net>
Joel Sherrill <joel@rtems.org>
* common/config/or1k/or1k-common.c: New file.
* config/or1k/*: New.
* config.gcc (or1k*-*-*): New.
* configure.ac (or1k*-*-*): New test for openrisc tls.
* configure: Regenerated.
* doc/install.texi: Document OpenRISC triplets.
* doc/invoke.texi: Document OpenRISC arguments.
* doc/md.texi: Document OpenRISC.
2018-11-09 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm-cpus.in (arm7tdmi): Add an alias for arm7tdmi-s.
gcc/common/config/or1k/or1k-common.c 0 → 100644
/* Common hooks for OpenRISC
Copyright (C) 2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "diagnostic-core.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
static const struct default_options or1k_option_optimization_table[] =
{
/* Enable section anchors by default at -O1 or higher. */
{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE or1k_option_optimization_table
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
gcc/config.gcc
......@@ -484,6 +484,9 @@ nios2-*-*)
nvptx-*-*)
cpu_type=nvptx
;;
or1k*-*-*)
cpu_type=or1k
;;
powerpc*-*-*spe*)
cpu_type=powerpcspe
extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
......@@ -2490,6 +2493,48 @@ nvptx-*)
tm_file="${tm_file} nvptx/offload.h"
fi
;;
or1k*-*-*)
tm_file="elfos.h ${tm_file}"
tmake_file="${tmake_file} or1k/t-or1k"
# Force .init_array support. The configure script cannot always
# automatically detect that GAS supports it, yet we require it.
gcc_cv_initfini_array=yes
# Handle --with-multilib-list=...
or1k_multilibs="${with_multilib_list}"
if test "$or1k_multilibs" = "default"; then
or1k_multilibs="mcmov,msoft-mul,msoft-div"
fi
or1k_multilibs=`echo $or1k_multilibs | sed -e 's/,/ /g'`
for or1k_multilib in ${or1k_multilibs}; do
case ${or1k_multilib} in
mcmov | msext | msfimm | \
mhard-div | mhard-mul | \
msoft-div | msoft-mul )
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}"
;;
*)
echo "--with-multilib-list=${with_multilib_list} not supported."
exit 1
esac
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
case ${target} in
or1k*-*-linux*)
tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h"
tm_file="${tm_file} or1k/linux.h"
;;
or1k*-*-elf*)
tm_file="${tm_file} newlib-stdint.h or1k/elf.h"
extra_options="${extra_options} or1k/elf.opt"
;;
or1k*-*-rtems*)
tm_file="${tm_file} newlib-stdint.h or1k/rtems.h rtems.h"
tmake_file="${tmake_file} or1k/t-rtems"
;;
esac
;;
pdp11-*-*)
tm_file="${tm_file} newlib-stdint.h"
use_gcc_stdint=wrap
......
gcc/config/or1k/constraints.md 0 → 100644
;; Constraint definitions for OpenRISC
;; Copyright (C) 2018 Free Software Foundation, Inc.
;; Contributed by Stafford Horne
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; -------------------------------------------------------------------------
;; Constraints
;; -------------------------------------------------------------------------
; We use:
; c - sibcall registers
; I - constant signed 16-bit
; K - constant unsigned 16-bit
; M - constant signed 16-bit shifted left 16-bits (l.movhi)
; O - constant zero
(define_register_constraint "c" "SIBCALL_REGS"
"Registers which can hold a sibling call address")
;; Immediates
(define_constraint "I"
"A signed 16-bit immediate in the range -32768 to 32767."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, -32768, 32767)")))
(define_constraint "K"
"An unsigned 16-bit immediate in the range 0 to 0xffff."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 0, 65535)")))
(define_constraint "M"
"A shifted signed 16-bit constant suitable for l.movhi."
(and (match_code "const_int")
(match_test "(ival & 0xffff) == 0
&& (ival >> 31 == -1 || ival >> 31 == 0)")))
(define_constraint "O"
"The constant zero"
(and (match_code "const_int")
(match_test "ival == 0")))
gcc/config/or1k/elf.h 0 → 100644
/* Target Newlib Definitions for OpenRISC.
Copyright (C) 2018 Free Software Foundation, Inc.
Contributed by Stafford Horne.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_OR1K_ELF_H
#define GCC_OR1K_ELF_H
#undef LIB_SPEC
#define LIB_SPEC "--start-group -lc -lor1k " \
"%{mboard=*:-lboard-%*; :-lboard-or1ksim} --end-group"
#undef LINK_SPEC
#define LINK_SPEC "%{h*} \
%{static:-Bstatic} \
%{shared:-shared} \
%{symbolic:-Bsymbolic} \
%{!static:%{rdynamic:-export-dynamic}} \
--entry=0x100"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s"
#endif /* GCC_OR1K_ELF_H */
gcc/config/or1k/elf.opt 0 → 100644
; OpenRISC command line options for newlib binaries
; Copyright (C) 2010-2018 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
; See the GCC internals manual (options.texi) for a description of
; this file's format.
; Please try to keep this file in ASCII collating order.
mboard=
Target RejectNegative Joined
Configure board specific runtime.
mnewlib
Target RejectNegative
For compatibility, it's always newlib for elf now.
gcc/config/or1k/linux.h 0 → 100644
/* Linux Definitions for OpenRISC.
Copyright (C) 2018 Free Software Foundation, Inc.
Contributed by Stafford Horne.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_OR1K_LINUX_H
#define GCC_OR1K_LINUX_H
/* elfos.h should have already been included. Now just override
any conflicting definitions and add any extras. */
#define TARGET_OS_CPP_BUILTINS() \
GNU_USER_TARGET_OS_CPP_BUILTINS ()
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-or1k.so.1"
#undef MUSL_DYNAMIC_LINKER
#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-or1k.so.1"
#undef LINK_SPEC
#define LINK_SPEC "%{h*} \
%{static:-Bstatic} \
%{shared:-shared} \
%{symbolic:-Bsymbolic} \
%{!static:%{!static-pie: \
%{rdynamic:-export-dynamic} \
%{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \
%{static-pie:-Bstatic -pie --no-dynamic-linker -z text}"
#endif /* GCC_OR1K_LINUX_H */
gcc/config/or1k/or1k-protos.h 0 → 100644
/* Prototypes for OpenRISC functions used in the md file & elsewhere.
Copyright (C) 2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
extern HOST_WIDE_INT or1k_initial_elimination_offset (int, int);
extern void or1k_expand_prologue (void);
extern void or1k_expand_epilogue (void);
extern void or1k_expand_eh_return (rtx);
extern rtx or1k_initial_frame_addr (void);
extern rtx or1k_dynamic_chain_addr (rtx);
extern rtx or1k_return_addr (int, rtx);
extern void or1k_expand_move (machine_mode, rtx, rtx);
extern void or1k_expand_compare (rtx *);
extern void or1k_expand_call (rtx, rtx, rtx, bool);
#ifdef RTX_CODE
void or1k_expand_atomic_compare_and_swap (rtx operands[]);
void or1k_expand_atomic_compare_and_swap_qihi (rtx operands[]);
void or1k_expand_atomic_exchange (rtx operands[]);
void or1k_expand_atomic_exchange_qihi (rtx operands[]);
void or1k_expand_atomic_op (rtx_code, rtx, rtx, rtx, rtx);
void or1k_expand_atomic_op_qihi (rtx_code, rtx, rtx, rtx, rtx);
#endif
gcc/config/or1k/or1k.opt 0 → 100644
; OpenRISC command line options
; Copyright (C) 2010-2018 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
; See the GCC internals manual (options.texi) for a description of
; this file's format.
; Please try to keep this file in ASCII collating order.
mhard-div
Target RejectNegative InverseMask(SOFT_DIV)
Use hardware divide instructions, use -msoft-div for emulation.
mhard-mul
Target RejectNegative InverseMask(SOFT_MUL).
Use hardware multiply instructions, use -msoft-mul for emulation.
mcmov
Target RejectNegative Mask(CMOV)
Allows generation of binaries which use the l.cmov instruction. If your target
does not support this the compiler will generate the equivalent using set and
branch.
mror
Target RejectNegative Mask(ROR)
Allows generation of binaries which use the l.rori instructions.
msext
Target RejectNegative Mask(SEXT)
Allows generation of binaries which use sign-extension instructions. If your
target does not support this the compiler will use memory loads to perform sign
extension.
msfimm
Target RejectNegative Mask(SFIMM)
Allows generation of binaries which use l.sf*i instructions. If your target
does not support this the compiler will generate instructions to store the
immediate to a register first.
mshftimm
Target RejectNegative Mask(SHFTIMM)
Allows generation of binaries which support shifts and rotate instructions
supporting immediate arguments, for example l.rori.
msoft-div
Target RejectNegative Mask(SOFT_DIV)
Use divide emulation.
msoft-mul
Target RejectNegative Mask(SOFT_MUL).
Use multiply emulation.
gcc/config/or1k/predicates.md 0 → 100644
;; Predicate definitions for OpenRISC
;; Copyright (C) 2018 Free Software Foundation, Inc.
;; Contributed by Stafford Horne
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; -------------------------------------------------------------------------
;; Predicates
;; -------------------------------------------------------------------------
(define_predicate "input_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "memory_operand")
(and (match_code "const_int")
(match_test "satisfies_constraint_I (op)
|| satisfies_constraint_K (op)
|| satisfies_constraint_M (op)"))))
(define_predicate "const0_operand"
(and (match_code "const_int,const_wide_int,const_double,const_vector")
(match_test "op == CONST0_RTX (mode)")))
(define_predicate "reg_or_0_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "const0_operand")))
(define_predicate "reg_or_u6_operand"
(if_then_else (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x3f")
(match_operand 0 "register_operand")))
(define_predicate "reg_or_u16_operand"
(if_then_else (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0xffff")
(match_operand 0 "register_operand")))
(define_predicate "reg_or_s16_operand"
(if_then_else (match_code "const_int")
(match_test "INTVAL (op) >= -32768 && INTVAL (op) <= 32767")
(match_operand 0 "register_operand")))
(define_predicate "call_insn_operand"
(ior (match_code "symbol_ref")
(match_operand 0 "register_operand")))
(define_predicate "high_operand"
(match_code "symbol_ref,label_ref,const,unspec"))
;; Return true for relocations that must use MOVHI+ADDI
(define_predicate "losum_add_operand"
(match_code "symbol_ref,label_ref,const,unspec"))
;; Return true for relocations that must use MOVHI+ORI
(define_predicate "losum_ior_operand"
(and (match_code "unspec")
(match_test "XINT(op, 1) == UNSPEC_TLSGD")))
;; Return true for a "virtual" or "soft" register that will be
;; adjusted to a "soft" or "hard" register during elimination.
(define_predicate "virtual_frame_reg_operand"
(match_code "reg")
{
unsigned regno = REGNO (op);
return (regno != STACK_POINTER_REGNUM
&& regno != HARD_FRAME_POINTER_REGNUM
&& REGNO_PTR_FRAME_P (regno));
})
(define_predicate "equality_comparison_operator"
(match_code "ne,eq"))
gcc/config/or1k/rtems.h 0 → 100644
/* Target Newlib Definitions for OpenRISC.
Copyright (C) 2018 Free Software Foundation, Inc.
Contributed by Joel Sherrill (joel.sherrill@OARcorp.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Target OS builtins. */
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("__rtems__"); \
builtin_define ("__USE_INIT_FINI__"); \
builtin_assert ("system=rtems"); \
} \
while (0)
gcc/config/or1k/t-or1k 0 → 100644
# Target Makefile Fragment for OpenRISC
# Copyright (C) 2018 Free Software Foundation, Inc.
# Contributed by Stafford Horne.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published
# by the Free Software Foundation; either version 3, or (at your
# option) any later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
comma=,
MULTILIB_OPTIONS = $(subst $(comma), ,$(TM_MULTILIB_CONFIG))
gcc/config/or1k/t-rtems 0 → 100644
# RTEMS OR1K multilibs
# No custom multilibs defined
gcc/configure
......@@ -24391,6 +24391,18 @@ foo: .long 25
tls_first_minor=20
tls_as_opt='--fatal-warnings'
;;
or1k*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25
.text
l.movhi r3, tpoffha(foo)
l.add r3, r3, r10
l.lwz r4, tpofflo(foo)(r3)'
tls_first_major=2
tls_first_minor=30
tls_as_opt=--fatal-warnings
;;
powerpc-ibm-aix*)
conftest_s='
.extern __get_tpointer
......
gcc/configure.ac
......@@ -3473,6 +3473,18 @@ foo: .long 25
tls_first_minor=20
tls_as_opt='--fatal-warnings'
;;
or1k*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25
.text
l.movhi r3, tpoffha(foo)
l.add r3, r3, r10
l.lwz r4, tpofflo(foo)(r3)'
tls_first_major=2
tls_first_minor=30
tls_as_opt=--fatal-warnings
;;
powerpc-ibm-aix*)
conftest_s='
.extern __get_tpointer
......
gcc/doc/install.texi
......@@ -3269,6 +3269,10 @@ information have to.
@item
@uref{#nvptx-x-none,,nvptx-*-none}
@item
@uref{#or1k-x-elf,,or1k-*-elf}
@item
@uref{#or1k-x-linux,,or1k-*-linux}
@item
@uref{#powerpc-x-x,,powerpc*-*-*}
@item
@uref{#powerpc-x-darwin,,powerpc-*-darwin*}
......@@ -4239,6 +4243,21 @@ Use the @option{--disable-sjlj-exceptions} and
@html
<hr />
@end html
@anchor{or1k-x-elf}
@heading or1k-*-elf
The OpenRISC 1000 32-bit processor with delay slots.
This configuration is intended for embedded systems.
@html
<hr />
@end html
@anchor{or1k-x-linux}
@heading or1k-*-linux
The OpenRISC 1000 32-bit processor with delay slots.
@html
<hr />
@end html
@anchor{powerpc-x-x}
@heading powerpc-*-*
You can specify a default version for the @option{-mcpu=@var{cpu_type}}
......
gcc/doc/invoke.texi
......@@ -1010,6 +1010,11 @@ Objective-C and Objective-C++ Dialects}.
@emph{Nvidia PTX Options}
@gccoptlist{-m32 -m64 -mmainkernel -moptimize}
@emph{OpenRISC Options}
@gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol
-msoft-mul -msoft-div @gol
-mcmov -mror -msext -msfimm -mshftimm}
@emph{PDP-11 Options}
@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
-mint32 -mno-int16 -mint16 -mno-int32 @gol
......@@ -14984,6 +14989,7 @@ platform.
* NDS32 Options::
* Nios II Options::
* Nvidia PTX Options::
* OpenRISC Options::
* PDP-11 Options::
* picoChip Options::
* PowerPC Options::
......@@ -22762,6 +22768,68 @@ Generate code for use in OpenMP offloading: enables @option{-msoft-stack} and
@end table
@node OpenRISC Options
@subsection OpenRISC Options
@cindex OpenRISC Options
These options are defined for OpenRISC:
@table @gcctabopt
@item -mboard=@var{name}
@opindex mboard
Configure a board specific runtime. This will be passed to the linker for
newlib board library linking. The default is @code{or1ksim}.
@item -mnewlib
@opindex mnewlib
For compatibility, it's always newlib for elf now.
@item -mhard-div
@opindex mhard-div
Generate code for hardware which supports divide instructions. This is the
default.
@item -mhard-mul
@opindex mhard-mul
Generate code for hardware which supports multiply instructions. This is the
default.
@item -mcmov
@opindex mcmov
Generate code for hardware which supports the conditional move (@code{l.cmov})
instruction.
@item -mror
@opindex mror
Generate code for hardware which supports rotate right instructions.
@item -msext
@opindex msext
Generate code for hardware which supports sign-extension instructions.
@item -msfimm
@opindex msfimm
Generate code for hardware which supports set flag immediate (@code{l.sf*i})
instructions.
@item -mshftimm
@opindex mshftimm
Generate code for hardware which supports shift immediate related instructions
(i.e. @code{l.srai}, @code{l.srli}, @code{l.slli}, @code{1.rori}). Note, to
enable generation of the @code{l.rori} instruction the @option{-mror} flag must
also be specified.
@item -msoft-div
@opindex msoft-div
Generate code for hardware which requires divide instruction emulation.
@item -msoft-mul
@opindex msoft-mul
Generate code for hardware which requires multiply instruction emulation.
@end table
@node PDP-11 Options
@subsection PDP-11 Options
@cindex PDP-11 Options
gcc/doc/md.texi
......@@ -3003,6 +3003,31 @@ representing a supported PIC or TLS relocation.
@end table
@item OpenRISC---@file{config/or1k/constraints.md}
@table @code
@item I
Integer that is valid as an immediate operand in an
instruction taking a signed 16-bit number. Range
@minus{}32768 to 32767.
@item K
Integer that is valid as an immediate operand in an
instruction taking an unsigned 16-bit number. Range
0 to 65535.
@item M
Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi})
@item O
Zero
@ifset INTERNALS
@item c
Register usable for sibcalls.
@end ifset
@end table
@item PDP-11---@file{config/pdp11/constraints.md}
@table @code
@item a
......
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