[AArch64] Fix another ICE with -mgeneral-regs-only

gcc/:

	* config/aarch64/aarch64.md (<optab><fcvt_target><GPF:mode>2):
	Condition on TARGET_FLOAT.

gcc/testsuite/:

	* gcc.target/aarch64/mgeneral-regs_3.c: New.

From-SVN: r224910

gcc/ChangeLog

 2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
 
+	* config/aarch64/aarch64.md (<optab><fcvt_target><GPF:mode>2):
+	Condition on TARGET_FLOAT.
+
+2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
+
 	* doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd
 	and (no)crypto.
 

gcc/config/aarch64/aarch64.md

@@ -4117,7 +4117,7 @@
 (define_insn "<optab><fcvt_target><GPF:mode>2"
   [(set (match_operand:GPF 0 "register_operand" "=w,w")
         (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
-  ""
+  "TARGET_FLOAT"
   "@
    <su_optab>cvtf\t%<GPF:s>0, %<s>1
    <su_optab>cvtf\t%<GPF:s>0, %<w1>1"

gcc/testsuite/ChangeLog

 2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
 
+	* gcc.target/aarch64/mgeneral-regs_3.c: New.
+
+2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
+
 	* gcc.target/aarch64/mgeneral-regs_1.c: New file.
 	* gcc.target/aarch64/mgeneral-regs_2.c: New file.
 	* gcc.target/aarch64/nofp_1.c: New file.

gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c

+/* { dg-options "-mgeneral-regs-only -O2" } */
+
+extern void abort (void);
+
+int
+test (int i, ...)
+{
+  float f = (float) i; /* { dg-error "'-mgeneral-regs-only' is incompatible with floating-point code" } */
+  if (f != f) abort ();
+  return 2;
+}