altivec.md (build_vector_mask_for_load): Use MEM_P.

	* config/rs6000/altivec.md (build_vector_mask_for_load): Use MEM_P.
	* config/rs6000/constraints.md (Q constraint): Use REG_P.
	* config/rs6000/darwin.h (PREFERRED_RELOAD_CLASS): Use SYMBOL_REF_P.
	* config/rs6000/freebsd64.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Use
	SYMBOL_REF_P, CONST_INT_P and CONST_DOUBLE_P.
	* config/rs6000/linux64.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
	* config/rs6000/predicates.md (altivec_register_operand, vint_operand,
	vsx_register_operand, vsx_reg_sfsubreg_ok, vfloat_operand,
	vlogical_operand, gpc_reg_operand, int_reg_operand,
	int_reg_operand_not_pseudo): Use SUBREG_P and HARD_REGISTER_P.
	(ca_operand, base_reg_operand, htm_spr_reg_operand, cc_reg_operand,
	cc_reg_not_cr0_operand, input_operand): Use SUBREG_P.
	(save_world_operation, restore_world_operation, lmw_operation,
	stmw_operation): Use MEM_P and REG_P.
	(tie_operand): Use MEM_P.
	(vrsave_operation, crsave_operation): Use REG_P.
	(mfcr_operation, mtcrf_operation): Use REG_P and CONST_INT_P.
	(fpr_reg_operand): Use SUBREG_P and HARD_REGISTER_NUM_P.
	(quad_int_reg_operand): Use HARD_REGISTER_NUM_P.
	(call_operand): Use HARD_REGISTER_P.
	(indexed_or_indirect_operand, altivec_indexed_or_indirect_operand):
	Use CONST_INT_P.
	(lwa_operand): Use SUBREG_P, REG_P and CONST_INT_P.
	* config/rs6000/rs6000-p8swap.c (insn_is_load_p, insn_is_store_p,
	quad_aligned_load_p, replace_swapped_aligned_store,
	recombine_lvx_pattern, replace_swapped_aligned_load,
	recombine_stvx_pattern): Use MEM_P.
	(const_load_sequence_p, adjust_vperm, replace_swapped_load_constant):
	Use MEM_P and SYMBOL_REF_P.
	(rtx_is_swappable_p): Use REG_P and CONST_INT_P.
	(insn_is_swappable_p): Use REG_P and MEM_P.
	(insn_is_swap_p, (alignment_mask): Use CONST_INT_P.
	* config/rs6000/rs6000-string.c (expand_block_clear, expand_block_move):
	Use CONST_INT_P.
	* config/rs6000/rs6000.c (rs6000_secondary_reload, rs6000_emit_cmove):
	Use CONST_DOUBLE_P.
	(rs6000_output_move_128bit): Use CONST_DOUBLE_P, CONST_INT_P and
	CONST_WIDE_INT_P.
	(rs6000_legitimize_address): Use CONST_DOUBLE_P, CONST_INT_P,
	CONST_WIDE_INT_P, REG_P and SYMBOL_REF_P.
	(rs6000_emit_move): Use CONST_DOUBLE_P, CONST_INT_P, HARD_REGISTER_P,
	HARD_REGISTER_NUM_P, MEM_P, REG_P, SUBREG_P, SYMBOL_REF_P and
	reg_or_subregno:
	(output_toc): Use CONST_DOUBLE_P, CONST_INT_P and SYMBOL_REF_P.
	(easy_altivec_constant, rs6000_legitimate_offset_address_p,
	rs6000_mode_dependent_address, rs6000_expand_mtfsf_builtin,
	rs6000_expand_set_fpscr_rn_builtin, rs6000_expand_set_fpscr_drn_builtin,
	rs6000_expand_unop_builtin, INT_P, rs6000_generate_compare,
	rs6000_machopic_legitimize_pic_address, rs6000_split_logical_inner,
	rs6000_split_logical_di): Use CONST_INT_P.
	(rs6000_legitimize_reload_address): Use CONST_INT_P, HARD_REGISTER_P,
	REG_P and SYMBOL_REF_P.
	(setup_incoming_varargs, rs6000_rtx_costs): Use CONST_INT_P and MEM_P.
	(print_operand): Use CONST_INT_P, MEM_P and REG_P.
	(virtual_stack_registers_memory_p, rs6000_legitimate_address_p,
	mems_ok_for_quad_peep): Use CONST_INT_P and REG_P.
	(rs6000_secondary_reload_memory): Use CONST_INT_P and SUBREG_P.
	(small_data_operand, print_operand_address): Use CONST_INT_P and
	SYMBOL_REF_P.
	(split_stack_arg_pointer_used_p): Use HARD_REGISTER_P.
	(rs6000_init_hard_regno_mode_ok, direct_move_p):
	Use HARD_REGISTER_NUM_P.
	(rs6000_secondary_reload_gpr): Use HARD_REGISTER_NUM_P and MEM_P.
	(rs6000_secondary_reload_class): Use HARD_REGISTER_NUM_P, REG_P,
	SUBREG_P and SYMBOL_REF_P.
	(register_to_reg_type, rs6000_secondary_reload_inner): Use SUBREG_P
	and HARD_REGISTER_NUM_P.
	(rs6000_adjust_vec_address): Use HARD_REGISTER_NUM_P and
	reg_or_subregno.
	(rs6000_adjust_cost, find_mem_ref): Use MEM_P.
	(macho_lo_sum_memory_operand, rs6000_eliminate_indexed_memrefs): Use
	MEM_P and REG_P.
	(legitimate_indirect_address_p, legitimate_lo_sum_address_p,
	registers_ok_for_quad_peep, rs6000_output_function_epilogue,
	find_addr_reg): Use REG_P.
	(altivec_expand_vec_perm_const): Use REG_P and SUBREG_P.
	(rs6000_emit_le_vsx_move): Use SUBREG_P.
	(offsettable_ok_by_alignment, constant_pool_expr_p,
	legitimate_small_data_p, rs6000_output_dwarf_dtprel,
	rs6000_delegitimize_address, rs6000_const_not_ok_for_debug_p,
	rs6000_cannot_force_const_mem, rs6000_output_addr_const_extra,
	rs6000_assemble_integer, create_TOC_reference,
	rs6000_emit_allocate_stack, rs6000_xcoff_encode_section_info,
	rs6000_call_aix, rs6000_call_aix): Use SYMBOL_REF_P.
	(rs6000_split_vec_extract_var): Use reg_or_subregno.
	* config/rs6000/rtems.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Use
	CONST_DOUBLE_P, CONST_INT_P and SYMBOL_REF_P.
	* config/rs6000/sysv4.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
	* config/rs6000/xcoff.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
	* config/rs6000/rs6000.h (RS6000_SYMBOL_REF_TLS_P): Use SYMBOL_REF_P.
	(REGNO_OK_FOR_INDEX_P, REGNO_OK_FOR_BASE_P): Use HARD_REGISTER_NUM_P.
	(INT_REG_OK_FOR_INDEX_P, INT_REG_OK_FOR_BASE_P): Use HARD_REGISTER_P.
	(CONSTANT_ADDRESS_P): Use CONST_INT_P and SYMBOL_REF_P.
	* config/rs6000/rs6000.md (define_expands strlensi, mod<mode>3
	and cbranch<mode>4): Use CONST_INT_P.
	(multiple define_splits): Use REG_P and SUBREG_P.
	(define_expands call, call_value): Use MEM_P.
	(define_expands sibcall, sibcall_value): Use CONST_INT_P and  MEM_P.
	(define insn *mtcrfsi): Use CONST_INT_P and REG_P.
	* config/rs6000/vsx.md (*vsx_le_perm_load_<mode>,
	*vsx_le_perm_load_v8hi, *vsx_le_perm_load_v16qi): Use HARD_REGISTER_P
	and HARD_REGISTER_NUM_P.
	(multiple define_splits): Use HARD_REGISTER_NUM_P.

From-SVN: r268253

gcc/ChangeLog

+2019-01-24  Peter Bergner  <bergner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (build_vector_mask_for_load): Use MEM_P.
+	* config/rs6000/constraints.md (Q constraint): Use REG_P.
+	* config/rs6000/darwin.h (PREFERRED_RELOAD_CLASS): Use SYMBOL_REF_P.
+	* config/rs6000/freebsd64.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Use
+	SYMBOL_REF_P, CONST_INT_P and CONST_DOUBLE_P.
+	* config/rs6000/linux64.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
+	* config/rs6000/predicates.md (altivec_register_operand, vint_operand,
+	vsx_register_operand, vsx_reg_sfsubreg_ok, vfloat_operand,
+	vlogical_operand, gpc_reg_operand, int_reg_operand,
+	int_reg_operand_not_pseudo): Use SUBREG_P and HARD_REGISTER_P.
+	(ca_operand, base_reg_operand, htm_spr_reg_operand, cc_reg_operand,
+	cc_reg_not_cr0_operand, input_operand): Use SUBREG_P.
+	(save_world_operation, restore_world_operation, lmw_operation,
+	stmw_operation): Use MEM_P and REG_P.
+	(tie_operand): Use MEM_P.
+	(vrsave_operation, crsave_operation): Use REG_P.
+	(mfcr_operation, mtcrf_operation): Use REG_P and CONST_INT_P.
+	(fpr_reg_operand): Use SUBREG_P and HARD_REGISTER_NUM_P.
+	(quad_int_reg_operand): Use HARD_REGISTER_NUM_P.
+	(call_operand): Use HARD_REGISTER_P.
+	(indexed_or_indirect_operand, altivec_indexed_or_indirect_operand):
+	Use CONST_INT_P.
+	(lwa_operand): Use SUBREG_P, REG_P and CONST_INT_P.
+	* config/rs6000/rs6000-p8swap.c (insn_is_load_p, insn_is_store_p,
+	quad_aligned_load_p, replace_swapped_aligned_store,
+	recombine_lvx_pattern, replace_swapped_aligned_load,
+	recombine_stvx_pattern): Use MEM_P.
+	(const_load_sequence_p, adjust_vperm, replace_swapped_load_constant):
+	Use MEM_P and SYMBOL_REF_P.
+	(rtx_is_swappable_p): Use REG_P and CONST_INT_P.
+	(insn_is_swappable_p): Use REG_P and MEM_P.
+	(insn_is_swap_p, (alignment_mask): Use CONST_INT_P.
+	* config/rs6000/rs6000-string.c (expand_block_clear, expand_block_move):
+	Use CONST_INT_P.
+	* config/rs6000/rs6000.c (rs6000_secondary_reload, rs6000_emit_cmove):
+	Use CONST_DOUBLE_P.
+	(rs6000_output_move_128bit): Use CONST_DOUBLE_P, CONST_INT_P and
+	CONST_WIDE_INT_P.
+	(rs6000_legitimize_address): Use CONST_DOUBLE_P, CONST_INT_P,
+	CONST_WIDE_INT_P, REG_P and SYMBOL_REF_P.
+	(rs6000_emit_move): Use CONST_DOUBLE_P, CONST_INT_P, HARD_REGISTER_P,
+	HARD_REGISTER_NUM_P, MEM_P, REG_P, SUBREG_P, SYMBOL_REF_P and
+	reg_or_subregno:
+	(output_toc): Use CONST_DOUBLE_P, CONST_INT_P and SYMBOL_REF_P.
+	(easy_altivec_constant, rs6000_legitimate_offset_address_p,
+	rs6000_mode_dependent_address, rs6000_expand_mtfsf_builtin,
+	rs6000_expand_set_fpscr_rn_builtin, rs6000_expand_set_fpscr_drn_builtin,
+	rs6000_expand_unop_builtin, INT_P, rs6000_generate_compare,
+	rs6000_machopic_legitimize_pic_address, rs6000_split_logical_inner,
+	rs6000_split_logical_di): Use CONST_INT_P.
+	(rs6000_legitimize_reload_address): Use CONST_INT_P, HARD_REGISTER_P,
+	REG_P and SYMBOL_REF_P.
+	(setup_incoming_varargs, rs6000_rtx_costs): Use CONST_INT_P and MEM_P.
+	(print_operand): Use CONST_INT_P, MEM_P and REG_P.
+	(virtual_stack_registers_memory_p, rs6000_legitimate_address_p,
+	mems_ok_for_quad_peep): Use CONST_INT_P and REG_P.
+	(rs6000_secondary_reload_memory): Use CONST_INT_P and SUBREG_P.
+	(small_data_operand, print_operand_address): Use CONST_INT_P and
+	SYMBOL_REF_P.
+	(split_stack_arg_pointer_used_p): Use HARD_REGISTER_P.
+	(rs6000_init_hard_regno_mode_ok, direct_move_p):
+	Use HARD_REGISTER_NUM_P.
+	(rs6000_secondary_reload_gpr): Use HARD_REGISTER_NUM_P and MEM_P.
+	(rs6000_secondary_reload_class): Use HARD_REGISTER_NUM_P, REG_P,
+	SUBREG_P and SYMBOL_REF_P.
+	(register_to_reg_type, rs6000_secondary_reload_inner): Use SUBREG_P
+	and HARD_REGISTER_NUM_P.
+	(rs6000_adjust_vec_address): Use HARD_REGISTER_NUM_P and
+	reg_or_subregno.
+	(rs6000_adjust_cost, find_mem_ref): Use MEM_P.
+	(macho_lo_sum_memory_operand, rs6000_eliminate_indexed_memrefs): Use
+	MEM_P and REG_P.
+	(legitimate_indirect_address_p, legitimate_lo_sum_address_p,
+	registers_ok_for_quad_peep, rs6000_output_function_epilogue,
+	find_addr_reg): Use REG_P.
+	(altivec_expand_vec_perm_const): Use REG_P and SUBREG_P.
+	(rs6000_emit_le_vsx_move): Use SUBREG_P.
+	(offsettable_ok_by_alignment, constant_pool_expr_p,
+	legitimate_small_data_p, rs6000_output_dwarf_dtprel,
+	rs6000_delegitimize_address, rs6000_const_not_ok_for_debug_p,
+	rs6000_cannot_force_const_mem, rs6000_output_addr_const_extra,
+	rs6000_assemble_integer, create_TOC_reference,
+	rs6000_emit_allocate_stack, rs6000_xcoff_encode_section_info,
+	rs6000_call_aix, rs6000_call_aix): Use SYMBOL_REF_P.
+	(rs6000_split_vec_extract_var): Use reg_or_subregno.
+	* config/rs6000/rtems.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Use
+	CONST_DOUBLE_P, CONST_INT_P and SYMBOL_REF_P.
+	* config/rs6000/sysv4.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
+	* config/rs6000/xcoff.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
+	* config/rs6000/rs6000.h (RS6000_SYMBOL_REF_TLS_P): Use SYMBOL_REF_P.
+	(REGNO_OK_FOR_INDEX_P, REGNO_OK_FOR_BASE_P): Use HARD_REGISTER_NUM_P.
+	(INT_REG_OK_FOR_INDEX_P, INT_REG_OK_FOR_BASE_P): Use HARD_REGISTER_P.
+	(CONSTANT_ADDRESS_P): Use CONST_INT_P and SYMBOL_REF_P.
+	* config/rs6000/rs6000.md (define_expands strlensi, mod<mode>3
+	and cbranch<mode>4): Use CONST_INT_P.
+	(multiple define_splits): Use REG_P and SUBREG_P.
+	(define_expands call, call_value): Use MEM_P.
+	(define_expands sibcall, sibcall_value): Use CONST_INT_P and  MEM_P.
+	(define insn *mtcrfsi): Use CONST_INT_P and REG_P.
+	* config/rs6000/vsx.md (*vsx_le_perm_load_<mode>,
+	*vsx_le_perm_load_v8hi, *vsx_le_perm_load_v16qi): Use HARD_REGISTER_P
+	and HARD_REGISTER_NUM_P.
+	(multiple define_splits): Use HARD_REGISTER_NUM_P.
+
 2019-01-24  Uroš Bizjak  <ubizjak@gmail.com>
 
 	PR rtl-optimization/88948

gcc/config/rs6000/altivec.md

@@ -2523,7 +2523,7 @@
   rtx addr;
   rtx temp;
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
+  gcc_assert (MEM_P (operands[1]));
 
   addr = XEXP (operands[1], 0);
   temp = gen_reg_rtx (GET_MODE (addr));

gcc/config/rs6000/constraints.md

@@ -281,7 +281,7 @@ several times, or that might not access it at all."
   "Memory operand that is an offset from a register (it is usually better
 to use @samp{m} or @samp{es} in @code{asm} statements)"
   (and (match_code "mem")
-       (match_test "GET_CODE (XEXP (op, 0)) == REG")))
+       (match_test "REG_P (XEXP (op, 0))")))
 
 (define_memory_constraint "Y"
   "memory operand for 8 byte and 16 byte gpr load/store"

gcc/config/rs6000/darwin.h

@@ -342,7 +342,7 @@ extern int darwin_emit_branch_islands;
   ((CONSTANT_P (X)						\
     && reg_classes_intersect_p ((CLASS), FLOAT_REGS))		\
    ? NO_REGS							\
-   : ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == HIGH)	\
+   : ((SYMBOL_REF_P (X) || GET_CODE (X) == HIGH)		\
       && reg_class_subset_p (BASE_REGS, (CLASS)))		\
    ? BASE_REGS							\
    : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT			\

gcc/config/rs6000/freebsd64.h

@@ -400,13 +400,13 @@ extern int dot_symbols;
 #undef  ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE)                        \
   (TARGET_TOC                                                           \
-   && (GET_CODE (X) == SYMBOL_REF                                       \
+   && (SYMBOL_REF_P (X)							\
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS      \
-           && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)           \
+           && SYMBOL_REF_P (XEXP (XEXP (X, 0), 0)))			\
        || GET_CODE (X) == LABEL_REF                                     \
-       || (GET_CODE (X) == CONST_INT                                    \
+       || (CONST_INT_P (X)						\
            && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))      \
-       || (GET_CODE (X) == CONST_DOUBLE                                 \
+       || (CONST_DOUBLE_P (X)						\
            && ((TARGET_64BIT                                            \
                 && (TARGET_MINIMAL_TOC                                  \
                     || (SCALAR_FLOAT_MODE_P (GET_MODE (X))              \

gcc/config/rs6000/linux64.h

@@ -580,14 +580,14 @@ extern int dot_symbols;
 #undef  ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE)			\
   (TARGET_TOC								\
-   && (GET_CODE (X) == SYMBOL_REF					\
+   && (SYMBOL_REF_P (X)							\
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
-	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
+	   && SYMBOL_REF_P (XEXP (XEXP (X, 0), 0)))			\
        || GET_CODE (X) == LABEL_REF					\
-       || (GET_CODE (X) == CONST_INT 					\
+       || (CONST_INT_P (X)						\
 	   && TARGET_CMODEL != CMODEL_MEDIUM				\
 	   && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))	\
-       || (GET_CODE (X) == CONST_DOUBLE					\
+       || (CONST_DOUBLE_P (X)						\
 	   && ((TARGET_64BIT						\
 		&& (TARGET_MINIMAL_TOC					\
 		    || (SCALAR_FLOAT_MODE_P (GET_MODE (X))		\

gcc/config/rs6000/rs6000-string.c

@@ -49,7 +49,7 @@ expand_block_clear (rtx operands[])
   rtx orig_dest = operands[0];
   rtx bytes_rtx	= operands[1];
   rtx align_rtx = operands[3];
-  bool constp	= (GET_CODE (bytes_rtx) == CONST_INT);
+  bool constp	= CONST_INT_P (bytes_rtx);
   HOST_WIDE_INT align;
   HOST_WIDE_INT bytes;
   int offset;
@@ -61,7 +61,7 @@ expand_block_clear (rtx operands[])
     return 0;
 
   /* This must be a fixed size alignment  */
-  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+  gcc_assert (CONST_INT_P (align_rtx));
   align = INTVAL (align_rtx) * BITS_PER_UNIT;
 
   /* Anything to clear? */
@@ -113,7 +113,7 @@ expand_block_clear (rtx operands[])
 		 reload, not one per store.  */
 	      addr = XEXP (orig_dest, 0);
 	      if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
-		  && GET_CODE (XEXP (addr, 1)) == CONST_INT
+		  && CONST_INT_P (XEXP (addr, 1))
 		  && (INTVAL (XEXP (addr, 1)) & 3) != 0)
 		{
 		  addr = copy_addr_to_reg (addr);
@@ -2705,7 +2705,7 @@ expand_block_move (rtx operands[])
   rtx orig_src	= operands[1];
   rtx bytes_rtx	= operands[2];
   rtx align_rtx = operands[3];
-  int constp	= (GET_CODE (bytes_rtx) == CONST_INT);
+  int constp	= CONST_INT_P (bytes_rtx);
   int align;
   int bytes;
   int offset;
@@ -2718,7 +2718,7 @@ expand_block_move (rtx operands[])
     return 0;
 
   /* This must be a fixed size alignment */
-  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+  gcc_assert (CONST_INT_P (align_rtx));
   align = INTVAL (align_rtx) * BITS_PER_UNIT;
 
   /* Anything to move? */
@@ -2762,7 +2762,7 @@ expand_block_move (rtx operands[])
 		 reload, not one per load and/or store.  */
 	      addr = XEXP (orig_dest, 0);
 	      if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
-		  && GET_CODE (XEXP (addr, 1)) == CONST_INT
+		  && CONST_INT_P (XEXP (addr, 1))
 		  && (INTVAL (XEXP (addr, 1)) & 3) != 0)
 		{
 		  addr = copy_addr_to_reg (addr);
@@ -2770,7 +2770,7 @@ expand_block_move (rtx operands[])
 		}
 	      addr = XEXP (orig_src, 0);
 	      if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
-		  && GET_CODE (XEXP (addr, 1)) == CONST_INT
+		  && CONST_INT_P (XEXP (addr, 1))
 		  && (INTVAL (XEXP (addr, 1)) & 3) != 0)
 		{
 		  addr = copy_addr_to_reg (addr);

gcc/config/rs6000/rs6000.h

@@ -240,7 +240,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 
 /* Return 1 for a symbol ref for a thread-local storage symbol.  */
 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
-  (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
+  (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0)
 
 #ifdef IN_LIBGCC2
 /* For libgcc2 we make sure this is a compile time constant */
@@ -1685,7 +1685,7 @@ typedef struct rs6000_args
    allocation.  */
 
 #define REGNO_OK_FOR_INDEX_P(REGNO)				\
-((REGNO) < FIRST_PSEUDO_REGISTER				\
+(HARD_REGISTER_NUM_P (REGNO)					\
  ? (REGNO) <= 31 || (REGNO) == 67				\
    || (REGNO) == FRAME_POINTER_REGNUM				\
  : (reg_renumber[REGNO] >= 0					\
@@ -1693,7 +1693,7 @@ typedef struct rs6000_args
 	|| reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
 
 #define REGNO_OK_FOR_BASE_P(REGNO)				\
-((REGNO) < FIRST_PSEUDO_REGISTER				\
+(HARD_REGISTER_NUM_P (REGNO)					\
  ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67		\
    || (REGNO) == FRAME_POINTER_REGNUM				\
  : (reg_renumber[REGNO] > 0					\
@@ -1703,13 +1703,13 @@ typedef struct rs6000_args
 /* Nonzero if X is a hard reg that can be used as an index
    or if it is a pseudo reg in the non-strict case.  */
 #define INT_REG_OK_FOR_INDEX_P(X, STRICT)			\
-  ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER)		\
+  ((!(STRICT) && !HARD_REGISTER_P (X))				\
    || REGNO_OK_FOR_INDEX_P (REGNO (X)))
 
 /* Nonzero if X is a hard reg that can be used as a base reg
    or if it is a pseudo reg in the non-strict case.  */
 #define INT_REG_OK_FOR_BASE_P(X, STRICT)			\
-  ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER)		\
+  ((!(STRICT) && !HARD_REGISTER_P (X))				\
    || REGNO_OK_FOR_BASE_P (REGNO (X)))
 
 
@@ -1720,8 +1720,8 @@ typedef struct rs6000_args
 /* Recognize any constant value that is a valid address.  */
 
 #define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
+  (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X)			\
+   || CONST_INT_P (X) || GET_CODE (X) == CONST				\
    || GET_CODE (X) == HIGH)
 
 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)

gcc/config/rs6000/rs6000.md

@@ -1570,7 +1570,7 @@
   rtx addr, scratch_string, word1, word2, scratch_dlmzb;
   rtx loop_label, end_label, mem, cr0, cond;
   if (search_char != const0_rtx
-      || GET_CODE (align) != CONST_INT
+      || !CONST_INT_P (align)
       || INTVAL (align) < 8)
         FAIL;
   word1 = gen_reg_rtx (SImode);
@@ -3132,7 +3132,7 @@
   rtx temp1;
   rtx temp2;
 
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) <= 0
       || (i = exact_log2 (INTVAL (operands[2]))) < 0)
     {
@@ -7210,9 +7210,9 @@
   [(set (match_operand:FMOVE32 0 "gpc_reg_operand")
 	(match_operand:FMOVE32 1 "const_double_operand"))]
   "reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
+       || (SUBREG_P (operands[0])
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 3))]
 {
@@ -7422,9 +7422,9 @@
   [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
 	(match_operand:FMOVE64 1 "const_int_operand"))]
   "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
+       || (SUBREG_P (operands[0])
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 1))]
@@ -7442,9 +7442,9 @@
   [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
 	(match_operand:FMOVE64 1 "const_double_operand"))]
   "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
+       || (SUBREG_P (operands[0])
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 5))]
@@ -7464,9 +7464,9 @@
   [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
 	(match_operand:FMOVE64 1 "const_double_operand"))]
   "TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
+       || (SUBREG_P (operands[0])
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 3))]
 {
@@ -10236,7 +10236,7 @@
     operands[0] = machopic_indirect_call_target (operands[0]);
 #endif
 
-  gcc_assert (GET_CODE (operands[0]) == MEM);
+  gcc_assert (MEM_P (operands[0]));
 
   operands[0] = XEXP (operands[0], 0);
 
@@ -10265,7 +10265,7 @@
     operands[1] = machopic_indirect_call_target (operands[1]);
 #endif
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
+  gcc_assert (MEM_P (operands[1]));
 
   operands[1] = XEXP (operands[1], 0);
 
@@ -10722,8 +10722,8 @@
     operands[0] = machopic_indirect_call_target (operands[0]);
 #endif
 
-  gcc_assert (GET_CODE (operands[0]) == MEM);
-  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
+  gcc_assert (MEM_P (operands[0]));
+  gcc_assert (CONST_INT_P (operands[1]));
 
   operands[0] = XEXP (operands[0], 0);
 
@@ -10752,8 +10752,8 @@
     operands[1] = machopic_indirect_call_target (operands[1]);
 #endif
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
-  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+  gcc_assert (MEM_P (operands[1]));
+  gcc_assert (CONST_INT_P (operands[2]));
 
   operands[1] = XEXP (operands[1], 0);
 
@@ -11046,7 +11046,7 @@
 {
   /* Take care of the possibility that operands[2] might be negative but
      this might be a logical operation.  That insn doesn't exist.  */
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && INTVAL (operands[2]) < 0)
     {
       operands[2] = force_reg (<MODE>mode, operands[2]);
@@ -12950,9 +12950,9 @@
         (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
 		    (match_operand 2 "immediate_operand" "n")]
 		   UNSPEC_MOVESI_TO_CR))]
-  "GET_CODE (operands[0]) == REG
+  "REG_P (operands[0])
    && CR_REGNO_P (REGNO (operands[0]))
-   && GET_CODE (operands[2]) == CONST_INT
+   && CONST_INT_P (operands[2])
    && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
   "mtcrf %R0,%1"
   [(set_attr "type" "mtcr")])

gcc/config/rs6000/rtems.h

@@ -222,13 +222,13 @@
 #undef  ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE)			\
   (TARGET_TOC								\
-   && (GET_CODE (X) == SYMBOL_REF					\
+   && (SYMBOL_REF_P (X)							\
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
-	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
+	   && SYMBOL_REF_P (XEXP (XEXP (X, 0), 0)))			\
        || GET_CODE (X) == LABEL_REF					\
-       || (GET_CODE (X) == CONST_INT 					\
+       || (CONST_INT_P (X)						\
 	   && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))	\
-       || (GET_CODE (X) == CONST_DOUBLE					\
+       || (CONST_DOUBLE_P (X)						\
 	   && ((TARGET_64BIT						\
 		&& (TARGET_MINIMAL_TOC					\
 		    || (SCALAR_FLOAT_MODE_P (GET_MODE (X))		\

gcc/config/rs6000/sysv4.h

@@ -353,14 +353,14 @@ do {									\
 #undef	ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
 #define	ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE)			\
   (TARGET_TOC								\
-   && (GET_CODE (X) == SYMBOL_REF					\
+   && (SYMBOL_REF_P (X)							\
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
-	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
+	   && SYMBOL_REF_P (XEXP (XEXP (X, 0), 0)))			\
        || GET_CODE (X) == LABEL_REF					\
-       || (GET_CODE (X) == CONST_INT 					\
+       || (CONST_INT_P (X)						\
 	   && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))	\
        || (!TARGET_NO_FP_IN_TOC						\
-	   && GET_CODE (X) == CONST_DOUBLE				\
+	   && CONST_DOUBLE_P (X)					\
 	   && SCALAR_FLOAT_MODE_P (GET_MODE (X))			\
 	   && BITS_PER_WORD == HOST_BITS_PER_INT)))
 

gcc/config/rs6000/vsx.md

@@ -459,7 +459,7 @@
      allocation and the hard register destination is not in the altivec
      range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((reg_or_subregno (operands[0]) >= FIRST_PSEUDO_REGISTER)
+      && (!HARD_REGISTER_NUM_P (reg_or_subregno (operands[0]))
 	  || ALTIVEC_REGNO_P (reg_or_subregno (operands[0]))))
     {
       rtx mem_address = XEXP (mem, 0);
@@ -509,7 +509,7 @@
      allocation and the hard register destination is not in the altivec
      range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((REGNO(operands[0]) >= FIRST_PSEUDO_REGISTER)
+      && (!HARD_REGISTER_P (operands[0])
 	  || ALTIVEC_REGNO_P (REGNO(operands[0]))))
     {
       rtx mem_address = XEXP (mem, 0);
@@ -563,7 +563,7 @@
      allocation and the hard register destination is not in the altivec
      range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((REGNO(operands[0]) >= FIRST_PSEUDO_REGISTER)
+      && (!HARD_REGISTER_P (operands[0])
 	  || ALTIVEC_REGNO_P (REGNO(operands[0]))))
     {
       rtx mem_address = XEXP (mem, 0);
@@ -625,7 +625,7 @@
      allocation and the hard register destination is not in the altivec
      range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((REGNO(operands[0]) >= FIRST_PSEUDO_REGISTER)
+      && (!HARD_REGISTER_P (operands[0])
 	  || ALTIVEC_REGNO_P (REGNO(operands[0]))))
     {
       rtx mem_address = XEXP (mem, 0);
@@ -678,8 +678,8 @@
   /* Don't apply the swap optimization if we've already performed register
      allocation and the hard register source is not in the altivec range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((reg_or_subregno (operands[1]) >= FIRST_PSEUDO_REGISTER)
-          || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
+      && (!HARD_REGISTER_NUM_P (reg_or_subregno (operands[1]))
+	  || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
     {
       rtx mem_address = XEXP (mem, 0);
       enum machine_mode mode = GET_MODE (mem);
@@ -750,8 +750,8 @@
   /* Don't apply the swap optimization if we've already performed register
      allocation and the hard register source is not in the altivec range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((reg_or_subregno (operands[1]) >= FIRST_PSEUDO_REGISTER)
-          || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
+      && (!HARD_REGISTER_NUM_P (reg_or_subregno (operands[1]))
+	  || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
     {
       rtx mem_address = XEXP (mem, 0);
       enum machine_mode mode = GET_MODE (mem);
@@ -829,8 +829,8 @@
   /* Don't apply the swap optimization if we've already performed register
      allocation and the hard register source is not in the altivec range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((reg_or_subregno (operands[1]) >= FIRST_PSEUDO_REGISTER)
-          || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
+      && (!HARD_REGISTER_NUM_P (reg_or_subregno (operands[1]))
+	  || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
     {
       rtx mem_address = XEXP (mem, 0);
       enum machine_mode mode = GET_MODE (mem);
@@ -922,8 +922,8 @@
   /* Don't apply the swap optimization if we've already performed register
      allocation and the hard register source is not in the altivec range.  */
   if ((MEM_ALIGN (mem) >= 128)
-      && ((reg_or_subregno (operands[1]) >= FIRST_PSEUDO_REGISTER)
-          || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
+      && (!HARD_REGISTER_NUM_P (reg_or_subregno (operands[1]))
+	  || ALTIVEC_REGNO_P (reg_or_subregno (operands[1]))))
     {
       rtx mem_address = XEXP (mem, 0);
       enum machine_mode mode = GET_MODE (mem);

gcc/config/rs6000/xcoff.h

@@ -75,13 +75,13 @@
 
 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE)			\
   (TARGET_TOC								\
-   && (GET_CODE (X) == SYMBOL_REF					\
+   && (SYMBOL_REF_P (X)							\
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
-	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
+	   && SYMBOL_REF_P (XEXP (XEXP (X, 0), 0)))			\
        || GET_CODE (X) == LABEL_REF					\
-       || (GET_CODE (X) == CONST_INT 					\
+       || (CONST_INT_P (X)						\
 	   && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))	\
-       || (GET_CODE (X) == CONST_DOUBLE					\
+       || (CONST_DOUBLE_P (X)						\
 	   && (TARGET_MINIMAL_TOC					\
 	       || (SCALAR_FLOAT_MODE_P (GET_MODE (X))			\
 		   && ! TARGET_NO_FP_IN_TOC)))))