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Commit 23742a9e by Rohit Arul Raj Committed by Edmar Wienskoski
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re PR middle-end/60102 (powerpc fp-bit ices at dwf_regno) 

	PR target/60102

[libgcc]
2014-07-31  Rohit  <rohitarulraj@freescale.com>
	* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update
	  based on change in SPE high register numbers and 3 HTM registers.

[gcc]
2014-07-31  Rohit  <rohitarulraj@freescale.com>
	* config/rs6000/rs6000.c
	  (rs6000_reg_names) : Add SPE high register names.
	  (alt_reg_names) : Likewise.
	  (rs6000_dwarf_register_span) : For SPE high registers, replace
	  dwarf register numbers with GCC hard register numbers.
	  (rs6000_init_dwarf_reg_sizes_extra) : Likewise.
	  (rs6000_dbx_register_number): For SPE high registers, return dwarf
	  register number for the corresponding GCC hard register number.

	* config/rs6000/rs6000.h
	  (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard
	  register numbers for SPE high registers.
	  (DWARF_FRAME_REGISTERS) :  Likewise.
	  (DWARF_REG_TO_UNWIND_COLUMN) : Likewise.
	  (DWARF_FRAME_REGNUM) : Likewise.
	  (FIXED_REGISTERS) : Likewise.
	  (CALL_USED_REGISTERS) : Likewise.
	  (CALL_REALLY_USED_REGISTERS) : Likewise.
	  (REG_ALLOC_ORDER) : Likewise.
	  (enum reg_class) : Likewise.
	  (REG_CLASS_NAMES) : Likewise.
	  (REG_CLASS_CONTENTS) : Likewise.
	  (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers.	

	* gcc.target/powerpc/pr60102.c: New testcase.

From-SVN: r213596
parent 62c986af
Showing with 60 additions and 16 deletions
gcc/ChangeLog
2014-08-04 Rohit <rohitarulraj@freescale.com>
PR target/60102
* config/rs6000/rs6000.c
(rs6000_reg_names) : Add SPE high register names.
(alt_reg_names) : Likewise.
(rs6000_dwarf_register_span) : For SPE high registers, replace
dwarf register numbers with GCC hard register numbers.
(rs6000_init_dwarf_reg_sizes_extra) : Likewise.
(rs6000_dbx_register_number): For SPE high registers, return dwarf
register number for the corresponding GCC hard register number.
* config/rs6000/rs6000.h
(FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard
register numbers for SPE high registers.
(DWARF_FRAME_REGISTERS) : Likewise.
(DWARF_REG_TO_UNWIND_COLUMN) : Likewise.
(DWARF_FRAME_REGNUM) : Likewise.
(FIXED_REGISTERS) : Likewise.
(CALL_USED_REGISTERS) : Likewise.
(CALL_REALLY_USED_REGISTERS) : Likewise.
(REG_ALLOC_ORDER) : Likewise.
(enum reg_class) : Likewise.
(REG_CLASS_NAMES) : Likewise.
(REG_CLASS_CONTENTS) : Likewise.
(SPE_HIGH_REGNO_P) : New macro to identify SPE high registers.
* gcc.target/powerpc/pr60102.c: New testcase.
2014-08-04 Richard Biener <rguenther@suse.de>
* gimple-fold.h (gimple_fold_builtin): Remove.
......
gcc/config/rs6000/rs6000.c
......@@ -1221,7 +1221,12 @@ char rs6000_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
"tfhar", "tfiar", "texasr"
"tfhar", "tfiar", "texasr",
/* SPE High registers. */
"0", "1", "2", "3", "4", "5", "6", "7",
"8", "9", "10", "11", "12", "13", "14", "15",
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31"
};
#ifdef TARGET_REGNAMES
......@@ -1249,7 +1254,12 @@ static const char alt_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
"tfhar", "tfiar", "texasr"
"tfhar", "tfiar", "texasr",
/* SPE High registers. */
"%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
"%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
"%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
"%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
};
#endif
......@@ -31411,13 +31421,13 @@ rs6000_dwarf_register_span (rtx reg)
{
if (BYTES_BIG_ENDIAN)
{
parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
}
else
{
parts[2 * i] = gen_rtx_REG (SImode, regno);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
}
}
......@@ -31437,11 +31447,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
rtx mem = gen_rtx_MEM (BLKmode, addr);
rtx value = gen_int_mode (4, mode);
for (i = 1201; i < 1232; i++)
for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
{
int column = DWARF_REG_TO_UNWIND_COLUMN (i);
HOST_WIDE_INT offset
= DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
int column = DWARF_REG_TO_UNWIND_COLUMN
(DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
emit_move_insn (adjust_address (mem, mode, offset), value);
}
......@@ -31460,9 +31470,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
{
int column = DWARF_REG_TO_UNWIND_COLUMN (i);
HOST_WIDE_INT offset
= DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
int column = DWARF_REG_TO_UNWIND_COLUMN
(DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
emit_move_insn (adjust_address (mem, mode, offset), value);
}
......@@ -31494,9 +31504,8 @@ rs6000_dbx_register_number (unsigned int regno)
return 99;
if (regno == SPEFSCR_REGNO)
return 612;
/* SPE high reg number. We get these values of regno from
rs6000_dwarf_register_span. */
gcc_assert (regno >= 1200 && regno < 1232);
if (SPE_HIGH_REGNO_P (regno))
return regno - FIRST_SPE_HIGH_REGNO + 1200;
return regno;
}
......
gcc/config/rs6000/rs6000.md
......@@ -56,6 +56,8 @@
(TFHAR_REGNO 114)
(TFIAR_REGNO 115)
(TEXASR_REGNO 116)
(FIRST_SPE_HIGH_REGNO 117)
(LAST_SPE_HIGH_REGNO 148)
])
;;
......
libgcc/ChangeLog
2014-08-04 Rohit <rohitarulraj@freescale.com>
PR target/60102
* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update
based on change in SPE high register numbers and 3 HTM registers.
2014-08-01 Nathan Sidwell <nathan@acm.org>
* Makefile.in (LIBGCOV_MERGE, LIBGCOV_PROFILER,
......
libgcc/config/rs6000/linux-unwind.h
......@@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind_Context *context,
#ifdef __SPE__
for (i = 14; i < 32; i++)
{
fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET;
fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset
fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET;
fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset
= (long) &regs->vregs - new_cfa + 4 * i;
}
#endif
......
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