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Commit 23742a9e by Rohit Arul Raj Committed by Edmar Wienskoski
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re PR middle-end/60102 (powerpc fp-bit ices at dwf_regno) 

	PR target/60102

[libgcc]
2014-07-31  Rohit  <rohitarulraj@freescale.com>
	* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update
	  based on change in SPE high register numbers and 3 HTM registers.

[gcc]
2014-07-31  Rohit  <rohitarulraj@freescale.com>
	* config/rs6000/rs6000.c
	  (rs6000_reg_names) : Add SPE high register names.
	  (alt_reg_names) : Likewise.
	  (rs6000_dwarf_register_span) : For SPE high registers, replace
	  dwarf register numbers with GCC hard register numbers.
	  (rs6000_init_dwarf_reg_sizes_extra) : Likewise.
	  (rs6000_dbx_register_number): For SPE high registers, return dwarf
	  register number for the corresponding GCC hard register number.

	* config/rs6000/rs6000.h
	  (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard
	  register numbers for SPE high registers.
	  (DWARF_FRAME_REGISTERS) :  Likewise.
	  (DWARF_REG_TO_UNWIND_COLUMN) : Likewise.
	  (DWARF_FRAME_REGNUM) : Likewise.
	  (FIXED_REGISTERS) : Likewise.
	  (CALL_USED_REGISTERS) : Likewise.
	  (CALL_REALLY_USED_REGISTERS) : Likewise.
	  (REG_ALLOC_ORDER) : Likewise.
	  (enum reg_class) : Likewise.
	  (REG_CLASS_NAMES) : Likewise.
	  (REG_CLASS_CONTENTS) : Likewise.
	  (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers.	

	* gcc.target/powerpc/pr60102.c: New testcase.

From-SVN: r213596
parent 62c986af
Showing with 183 additions and 57 deletions
gcc/ChangeLog
2014-08-04 Rohit <rohitarulraj@freescale.com>
PR target/60102
* config/rs6000/rs6000.c
(rs6000_reg_names) : Add SPE high register names.
(alt_reg_names) : Likewise.
(rs6000_dwarf_register_span) : For SPE high registers, replace
dwarf register numbers with GCC hard register numbers.
(rs6000_init_dwarf_reg_sizes_extra) : Likewise.
(rs6000_dbx_register_number): For SPE high registers, return dwarf
register number for the corresponding GCC hard register number.
* config/rs6000/rs6000.h
(FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard
register numbers for SPE high registers.
(DWARF_FRAME_REGISTERS) : Likewise.
(DWARF_REG_TO_UNWIND_COLUMN) : Likewise.
(DWARF_FRAME_REGNUM) : Likewise.
(FIXED_REGISTERS) : Likewise.
(CALL_USED_REGISTERS) : Likewise.
(CALL_REALLY_USED_REGISTERS) : Likewise.
(REG_ALLOC_ORDER) : Likewise.
(enum reg_class) : Likewise.
(REG_CLASS_NAMES) : Likewise.
(REG_CLASS_CONTENTS) : Likewise.
(SPE_HIGH_REGNO_P) : New macro to identify SPE high registers.
* gcc.target/powerpc/pr60102.c: New testcase.
2014-08-04 Richard Biener <rguenther@suse.de> 2014-08-04 Richard Biener <rguenther@suse.de>
* gimple-fold.h (gimple_fold_builtin): Remove. * gimple-fold.h (gimple_fold_builtin): Remove.
......
gcc/config/rs6000/rs6000.c
...@@ -1221,7 +1221,12 @@ char rs6000_reg_names[][8] = ...@@ -1221,7 +1221,12 @@ char rs6000_reg_names[][8] =
/* Soft frame pointer. */ /* Soft frame pointer. */
"sfp", "sfp",
/* HTM SPR registers. */ /* HTM SPR registers. */
"tfhar", "tfiar", "texasr" "tfhar", "tfiar", "texasr",
/* SPE High registers. */
"0", "1", "2", "3", "4", "5", "6", "7",
"8", "9", "10", "11", "12", "13", "14", "15",
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31"
}; };
#ifdef TARGET_REGNAMES #ifdef TARGET_REGNAMES
...@@ -1249,7 +1254,12 @@ static const char alt_reg_names[][8] = ...@@ -1249,7 +1254,12 @@ static const char alt_reg_names[][8] =
/* Soft frame pointer. */ /* Soft frame pointer. */
"sfp", "sfp",
/* HTM SPR registers. */ /* HTM SPR registers. */
"tfhar", "tfiar", "texasr" "tfhar", "tfiar", "texasr",
/* SPE High registers. */
"%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
"%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
"%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
"%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
}; };
#endif #endif
...@@ -31411,13 +31421,13 @@ rs6000_dwarf_register_span (rtx reg) ...@@ -31411,13 +31421,13 @@ rs6000_dwarf_register_span (rtx reg)
{ {
if (BYTES_BIG_ENDIAN) if (BYTES_BIG_ENDIAN)
{ {
parts[2 * i] = gen_rtx_REG (SImode, regno + 1200); parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno); parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
} }
else else
{ {
parts[2 * i] = gen_rtx_REG (SImode, regno); parts[2 * i] = gen_rtx_REG (SImode, regno);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200); parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
} }
} }
...@@ -31437,11 +31447,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree address) ...@@ -31437,11 +31447,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
rtx mem = gen_rtx_MEM (BLKmode, addr); rtx mem = gen_rtx_MEM (BLKmode, addr);
rtx value = gen_int_mode (4, mode); rtx value = gen_int_mode (4, mode);
for (i = 1201; i < 1232; i++) for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
{ {
int column = DWARF_REG_TO_UNWIND_COLUMN (i); int column = DWARF_REG_TO_UNWIND_COLUMN
HOST_WIDE_INT offset (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
= DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
emit_move_insn (adjust_address (mem, mode, offset), value); emit_move_insn (adjust_address (mem, mode, offset), value);
} }
...@@ -31460,9 +31470,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree address) ...@@ -31460,9 +31470,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++) for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
{ {
int column = DWARF_REG_TO_UNWIND_COLUMN (i); int column = DWARF_REG_TO_UNWIND_COLUMN
HOST_WIDE_INT offset (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
= DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
emit_move_insn (adjust_address (mem, mode, offset), value); emit_move_insn (adjust_address (mem, mode, offset), value);
} }
...@@ -31494,9 +31504,8 @@ rs6000_dbx_register_number (unsigned int regno) ...@@ -31494,9 +31504,8 @@ rs6000_dbx_register_number (unsigned int regno)
return 99; return 99;
if (regno == SPEFSCR_REGNO) if (regno == SPEFSCR_REGNO)
return 612; return 612;
/* SPE high reg number. We get these values of regno from if (SPE_HIGH_REGNO_P (regno))
rs6000_dwarf_register_span. */ return regno - FIRST_SPE_HIGH_REGNO + 1200;
gcc_assert (regno >= 1200 && regno < 1232);
return regno; return regno;
} }
......
gcc/config/rs6000/rs6000.h
...@@ -930,35 +930,36 @@ enum data_align { align_abi, align_opt, align_both }; ...@@ -930,35 +930,36 @@ enum data_align { align_abi, align_opt, align_both };
The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
#define FIRST_PSEUDO_REGISTER 117 #define FIRST_PSEUDO_REGISTER 149
/* This must be included for pre gcc 3.0 glibc compatibility. */ /* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
/* Add 32 dwarf columns for synthetic SPE registers. */ /* True if register is an SPE High register. */
#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) #define SPE_HIGH_REGNO_P(N) \
((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
/* SPE high registers added as hard regs.
The sfp register and 3 HTM registers
aren't included in DWARF_FRAME_REGISTERS. */
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
/* The SPE has an additional 32 synthetic registers, with DWARF debug /* The SPE has an additional 32 synthetic registers, with DWARF debug
info numbering for these registers starting at 1200. While eh_frame info numbering for these registers starting at 1200. While eh_frame
register numbering need not be the same as the debug info numbering, register numbering need not be the same as the debug info numbering,
we choose to number these regs for eh_frame at 1200 too. This allows we choose to number these regs for eh_frame at 1200 too.
future versions of the rs6000 backend to add hard registers and
continue to use the gcc hard register numbering for eh_frame. If the
extra SPE registers in eh_frame were numbered starting from the
current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
avoid invalidating older SPE eh_frame info.
We must map them here to avoid huge unwinder tables mostly consisting We must map them here to avoid huge unwinder tables mostly consisting
of unused space. */ of unused space. */
#define DWARF_REG_TO_UNWIND_COLUMN(r) \ #define DWARF_REG_TO_UNWIND_COLUMN(r) \
((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
/* Use standard DWARF numbering for DWARF debugging information. */ /* Use standard DWARF numbering for DWARF debugging information. */
#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
/* Use gcc hard register numbering for eh_frame. */ /* Use gcc hard register numbering for eh_frame. */
#define DWARF_FRAME_REGNUM(REGNO) (REGNO) #define DWARF_FRAME_REGNUM(REGNO) \
(SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO))
/* Map register numbers held in the call frame info that gcc has /* Map register numbers held in the call frame info that gcc has
collected using DWARF_FRAME_REGNUM to those that should be output in collected using DWARF_FRAME_REGNUM to those that should be output in
...@@ -990,7 +991,10 @@ enum data_align { align_abi, align_opt, align_both }; ...@@ -990,7 +991,10 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \ 1, 1 \
, 1, 1, 1, 1, 1, 1 \ , 1, 1, 1, 1, 1, 1, \
/* SPE High registers. */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
} }
/* 1 for registers not available across function calls. /* 1 for registers not available across function calls.
...@@ -1010,7 +1014,10 @@ enum data_align { align_abi, align_opt, align_both }; ...@@ -1010,7 +1014,10 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \ 1, 1 \
, 1, 1, 1, 1, 1, 1 \ , 1, 1, 1, 1, 1, 1, \
/* SPE High registers. */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
} }
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
...@@ -1029,7 +1036,10 @@ enum data_align { align_abi, align_opt, align_both }; ...@@ -1029,7 +1036,10 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0 \ 0, 0 \
, 0, 0, 0, 0, 0, 0 \ , 0, 0, 0, 0, 0, 0, \
/* SPE High registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
} }
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
...@@ -1113,7 +1123,10 @@ enum data_align { align_abi, align_opt, align_both }; ...@@ -1113,7 +1123,10 @@ enum data_align { align_abi, align_opt, align_both };
96, 95, 94, 93, 92, 91, \ 96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
109, 110, \ 109, 110, \
111, 112, 113, 114, 115, 116 \ 111, 112, 113, 114, 115, 116, \
117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
141, 142, 143, 144, 145, 146, 147, 148 \
} }
/* True if register is floating-point. */ /* True if register is floating-point. */
...@@ -1348,6 +1361,7 @@ enum reg_class ...@@ -1348,6 +1361,7 @@ enum reg_class
CR_REGS, CR_REGS,
NON_FLOAT_REGS, NON_FLOAT_REGS,
CA_REGS, CA_REGS,
SPE_HIGH_REGS,
ALL_REGS, ALL_REGS,
LIM_REG_CLASSES LIM_REG_CLASSES
}; };
...@@ -1379,6 +1393,7 @@ enum reg_class ...@@ -1379,6 +1393,7 @@ enum reg_class
"CR_REGS", \ "CR_REGS", \
"NON_FLOAT_REGS", \ "NON_FLOAT_REGS", \
"CA_REGS", \ "CA_REGS", \
"SPE_HIGH_REGS", \
"ALL_REGS" \ "ALL_REGS" \
} }
...@@ -1386,30 +1401,54 @@ enum reg_class ...@@ -1386,30 +1401,54 @@ enum reg_class
This is an initializer for a vector of HARD_REG_SET This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */ of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS \ #define REG_CLASS_CONTENTS \
{ \ { \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ /* NO_REGS. */ \
{ 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ /* BASE_REGS. */ \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ /* GENERAL_REGS. */ \
{ 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ /* FLOAT_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ /* ALTIVEC_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \ /* VSX_REGS. */ \
{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ /* VRSAVE_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ /* VSCR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ /* SPE_ACC_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ /* SPEFSCR_REGS. */ \
{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ /* SPR_REGS. */ \
{ 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
/* NON_SPECIAL_REGS. */ \
{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
/* LINK_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
/* CTR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
/* LINK_OR_CTR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
/* SPECIAL_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
/* SPEC_OR_GEN_REGS. */ \
{ 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
/* CR0_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
/* CR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
/* NON_FLOAT_REGS. */ \
{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
/* CA_REGS. */ \
{ 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
/* SPE_HIGH_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
/* ALL_REGS. */ \
{ 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
} }
/* The same information, inverted: /* The same information, inverted:
...@@ -2348,6 +2387,39 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ ...@@ -2348,6 +2387,39 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[114][0], /* tfhar */ \ &rs6000_reg_names[114][0], /* tfhar */ \
&rs6000_reg_names[115][0], /* tfiar */ \ &rs6000_reg_names[115][0], /* tfiar */ \
&rs6000_reg_names[116][0], /* texasr */ \ &rs6000_reg_names[116][0], /* texasr */ \
\
&rs6000_reg_names[117][0], /* SPE rh0. */ \
&rs6000_reg_names[118][0], /* SPE rh1. */ \
&rs6000_reg_names[119][0], /* SPE rh2. */ \
&rs6000_reg_names[120][0], /* SPE rh3. */ \
&rs6000_reg_names[121][0], /* SPE rh4. */ \
&rs6000_reg_names[122][0], /* SPE rh5. */ \
&rs6000_reg_names[123][0], /* SPE rh6. */ \
&rs6000_reg_names[124][0], /* SPE rh7. */ \
&rs6000_reg_names[125][0], /* SPE rh8. */ \
&rs6000_reg_names[126][0], /* SPE rh9. */ \
&rs6000_reg_names[127][0], /* SPE rh10. */ \
&rs6000_reg_names[128][0], /* SPE rh11. */ \
&rs6000_reg_names[129][0], /* SPE rh12. */ \
&rs6000_reg_names[130][0], /* SPE rh13. */ \
&rs6000_reg_names[131][0], /* SPE rh14. */ \
&rs6000_reg_names[132][0], /* SPE rh15. */ \
&rs6000_reg_names[133][0], /* SPE rh16. */ \
&rs6000_reg_names[134][0], /* SPE rh17. */ \
&rs6000_reg_names[135][0], /* SPE rh18. */ \
&rs6000_reg_names[136][0], /* SPE rh19. */ \
&rs6000_reg_names[137][0], /* SPE rh20. */ \
&rs6000_reg_names[138][0], /* SPE rh21. */ \
&rs6000_reg_names[139][0], /* SPE rh22. */ \
&rs6000_reg_names[140][0], /* SPE rh22. */ \
&rs6000_reg_names[141][0], /* SPE rh24. */ \
&rs6000_reg_names[142][0], /* SPE rh25. */ \
&rs6000_reg_names[143][0], /* SPE rh26. */ \
&rs6000_reg_names[144][0], /* SPE rh27. */ \
&rs6000_reg_names[145][0], /* SPE rh28. */ \
&rs6000_reg_names[146][0], /* SPE rh29. */ \
&rs6000_reg_names[147][0], /* SPE rh30. */ \
&rs6000_reg_names[148][0], /* SPE rh31. */ \
} }
/* Table of additional register names to use in user input. */ /* Table of additional register names to use in user input. */
...@@ -2403,7 +2475,17 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ ...@@ -2403,7 +2475,17 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
/* Transactional Memory Facility (HTM) Registers. */ \ /* Transactional Memory Facility (HTM) Registers. */ \
{"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} } {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
/* SPE high registers. */ \
{"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
{"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
{"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
{"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
{"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
{"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
{"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
{"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
}
/* This is how to output an element of a case-vector that is relative. */ /* This is how to output an element of a case-vector that is relative. */
......
gcc/config/rs6000/rs6000.md
...@@ -56,6 +56,8 @@ ...@@ -56,6 +56,8 @@
(TFHAR_REGNO 114) (TFHAR_REGNO 114)
(TFIAR_REGNO 115) (TFIAR_REGNO 115)
(TEXASR_REGNO 116) (TEXASR_REGNO 116)
(FIRST_SPE_HIGH_REGNO 117)
(LAST_SPE_HIGH_REGNO 148)
]) ])
;; ;;
......
libgcc/ChangeLog
2014-08-04 Rohit <rohitarulraj@freescale.com>
PR target/60102
* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update
based on change in SPE high register numbers and 3 HTM registers.
2014-08-01 Nathan Sidwell <nathan@acm.org> 2014-08-01 Nathan Sidwell <nathan@acm.org>
* Makefile.in (LIBGCOV_MERGE, LIBGCOV_PROFILER, * Makefile.in (LIBGCOV_MERGE, LIBGCOV_PROFILER,
......
libgcc/config/rs6000/linux-unwind.h
...@@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind_Context *context, ...@@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind_Context *context,
#ifdef __SPE__ #ifdef __SPE__
for (i = 14; i < 32; i++) for (i = 14; i < 32; i++)
{ {
fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET;
fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset
= (long) &regs->vregs - new_cfa + 4 * i; = (long) &regs->vregs - new_cfa + 4 * i;
} }
#endif #endif
......
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