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riscv-gcc-1
Commit 113c53c3 by Wilco Dijkstra Committed by Wilco Dijkstra
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[Arm] Cleanup IT attributes 

A recent change to remove the movdi_vfp_cortexa8 meant that ldrd was used in
ITs block even when arm_restrict_it was enabled.  Rather than just fixing this
latent issue, change the default of predicable_short_it to "no" so that only
16-bit instructions need to be marked with it.  As a result there are far fewer
patterns that need the attribute, and omitting predicable_short_it is no longer
causing issues.

	* config/arm/arm.md (predicable_short_it): Change default to "no",
	improve documentation, remove uses that are identical to the default.
	(enabled_for_depr_it): Rename to enabled_for_short_it.
	* gcc/config/arm/arm-fixed.md (predicable_short_it): Remove default uses.
	* gcc/config/arm/ldmstm.md (predicable_short_it): Likewise.
	* gcc/config/arm/sync.md (predicable_short_it): Likewise.
	* gcc/config/arm/thumb2.md (predicable_short_it): Likewise.
	* gcc/config/arm/vfp.md (predicable_short_it): Likewise.

From-SVN: r254463
parent aeed6d61
Showing with 107 additions and 260 deletions
gcc/ChangeLog
2017-11-06 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (predicable_short_it): Change default to "no",
improve documentation, remove uses that are identical to the default.
(enabled_for_depr_it): Rename to enabled_for_short_it.
* gcc/config/arm/arm-fixed.md (predicable_short_it): Remove default uses.
* gcc/config/arm/ldmstm.md (predicable_short_it): Likewise.
* gcc/config/arm/sync.md (predicable_short_it): Likewise.
* gcc/config/arm/thumb2.md (predicable_short_it): Likewise.
* gcc/config/arm/vfp.md (predicable_short_it): Likewise.
2017-11-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/82748
gcc/config/arm/arm-fixed.md
......@@ -35,7 +35,6 @@
"TARGET_INT_SIMD"
"sadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "usadd<mode>3"
......@@ -45,7 +44,6 @@
"TARGET_INT_SIMD"
"uqadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "ssadd<mode>3"
......@@ -55,7 +53,6 @@
"TARGET_INT_SIMD"
"qadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "sub<mode>3"
......@@ -75,7 +72,6 @@
"TARGET_INT_SIMD"
"ssub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "ussub<mode>3"
......@@ -86,7 +82,6 @@
"TARGET_INT_SIMD"
"uqsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "sssub<mode>3"
......@@ -96,7 +91,6 @@
"TARGET_INT_SIMD"
"qsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
;; Fractional multiplies.
......@@ -414,7 +408,6 @@
"TARGET_32BIT && arm_arch6"
"ssat%?\\t%0, #16, %2%S1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "1")
(set_attr "type" "alu_shift_imm")])
......@@ -424,6 +417,5 @@
"TARGET_INT_SIMD"
"usat%?\\t%0, #16, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_imm")]
)
gcc/config/arm/arm.md
......@@ -81,14 +81,17 @@
(const (if_then_else (symbol_ref "TARGET_THUMB1")
(const_string "yes") (const_string "no"))))
; We use this attribute to disable alternatives that can produce 32-bit
; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks
; that contain 32-bit instructions.
(define_attr "enabled_for_depr_it" "no,yes" (const_string "yes"))
; This attribute is used to disable a predicated alternative when we have
; arm_restrict_it.
(define_attr "predicable_short_it" "no,yes" (const_string "yes"))
; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
; The arm_restrict_it flag enables the "short IT" feature which
; restricts IT blocks to a single 16-bit instruction.
; This attribute should only be used on 16-bit Thumb-2 instructions
; which may be predicated (the "predicable" attribute must be set).
(define_attr "predicable_short_it" "no,yes" (const_string "no"))
; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
; This attribute should only be used on instructions which may emit
; an IT block in their expansion which is not a short IT.
(define_attr "enabled_for_short_it" "no,yes" (const_string "yes"))
;; Operand number of an input operand that is shifted. Zero if the
;; given instruction does not shift one of its input operands.
......@@ -229,7 +232,7 @@
(match_test "arm_restrict_it")))
(const_string "no")
(and (eq_attr "enabled_for_depr_it" "no")
(and (eq_attr "enabled_for_short_it" "no")
(match_test "arm_restrict_it"))
(const_string "no")
......@@ -1036,7 +1039,6 @@
"adc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift_imm")
(const_string "alu_shift_reg")))]
......@@ -1136,7 +1138,6 @@
[(set_attr "conds" "use")
(set_attr "arch" "*,a,t2")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
)
......@@ -1666,8 +1667,7 @@
"TARGET_32BIT && arm_arch6"
"mla%?\\t%0, %2, %1, %3"
[(set_attr "type" "mla")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "*mulsi3addsi_compare0"
......@@ -1743,8 +1743,7 @@
"TARGET_32BIT && arm_arch_thumb2"
"mls%?\\t%0, %2, %1, %3"
[(set_attr "type" "mla")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "maddsidi4"
......@@ -1780,8 +1779,7 @@
"TARGET_32BIT && arm_arch6"
"smlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "type" "smlal")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
;; 32x32->64 widening multiply.
......@@ -1818,8 +1816,7 @@
"TARGET_32BIT && arm_arch6"
"smull%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smull")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "umulsidi3"
......@@ -1850,8 +1847,7 @@
"TARGET_32BIT && arm_arch6"
"umull%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "umull")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "umaddsidi4"
......@@ -1887,8 +1883,7 @@
"TARGET_32BIT && arm_arch6"
"umlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "type" "umlal")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "smulsi3_highpart"
......@@ -1932,8 +1927,7 @@
"TARGET_32BIT && arm_arch6"
"smull%?\\t%3, %0, %2, %1"
[(set_attr "type" "smull")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "umulsi3_highpart"
......@@ -1977,8 +1971,7 @@
"TARGET_32BIT && arm_arch6"
"umull%?\\t%3, %0, %2, %1"
[(set_attr "type" "umull")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "mulhisi3"
......@@ -2003,8 +1996,7 @@
"TARGET_DSP_MULTIPLY"
"smultb%?\\t%0, %1, %2"
[(set_attr "type" "smulxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "*mulhisi3bt"
......@@ -2017,8 +2009,7 @@
"TARGET_DSP_MULTIPLY"
"smulbt%?\\t%0, %1, %2"
[(set_attr "type" "smulxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "*mulhisi3tt"
......@@ -2032,8 +2023,7 @@
"TARGET_DSP_MULTIPLY"
"smultt%?\\t%0, %1, %2"
[(set_attr "type" "smulxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "maddhisi4"
......@@ -2046,8 +2036,7 @@
"TARGET_DSP_MULTIPLY"
"smlabb%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
;; Note: there is no maddhisi4ibt because this one is canonical form
......@@ -2062,8 +2051,7 @@
"TARGET_DSP_MULTIPLY"
"smlatb%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "*maddhisi4tt"
......@@ -2078,8 +2066,7 @@
"TARGET_DSP_MULTIPLY"
"smlatt%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "maddhidi4"
......@@ -2093,8 +2080,7 @@
"TARGET_DSP_MULTIPLY"
"smlalbb%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smlalxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
;; Note: there is no maddhidi4ibt because this one is canonical form
(define_insn "*maddhidi4tb"
......@@ -2110,8 +2096,7 @@
"TARGET_DSP_MULTIPLY"
"smlaltb%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smlalxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*maddhidi4tt"
[(set (match_operand:DI 0 "s_register_operand" "=r")
......@@ -2128,8 +2113,7 @@
"TARGET_DSP_MULTIPLY"
"smlaltt%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smlalxy")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
......@@ -2518,7 +2502,6 @@
"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logics_imm")]
)
......@@ -2918,7 +2901,6 @@
"bfc%?\t%0, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
......@@ -2931,7 +2913,6 @@
"bfi%?\t%0, %3, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
......@@ -2986,7 +2967,6 @@
}"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
......@@ -3008,7 +2988,6 @@
}"
[(set_attr "length" "8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
......@@ -3033,7 +3012,6 @@
}"
[(set_attr "length" "8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
......@@ -3044,7 +3022,6 @@
"TARGET_32BIT"
"bic%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg")]
)
......@@ -3078,7 +3055,6 @@
"TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
"bics%?\\t%4, %3, %1%S0"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "conds" "set")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
......@@ -3104,7 +3080,6 @@
"TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
"bics%?\\t%4, %3, %1%S0"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "conds" "set")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
......@@ -3219,7 +3194,6 @@
#"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg,multiple")]
)
......@@ -3419,7 +3393,6 @@
#"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg")]
)
......@@ -3563,7 +3536,6 @@
[(set_attr "length" "8")
(set_attr "ce_count" "2")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
......@@ -3701,7 +3673,6 @@
"TARGET_32BIT"
"bic%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_shift_reg")]
)
......@@ -3712,7 +3683,6 @@
"TARGET_32BIT"
"orr%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_shift_reg")]
)
......@@ -3763,7 +3733,6 @@
"TARGET_32BIT"
"and%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_shift_reg")]
)
......@@ -4000,7 +3969,6 @@
return "usat%?\t%0, %1, %3";
}
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alus_imm")]
)
......@@ -4027,7 +3995,6 @@
return "usat%?\t%0, %1, %4%S3";
}
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "3")
(set_attr "type" "logic_shift_reg")])
......@@ -4278,7 +4245,6 @@
"TARGET_32BIT"
"mvn%?\\t%0, %1%S3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
(set_attr "type" "mvn_shift,mvn_shift_reg")])
......@@ -4554,7 +4520,6 @@
"sbfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
......@@ -4569,7 +4534,6 @@
"ubfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
......@@ -4585,7 +4549,6 @@
sdiv\t%0, %1, %2"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "sdiv")]
)
......@@ -4599,7 +4562,6 @@
udiv\t%0, %1, %2"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "udiv")]
)
......@@ -5377,8 +5339,7 @@
"TARGET_INT_SIMD"
"uxtah%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift_reg")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "zero_extendqisi2"
......@@ -5448,7 +5409,6 @@
"TARGET_INT_SIMD"
"uxtab%?\\t%0, %2, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "alu_shift_reg")]
)
......@@ -5501,7 +5461,6 @@
"tst%?\\t%0, #255"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_imm")]
)
......@@ -5611,8 +5570,7 @@
sxth%?\\t%0, %1
ldrsh%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_insn "*arm_extendhisi2addsi"
......@@ -5716,8 +5674,7 @@
"TARGET_INT_SIMD"
"sxtab%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift_reg")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "extendsfdf2"
......@@ -6084,7 +6041,6 @@
movt\t%0, #:upper16:%c2"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "length" "4")
(set_attr "type" "alu_sreg")]
)
......@@ -6964,8 +6920,7 @@
[(set_attr "conds" "unconditional")
(set_attr "type" "load_4,store_4,mov_reg,multiple")
(set_attr "length" "4,4,4,8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(set_attr "predicable" "yes")]
)
(define_expand "movsf"
......@@ -7018,7 +6973,6 @@
ldr%?\\t%0, %1\\t%@ float
str%?\\t%1, %0\\t%@ float"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "mov_reg,load_4,store_4")
(set_attr "arm_pool_range" "*,4096,*")
(set_attr "thumb2_pool_range" "*,4094,*")
......@@ -7436,7 +7390,7 @@
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "set")
(set_attr "enabled_for_depr_it" "yes,yes,no,*")
(set_attr "enabled_for_short_it" "yes,yes,no,*")
(set_attr "arch" "t2,t2,t2,a")
(set_attr "length" "6,6,10,8")
(set_attr "type" "multiple")]
......@@ -8823,7 +8777,6 @@
"TARGET_32BIT"
"<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "arch" "a,t2")
(set_attr "type" "alu_shift_imm")])
......@@ -8838,7 +8791,6 @@
"TARGET_32BIT && GET_CODE (operands[2]) != MULT"
"<arith_shift_insn>%?\\t%0, %1, %3%S2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "3")
(set_attr "arch" "a,t2,a")
(set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
......@@ -9345,7 +9297,7 @@
}"
[(set_attr "conds" "set")
(set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
(set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
(set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
(set_attr "type" "multiple")
(set_attr_alternative "length"
[(const_int 6)
......@@ -9429,7 +9381,7 @@
}"
[(set_attr "conds" "set")
(set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
(set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
(set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
......@@ -9512,7 +9464,7 @@
[(set_attr "conds" "set")
(set_attr "predicable" "no")
(set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
(set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
(set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
......@@ -9595,7 +9547,7 @@
"
[(set_attr "conds" "set")
(set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
(set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
(set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
......@@ -9643,7 +9595,7 @@
DOM_CC_X_OR_Y),
CC_REGNUM);"
[(set_attr "conds" "clob")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
......@@ -9674,7 +9626,7 @@
(set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
""
[(set_attr "conds" "set")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
......@@ -9707,7 +9659,7 @@
DOM_CC_X_AND_Y),
CC_REGNUM);"
[(set_attr "conds" "clob")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
......@@ -9738,7 +9690,7 @@
(set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
""
[(set_attr "conds" "set")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
......@@ -9925,7 +9877,7 @@
}
"
[(set_attr "conds" "clob")
(set_attr "enabled_for_depr_it" "no,yes,yes")
(set_attr "enabled_for_short_it" "no,yes,yes")
(set_attr "type" "multiple")]
)
......@@ -10543,7 +10495,7 @@
[(set_attr "conds" "use")
(set_attr "length" "4")
(set_attr "arch" "t2,32")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "type" "logic_shift_imm")]
)
......@@ -10589,7 +10541,7 @@
[(set_attr "conds" "use")
(set_attr "length" "4")
(set_attr "arch" "t2,32")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "type" "logic_shift_imm")]
)
......@@ -11325,7 +11277,6 @@
"TARGET_32BIT && arm_arch5"
"clz%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "clz")])
(define_insn "rbitsi2"
......@@ -11334,7 +11285,6 @@
"TARGET_32BIT && arm_arch_thumb2"
"rbit%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "clz")])
;; Keep this as a CTZ expression until after reload and then split
......@@ -11486,7 +11436,6 @@
movt\t%0, %L1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "length" "4")
(set_attr "type" "alu_sreg")]
)
......@@ -11502,7 +11451,6 @@
[(set_attr "arch" "t1,t2,32")
(set_attr "length" "2,2,4")
(set_attr "predicable" "no,yes,yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "rev")]
)
......@@ -11750,8 +11698,7 @@
false, true))"
"ldrd%?\t%0, %3, [%1, %2]"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb2_ldrd_base"
[(set (match_operand:SI 0 "s_register_operand" "=r")
......@@ -11764,8 +11711,7 @@
operands[1], 0, false, true))"
"ldrd%?\t%0, %2, [%1]"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb2_ldrd_base_neg"
[(set (match_operand:SI 0 "s_register_operand" "=r")
......@@ -11778,8 +11724,7 @@
operands[1], -4, false, true))"
"ldrd%?\t%0, %2, [%1, #-4]"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb2_strd"
[(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
......@@ -11795,8 +11740,7 @@
false, false))"
"strd%?\t%2, %4, [%0, %1]"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb2_strd_base"
[(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk"))
......@@ -11809,8 +11753,7 @@
operands[0], 0, false, false))"
"strd%?\t%1, %2, [%0]"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb2_strd_base_neg"
[(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
......@@ -11823,8 +11766,7 @@
operands[0], -4, false, false))"
"strd%?\t%1, %2, [%0, #-4]"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
;; ARMv8 CRC32 instructions.
(define_insn "<crc_variant>"
......
gcc/config/arm/ldmstm.md
......@@ -37,8 +37,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm4_ia"
[(match_parallel 0 "load_multiple_operation"
......@@ -75,8 +74,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmia%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm4_ia_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -110,8 +108,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm4_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -128,8 +125,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmia%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_stm4_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -306,8 +302,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*ldm4_db_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -328,8 +323,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmdb%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm4_db"
[(match_parallel 0 "store_multiple_operation"
......@@ -344,8 +338,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm4_db_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -362,8 +355,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmdb%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
......@@ -485,8 +477,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%?\t%4, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm3_ia"
[(match_parallel 0 "load_multiple_operation"
......@@ -517,8 +508,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmia%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm3_ia_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -547,8 +537,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%?\t%4, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm3_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -563,8 +552,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmia%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_stm3_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -716,8 +704,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%4, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*ldm3_db_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -735,8 +722,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "load_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm3_db"
[(match_parallel 0 "store_multiple_operation"
......@@ -749,8 +735,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%4, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm3_db_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -765,8 +750,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "store_12")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
......@@ -871,8 +855,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldm%?\t%3, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm2_ia"
[(match_parallel 0 "load_multiple_operation"
......@@ -897,8 +880,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmia%?\t%3!, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_ldm2_ia_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -922,8 +904,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%?\t%3, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm2_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -936,8 +917,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmia%?\t%3!, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*thumb_stm2_ia_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -1064,8 +1044,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldmdb%?\t%3, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*ldm2_db_update"
[(match_parallel 0 "load_multiple_operation"
......@@ -1080,8 +1059,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%3!, {%1, %2}"
[(set_attr "type" "load_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm2_db"
[(match_parallel 0 "store_multiple_operation"
......@@ -1092,8 +1070,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stmdb%?\t%3, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "*stm2_db_update"
[(match_parallel 0 "store_multiple_operation"
......@@ -1106,8 +1083,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%3!, {%1, %2}"
[(set_attr "type" "store_8")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
......
gcc/config/arm/sync.md
......@@ -87,8 +87,7 @@
}
}
[(set_attr "arch" "32,v8mb,any")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "atomic_store<mode>"
[(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q")
......@@ -115,8 +114,7 @@
}
}
[(set_attr "arch" "32,v8mb,any")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets
......@@ -127,8 +125,7 @@
VUNSPEC_LDRD_ATOMIC))]
"ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE"
"ldrd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
;; There are three ways to expand this depending on the architecture
;; features available. As for the barriers, a load needs a barrier
......@@ -461,8 +458,7 @@
ldrex<sync_sfx>%?\t%0, %C1
ldrex<sync_sfx>\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
......@@ -475,8 +471,7 @@
ldaex<sync_sfx>%?\\t%0, %C1
ldaex<sync_sfx>\\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
......@@ -488,8 +483,7 @@
ldrex%?\t%0, %C1
ldrex\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
......@@ -501,8 +495,7 @@
ldaex%?\t%0, %C1
ldaex\t%0, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
(define_insn "arm_load_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
......@@ -511,8 +504,7 @@
VUNSPEC_LL))]
"TARGET_HAVE_LDREXD"
"ldrexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
......@@ -521,8 +513,7 @@
VUNSPEC_LAX))]
"TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
"ldaexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_store_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
......@@ -548,8 +539,7 @@
else
return "strex<sync_sfx>%?\t%0, %2, %C1";
}
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_store_release_exclusivedi"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
......@@ -564,8 +554,7 @@
gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
return "stlexd%?\t%0, %2, %H2, %C1";
}
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
[(set_attr "predicable" "yes")])
(define_insn "arm_store_release_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
......@@ -579,5 +568,4 @@
stlex<sync_sfx>%?\t%0, %2, %C1
stlex<sync_sfx>\t%0, %2, %C1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(set_attr "predicable" "yes")])
gcc/config/arm/thumb2.md
......@@ -34,7 +34,6 @@
"TARGET_THUMB2"
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "alu_shift_imm")]
)
......@@ -57,7 +56,7 @@
(match_dup 2)))]
""
[(set_attr "conds" "clob")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "length" "6,6,10")
(set_attr "type" "multiple")]
)
......@@ -78,7 +77,7 @@
(match_dup 2)))]
""
[(set_attr "conds" "clob")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "length" "6,6,10")
(set_attr "type" "multiple")]
)
......@@ -100,7 +99,7 @@
""
[(set_attr "conds" "clob")
(set_attr "length" "6,6,10")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "type" "multiple")]
)
......@@ -121,7 +120,7 @@
""
[(set_attr "conds" "clob")
(set_attr "length" "6,6,10")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "type" "multiple")]
)
......@@ -172,8 +171,7 @@
[(set_attr "conds" "*,clob,clob")
(set_attr "shift" "1")
(set_attr "predicable" "yes,no,no")
(set_attr "predicable_short_it" "no")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "ce_count" "2")
(set_attr "length" "8,6,10")
(set_attr "type" "multiple")]
......@@ -226,8 +224,7 @@
[(set_attr "conds" "*,clob,clob")
(set_attr "shift" "1")
(set_attr "predicable" "yes,no,no")
(set_attr "enabled_for_depr_it" "yes,yes,no")
(set_attr "predicable_short_it" "no")
(set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "ce_count" "2")
(set_attr "length" "8,6,10")
(set_attr "type" "multiple")]
......@@ -354,7 +351,7 @@
(const_int 0)))]
""
[(set_attr "conds" "use")
(set_attr "enabled_for_depr_it" "yes,no")
(set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "8,10")
(set_attr "type" "multiple")]
)
......@@ -504,7 +501,7 @@
DONE;
}
[(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
(set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
(set_attr "enabled_for_short_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
(set_attr "conds" "use")
(set_attr_alternative "type"
[(if_then_else (match_operand 2 "const_int_operand" "")
......@@ -1044,7 +1041,6 @@
ldrsb%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
......@@ -1058,7 +1054,6 @@
ldrh%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
......@@ -1072,7 +1067,6 @@
ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
......@@ -1538,7 +1532,6 @@
"TARGET_THUMB2"
"orn%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg")]
)
......@@ -1551,7 +1544,6 @@
"TARGET_THUMB2"
"orn%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "alu_shift_imm")]
)
......
gcc/config/arm/vfp.md
......@@ -612,7 +612,6 @@
}
"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type"
"f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
......@@ -824,7 +823,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vabs%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
......@@ -834,7 +832,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vabs%?.f64\\t%P0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "ffarithd")]
)
......@@ -846,7 +843,6 @@
vneg%?.f32\\t%0, %1
eor%?\\t%0, %1, #-2147483648"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
......@@ -892,7 +888,6 @@
}
"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "length" "4,4,8")
(set_attr "type" "ffarithd")]
)
......@@ -961,7 +956,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vadd%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
......@@ -972,7 +966,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vadd%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
......@@ -995,7 +988,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vsub%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
......@@ -1006,7 +998,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vsub%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
......@@ -1036,7 +1027,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vdiv%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fdivs")]
)
......@@ -1048,7 +1038,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vdiv%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fdivd")]
)
......@@ -1074,7 +1063,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
......@@ -1085,7 +1073,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
......@@ -1116,7 +1103,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
......@@ -1127,7 +1113,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
......@@ -1139,7 +1124,6 @@
&& !flag_rounding_math"
"vnmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
......@@ -1150,7 +1134,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
......@@ -1178,7 +1161,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
......@@ -1190,7 +1172,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmla%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
......@@ -1214,7 +1195,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
......@@ -1226,7 +1206,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmls%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
......@@ -1250,7 +1229,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
......@@ -1262,7 +1240,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmls%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
......@@ -1289,7 +1266,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
......@@ -1302,7 +1278,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmla%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
......@@ -1340,7 +1315,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
......@@ -1377,7 +1351,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
......@@ -1400,7 +1373,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
......@@ -1424,7 +1396,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
......@@ -1437,7 +1408,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.f32\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
......@@ -1447,7 +1417,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
......@@ -1457,7 +1426,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
"vcvtb%?.f32.f16\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
......@@ -1467,7 +1435,6 @@
"TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
"vcvtb%?.f16.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
......@@ -1477,7 +1444,6 @@
"TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
"vcvtb%?.f64.f16\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
......@@ -1487,7 +1453,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
"vcvtb%?.f16.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
......@@ -1497,7 +1462,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.s32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
......@@ -1507,7 +1471,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.s32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
......@@ -1518,7 +1481,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.u32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
......@@ -1528,7 +1490,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.u32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
......@@ -1539,7 +1500,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.s32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
......@@ -1549,7 +1509,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.s32\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
......@@ -1560,7 +1519,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.u32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
......@@ -1570,7 +1528,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.u32\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
......@@ -1607,7 +1564,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vsqrt%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fsqrts")]
)
......@@ -1618,7 +1574,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vsqrt%?.f64\\t%P0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fsqrtd")]
)
......@@ -1710,7 +1665,6 @@
vcmp%?.f32\\t%0, %1
vcmp%?.f32\\t%0, #0"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
......@@ -1723,7 +1677,6 @@
vcmpe%?.f32\\t%0, %1
vcmpe%?.f32\\t%0, #0"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
......@@ -1736,7 +1689,6 @@
vcmp%?.f64\\t%P0, %P1
vcmp%?.f64\\t%P0, #0"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
......@@ -1749,7 +1701,6 @@
vcmpe%?.f64\\t%P0, %P1
vcmpe%?.f64\\t%P0, #0"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
......@@ -1762,7 +1713,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
......@@ -1781,7 +1731,6 @@
vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
[(set_attr "predicable" "yes")
(set_attr "ce_count" "2")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")
(set_attr "length" "8")]
)
......@@ -1794,7 +1743,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt%?.s32.f32\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
......@@ -1940,7 +1888,6 @@
"TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
[(set_attr "predicable" "<vrint_predicable>")
(set_attr "predicable_short_it" "no")
(set_attr "type" "f_rint<vfp_type>")
(set_attr "conds" "<vrint_conds>")]
)
......@@ -1953,8 +1900,7 @@
"register_operand" "<F_constraint>")] VCVT)))]
"TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
[(set_attr "predicable" "no")
(set_attr "conds" "unconditional")
[(set_attr "conds" "unconditional")
(set_attr "type" "f_cvtf2i")]
)
......
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