Skip to content

R
riscv-gcc-1
Commit 10a88311 by Terry Guo Committed by Xuepeng Guo
Options

* config/arm/cortex-m4.md: Add a new bypass. 

From-SVN: r198021
parent f3d096b0
Showing with 8 additions and 0 deletions
gcc/ChangeLog
2013-04-17 Terry Guo <terry.guo@arm.com>
* config/arm/cortex-m4.md: Add a new bypass.
2013-04-16 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> 2013-04-16 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/aarch64/aarch64.md (*adds_<optab><mode>_multp2): * config/aarch64/aarch64.md (*adds_<optab><mode>_multp2):
......
gcc/config/arm/cortex-m4.md
...@@ -84,6 +84,10 @@ ...@@ -84,6 +84,10 @@
(eq_attr "type" "store4")) (eq_attr "type" "store4"))
"cortex_m4_ex*5") "cortex_m4_ex*5")
(define_bypass 1 "cortex_m4_load1"
"cortex_m4_store1_1,cortex_m4_store1_2"
"arm_no_early_store_addr_dep")
;; If the address of load or store depends on the result of the preceding ;; If the address of load or store depends on the result of the preceding
;; instruction, the latency is increased by one. ;; instruction, the latency is increased by one.
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment