* config/arm/cortex-m4.md: Add a new bypass.

From-SVN: r198021

* config/arm/cortex-m4.md: Add a new bypass.
From-SVN: r198021
10a88311 · Terry Guo · Xuepeng Guo · f3d096b0 · 10a88311 · 10a88311
Commit 10a88311 authored Apr 17, 2013 by Terry Guo Committed by Xuepeng Guo Apr 17, 2013
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gcc/ChangeLog
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gcc/config/arm/cortex-m4.md
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--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
+2013-04-17  Terry Guo  <terry.guo@arm.com>
+
+	* config/arm/cortex-m4.md: Add a new bypass.
+
 2013-04-16   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

 	* config/aarch64/aarch64.md (*adds_<optab><mode>_multp2):

--- a/gcc/config/arm/cortex-m4.md
+++ b/gcc/config/arm/cortex-m4.md
@@ -84,6 +84,10 @@
       (eq_attr "type" "store4"))
  "cortex_m4_ex*5")

+(define_bypass 1 "cortex_m4_load1"
+                 "cortex_m4_store1_1,cortex_m4_store1_2"
+                 "arm_no_early_store_addr_dep")
+
 ;; If the address of load or store depends on the result of the preceding
 ;; instruction, the latency is increased by one.