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lvzhengyang
riscv-gcc-1
Commits
0aaae060
Commit
0aaae060
authored
Jan 06, 2004
by
Jan Hubicka
Committed by
Jan Hubicka
Jan 06, 2004
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* invoke.texi: Remove typo in last change.
From-SVN: r75479
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68f14fb0
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gcc/ChangeLog
View file @
0aaae060
2004-01-06 Jan Hubicka <jh@suse.cz>
2004-01-06 Jan Hubicka <jh@suse.cz>
* invoke.texi: Remove typo in last change.
PR target/10301
PR target/10301
* config.gcc: Accept opteron and athlon-64 as variants
* config.gcc: Accept opteron and athlon-64 as variants
of k8.
of k8.
...
...
gcc/doc/invoke.texi
View file @
0aaae060
...
@@ -8134,7 +8134,7 @@ implemented for this chip.)
...
@@ -8134,7 +8134,7 @@ implemented for this chip.)
@item c3-2
@item c3-2
Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
implemented for this chip.)
implemented for this chip.)
@end table
.
@end table
While picking a specific @var{cpu-type} will schedule things appropriately
While picking a specific @var{cpu-type} will schedule things appropriately
for that particular chip, the compiler will not generate any code that
for that particular chip, the compiler will not generate any code that
...
...
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