mips.h (TARGET_SYNC_AFTER_SC): New macro.

2009-08-04  David Daney  <ddaney@caviumnetworks.com>

	* config/mips/mips.h (TARGET_SYNC_AFTER_SC): New macro.
	* mips_output_sync_loop (mips_output_sync_loop): Only emit
	trailing sync if TARGET_SYNC_AFTER_SC.

From-SVN: r150513

gcc/ChangeLog

+2009-08-04  David Daney  <ddaney@caviumnetworks.com>
+
+	* config/mips/mips.h (TARGET_SYNC_AFTER_SC): New macro.
+	* mips_output_sync_loop (mips_output_sync_loop): Only emit
+	trailing sync if TARGET_SYNC_AFTER_SC.
+
 2009-08-05  David Daney  <ddaney@caviumnetworks.com>
 
 	* gcc/config/mips/sync.md (sync_compare_and_swap<mode>,

gcc/config/mips/mips.c

@@ -10764,9 +10764,17 @@ mips_output_sync_loop (bool barrier_before,
     output_asm_insn ("sync", NULL);
   /* Use branch-likely instructions to work around the LL/SC R10000 errata.  */
   mips_branch_likely = TARGET_FIX_R10000;
-  output_asm_insn (loop, operands);
 
-  return "sync";
+  /* If the target needs a sync after the loop, emit the loop now and
+     return the sync.  */
+
+  if (TARGET_SYNC_AFTER_SC)
+    {
+      output_asm_insn (loop, operands);
+      loop = "sync";
+    }
+ 
+  return loop;
 }
 
 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has

gcc/config/mips/mips.h

@@ -337,7 +337,15 @@ enum mips_code_readable_setting {
    in use.  */
 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
-  
+
+/* False if SC acts as a memory barrier with respect to itself,
+   otherwise a SYNC will be emitted after SC for atomic operations
+   that require ordering between the SC and following loads and
+   stores.  It does not tell anything about ordering of loads and
+   stores prior to and following the SC, only about the SC itself and
+   those loads and stores follow it.  */
+#define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
+
 /* IRIX specific stuff.  */
 #define TARGET_IRIX	   0
 #define TARGET_IRIX6	   0