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Commit 40a4a37b by David Daney Committed by David Daney
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sync.md (sync_compare_and_swap<mode>, [...]): Rewrite calls to mips_output_sync_loop. 

2009-08-05  David Daney  <ddaney@caviumnetworks.com>

	* gcc/config/mips/sync.md (sync_compare_and_swap<mode>,
	compare_and_swap_12, sync_add<mode>, sync_<optab>_12,
	sync_old_<optab>_12, sync_new_<optab>_12, sync_nand_12,
	sync_old_nand_12, sync_new_nand_12, sync_sub<mode>,
	sync_old_add<mode>, sync_old_sub<mode>, sync_new_add<mode>,
	sync_new_sub<mode>, sync_<optab><mode>, sync_old_<optab><mode>,
	sync_new_<optab><mode>, sync_nand<mode>, sync_old_nand<mode>,
	sync_new_nand<mode>, sync_lock_test_and_set<mode>,
	test_and_set_12): Rewrite calls to mips_output_sync_loop.
	* gcc/config/mips/mips-protos.h (mips_output_sync_loop): Make
	the prototype declaration match the definition.
	* gcc/config/mips/mips.c (mips_output_sync_loop):  Emit sync
	instructions explicitly.  Add barrier_before and operands
	parameters.
	* gcc/config/mips/mips.h (MIPS_COMPARE_AND_SWAP,
	MIPS_COMPARE_AND_SWAP_12, MIPS_SYNC_OP, MIPS_SYNC_OP_12,
	MIPS_SYNC_OLD_OP_12, MIPS_SYNC_NEW_OP_12, MIPS_SYNC_OLD_OP,
	MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND,
	MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE,
	MIPS_SYNC_EXCHANGE_12): Remove sync instructions.

From-SVN: r150512
parent 60376e9d
Showing with 130 additions and 100 deletions
gcc/ChangeLog
2009-08-05 David Daney <ddaney@caviumnetworks.com>
* gcc/config/mips/sync.md (sync_compare_and_swap<mode>,
compare_and_swap_12, sync_add<mode>, sync_<optab>_12,
sync_old_<optab>_12, sync_new_<optab>_12, sync_nand_12,
sync_old_nand_12, sync_new_nand_12, sync_sub<mode>,
sync_old_add<mode>, sync_old_sub<mode>, sync_new_add<mode>,
sync_new_sub<mode>, sync_<optab><mode>, sync_old_<optab><mode>,
sync_new_<optab><mode>, sync_nand<mode>, sync_old_nand<mode>,
sync_new_nand<mode>, sync_lock_test_and_set<mode>,
test_and_set_12): Rewrite calls to mips_output_sync_loop.
* gcc/config/mips/mips-protos.h (mips_output_sync_loop): Make
the prototype declaration match the definition.
* gcc/config/mips/mips.c (mips_output_sync_loop): Emit sync
instructions explicitly. Add barrier_before and operands
parameters.
* gcc/config/mips/mips.h (MIPS_COMPARE_AND_SWAP,
MIPS_COMPARE_AND_SWAP_12, MIPS_SYNC_OP, MIPS_SYNC_OP_12,
MIPS_SYNC_OLD_OP_12, MIPS_SYNC_NEW_OP_12, MIPS_SYNC_OLD_OP,
MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND,
MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE,
MIPS_SYNC_EXCHANGE_12): Remove sync instructions.
2009-08-05 Andrew Pinski <pinskia@gmail.com> 2009-08-05 Andrew Pinski <pinskia@gmail.com>
* tree-ssa-alias.c: Fix intervals to use [) syntax. * tree-ssa-alias.c: Fix intervals to use [) syntax.
......
gcc/config/mips/mips-protos.h
...@@ -298,7 +298,7 @@ extern const char *mips_output_load_label (void); ...@@ -298,7 +298,7 @@ extern const char *mips_output_load_label (void);
extern const char *mips_output_conditional_branch (rtx, rtx *, const char *, extern const char *mips_output_conditional_branch (rtx, rtx *, const char *,
const char *); const char *);
extern const char *mips_output_order_conditional_branch (rtx, rtx *, bool); extern const char *mips_output_order_conditional_branch (rtx, rtx *, bool);
extern const char *mips_output_sync_loop (const char *); extern const char *mips_output_sync_loop (bool, const char *, rtx *);
extern const char *mips_output_division (const char *, rtx *); extern const char *mips_output_division (const char *, rtx *);
extern unsigned int mips_hard_regno_nregs (int, enum machine_mode); extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
extern bool mips_linked_madd_p (rtx, rtx); extern bool mips_linked_madd_p (rtx, rtx);
......
gcc/config/mips/mips.c
...@@ -10750,15 +10750,23 @@ mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p) ...@@ -10750,15 +10750,23 @@ mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
return mips_output_conditional_branch (insn, operands, branch[1], branch[0]); return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
} }
/* Return the assembly code for __sync_*() loop LOOP. The loop should support /* Return or emit the assembly code for __sync_*() loop LOOP. The
both normal and likely branches, using %? and %~ where appropriate. */ loop should support both normal and likely branches, using %? and
%~ where appropriate. If BARRIER_BEFORE is true a sync sequence is
emitted before the loop. A sync is always emitted after the loop.
OPERANDS are the insn operands. */
const char * const char *
mips_output_sync_loop (const char *loop) mips_output_sync_loop (bool barrier_before,
const char *loop, rtx *operands)
{ {
if (barrier_before)
output_asm_insn ("sync", NULL);
/* Use branch-likely instructions to work around the LL/SC R10000 errata. */ /* Use branch-likely instructions to work around the LL/SC R10000 errata. */
mips_branch_likely = TARGET_FIX_R10000; mips_branch_likely = TARGET_FIX_R10000;
return loop; output_asm_insn (loop, operands);
return "sync";
} }
/* Return the assembly code for DIV or DDIV instruction DIVISION, which has /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
......
gcc/config/mips/mips.h
...@@ -3144,14 +3144,12 @@ while (0) ...@@ -3144,14 +3144,12 @@ while (0)
and OP is the instruction that should be used to load %3 into a and OP is the instruction that should be used to load %3 into a
register. */ register. */
#define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \ #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
"1:\tll" SUFFIX "\t%0,%1\n" \
"\tbne\t%0,%z2,2f\n" \ "\tbne\t%0,%z2,2f\n" \
"\t" OP "\t%@,%3\n" \ "\t" OP "\t%@,%3\n" \
"\tsc" SUFFIX "\t%@,%1\n" \ "\tsc" SUFFIX "\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)\n" \
"\tsync%-%]%>%)\n" \
"2:\n" "2:\n"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3167,16 +3165,14 @@ while (0) ...@@ -3167,16 +3165,14 @@ while (0)
OPS are the instructions needed to OR %5 with %@. */ OPS are the instructions needed to OR %5 with %@. */
#define MIPS_COMPARE_AND_SWAP_12(OPS) \ #define MIPS_COMPARE_AND_SWAP_12(OPS) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll\t%0,%1\n" \
"1:\tll\t%0,%1\n" \
"\tand\t%@,%0,%2\n" \ "\tand\t%@,%0,%2\n" \
"\tbne\t%@,%z4,2f\n" \ "\tbne\t%@,%z4,2f\n" \
"\tand\t%@,%0,%3\n" \ "\tand\t%@,%0,%3\n" \
OPS \ OPS \
"\tsc\t%@,%1\n" \ "\tsc\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)\n" \
"\tsync%-%]%>%)\n" \
"2:\n" "2:\n"
#define MIPS_COMPARE_AND_SWAP_12_ZERO_OP "" #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
...@@ -3190,13 +3186,11 @@ while (0) ...@@ -3190,13 +3186,11 @@ while (0)
SUFFIX is the suffix that should be added to "ll" and "sc" SUFFIX is the suffix that should be added to "ll" and "sc"
instructions. */ instructions. */
#define MIPS_SYNC_OP(SUFFIX, INSN) \ #define MIPS_SYNC_OP(SUFFIX, INSN) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll" SUFFIX "\t%@,%0\n" \
"1:\tll" SUFFIX "\t%@,%0\n" \
"\t" INSN "\t%@,%@,%1\n" \ "\t" INSN "\t%@,%@,%1\n" \
"\tsc" SUFFIX "\t%@,%0\n" \ "\tsc" SUFFIX "\t%@,%0\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3213,16 +3207,14 @@ while (0) ...@@ -3213,16 +3207,14 @@ while (0)
INSN is already correctly masked -- it instead performs a bitwise INSN is already correctly masked -- it instead performs a bitwise
not. */ not. */
#define MIPS_SYNC_OP_12(INSN, AND_OP) \ #define MIPS_SYNC_OP_12(INSN, AND_OP) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll\t%4,%0\n" \
"1:\tll\t%4,%0\n" \
"\tand\t%@,%4,%2\n" \ "\tand\t%@,%4,%2\n" \
"\t" INSN "\t%4,%4,%z3\n" \ "\t" INSN "\t%4,%4,%z3\n" \
AND_OP \ AND_OP \
"\tor\t%@,%@,%4\n" \ "\tor\t%@,%@,%4\n" \
"\tsc\t%@,%0\n" \ "\tsc\t%@,%0\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
#define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n" #define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n"
#define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n" #define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n"
...@@ -3244,16 +3236,14 @@ while (0) ...@@ -3244,16 +3236,14 @@ while (0)
INSN is already correctly masked -- it instead performs a bitwise INSN is already correctly masked -- it instead performs a bitwise
not. */ not. */
#define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \ #define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll\t%0,%1\n" \
"1:\tll\t%0,%1\n" \
"\tand\t%@,%0,%3\n" \ "\tand\t%@,%0,%3\n" \
"\t" INSN "\t%5,%0,%z4\n" \ "\t" INSN "\t%5,%0,%z4\n" \
AND_OP \ AND_OP \
"\tor\t%@,%@,%5\n" \ "\tor\t%@,%@,%5\n" \
"\tsc\t%@,%1\n" \ "\tsc\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
#define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n" #define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n"
#define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n" #define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n"
...@@ -3273,16 +3263,14 @@ while (0) ...@@ -3273,16 +3263,14 @@ while (0)
INSN is already correctly masked -- it instead performs a bitwise INSN is already correctly masked -- it instead performs a bitwise
not. */ not. */
#define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \ #define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll\t%0,%1\n" \
"1:\tll\t%0,%1\n" \
"\tand\t%@,%0,%3\n" \ "\tand\t%@,%0,%3\n" \
"\t" INSN "\t%0,%0,%z4\n" \ "\t" INSN "\t%0,%0,%z4\n" \
AND_OP \ AND_OP \
"\tor\t%@,%@,%0\n" \ "\tor\t%@,%@,%0\n" \
"\tsc\t%@,%1\n" \ "\tsc\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
#define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n" #define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n"
#define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n" #define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n"
...@@ -3296,13 +3284,11 @@ while (0) ...@@ -3296,13 +3284,11 @@ while (0)
SUFFIX is the suffix that should be added to "ll" and "sc" SUFFIX is the suffix that should be added to "ll" and "sc"
instructions. */ instructions. */
#define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \ #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
"1:\tll" SUFFIX "\t%0,%1\n" \
"\t" INSN "\t%@,%0,%2\n" \ "\t" INSN "\t%@,%0,%2\n" \
"\tsc" SUFFIX "\t%@,%1\n" \ "\tsc" SUFFIX "\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3313,13 +3299,11 @@ while (0) ...@@ -3313,13 +3299,11 @@ while (0)
SUFFIX is the suffix that should be added to "ll" and "sc" SUFFIX is the suffix that should be added to "ll" and "sc"
instructions. */ instructions. */
#define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \ #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
"1:\tll" SUFFIX "\t%0,%1\n" \
"\t" INSN "\t%@,%0,%2\n" \ "\t" INSN "\t%@,%0,%2\n" \
"\tsc" SUFFIX "\t%@,%1\n" \ "\tsc" SUFFIX "\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b%~\n" \ "\tbeq%?\t%@,%.,1b%~\n" \
"\t" INSN "\t%0,%0,%2\n" \ "\t" INSN "\t%0,%0,%2%-%]%>%)"
"\tsync%-%]%>%)"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3329,14 +3313,12 @@ while (0) ...@@ -3329,14 +3313,12 @@ while (0)
instructions. INSN is the and instruction needed to and a register instructions. INSN is the and instruction needed to and a register
with %2. */ with %2. */
#define MIPS_SYNC_NAND(SUFFIX, INSN) \ #define MIPS_SYNC_NAND(SUFFIX, INSN) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll" SUFFIX "\t%@,%0\n" \
"1:\tll" SUFFIX "\t%@,%0\n" \
"\t" INSN "\t%@,%@,%1\n" \ "\t" INSN "\t%@,%@,%1\n" \
"\tnor\t%@,%@,%.\n" \ "\tnor\t%@,%@,%.\n" \
"\tsc" SUFFIX "\t%@,%0\n" \ "\tsc" SUFFIX "\t%@,%0\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3348,14 +3330,12 @@ while (0) ...@@ -3348,14 +3330,12 @@ while (0)
instructions. INSN is the and instruction needed to and a register instructions. INSN is the and instruction needed to and a register
with %2. */ with %2. */
#define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \ #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
"1:\tll" SUFFIX "\t%0,%1\n" \
"\t" INSN "\t%@,%0,%2\n" \ "\t" INSN "\t%@,%0,%2\n" \
"\tnor\t%@,%@,%.\n" \ "\tnor\t%@,%@,%.\n" \
"\tsc" SUFFIX "\t%@,%1\n" \ "\tsc" SUFFIX "\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3367,14 +3347,12 @@ while (0) ...@@ -3367,14 +3347,12 @@ while (0)
instructions. INSN is the and instruction needed to and a register instructions. INSN is the and instruction needed to and a register
with %2. */ with %2. */
#define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \ #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
"%(%<%[%|sync\n" \ "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
"1:\tll" SUFFIX "\t%0,%1\n" \
"\t" INSN "\t%0,%0,%2\n" \ "\t" INSN "\t%0,%0,%2\n" \
"\tnor\t%@,%0,%.\n" \ "\tnor\t%@,%0,%.\n" \
"\tsc" SUFFIX "\t%@,%1\n" \ "\tsc" SUFFIX "\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b%~\n" \ "\tbeq%?\t%@,%.,1b%~\n" \
"\tnor\t%0,%0,%.\n" \ "\tnor\t%0,%0,%.%-%]%>%)"
"\tsync%-%]%>%)"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3391,8 +3369,7 @@ while (0) ...@@ -3391,8 +3369,7 @@ while (0)
"\t" OP "\t%@,%2\n" \ "\t" OP "\t%@,%2\n" \
"\tsc" SUFFIX "\t%@,%1\n" \ "\tsc" SUFFIX "\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
/* Return an asm string that atomically: /* Return an asm string that atomically:
...@@ -3415,8 +3392,7 @@ while (0) ...@@ -3415,8 +3392,7 @@ while (0)
OPS \ OPS \
"\tsc\t%@,%1\n" \ "\tsc\t%@,%1\n" \
"\tbeq%?\t%@,%.,1b\n" \ "\tbeq%?\t%@,%.,1b\n" \
"\tnop\n" \ "\tnop%-%]%>%)"
"\tsync%-%]%>%)"
#define MIPS_SYNC_EXCHANGE_12_ZERO_OP "" #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
#define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n" #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
......
gcc/config/mips/sync.md
...@@ -51,10 +51,12 @@ ...@@ -51,10 +51,12 @@
UNSPEC_COMPARE_AND_SWAP))] UNSPEC_COMPARE_AND_SWAP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "li")); loop = MIPS_COMPARE_AND_SWAP ("<d>", "li");
else else
return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "move")); loop = MIPS_COMPARE_AND_SWAP ("<d>", "move");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "32")]) [(set_attr "length" "32")])
...@@ -84,12 +86,12 @@ ...@@ -84,12 +86,12 @@
UNSPEC_COMPARE_AND_SWAP_12))] UNSPEC_COMPARE_AND_SWAP_12))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return (mips_output_sync_loop loop = MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP);
(MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP)));
else else
return (mips_output_sync_loop loop = MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP);
(MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP))); return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "40,36")]) [(set_attr "length" "40,36")])
...@@ -101,10 +103,12 @@ ...@@ -101,10 +103,12 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addiu")); loop = MIPS_SYNC_OP ("<d>", "<d>addiu");
else else
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addu")); loop = MIPS_SYNC_OP ("<d>", "<d>addu");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -135,8 +139,8 @@ ...@@ -135,8 +139,8 @@
(clobber (match_scratch:SI 4 "=&d"))] (clobber (match_scratch:SI 4 "=&d"))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return (mips_output_sync_loop const char *loop = MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_AND);
(MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_AND))); return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "40")]) [(set_attr "length" "40")])
...@@ -172,8 +176,8 @@ ...@@ -172,8 +176,8 @@
(clobber (match_scratch:SI 5 "=&d"))] (clobber (match_scratch:SI 5 "=&d"))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return (mips_output_sync_loop const char *loop = MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_AND);
(MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_AND))); return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "40")]) [(set_attr "length" "40")])
...@@ -214,8 +218,8 @@ ...@@ -214,8 +218,8 @@
(match_dup 4)] UNSPEC_SYNC_NEW_OP_12))] (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return (mips_output_sync_loop const char *loop = MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_AND);
(MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_AND))); return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "40")]) [(set_attr "length" "40")])
...@@ -246,8 +250,8 @@ ...@@ -246,8 +250,8 @@
(clobber (match_scratch:SI 4 "=&d"))] (clobber (match_scratch:SI 4 "=&d"))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return (mips_output_sync_loop const char *loop = MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR);
(MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR))); return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "40")]) [(set_attr "length" "40")])
...@@ -281,8 +285,8 @@ ...@@ -281,8 +285,8 @@
(clobber (match_scratch:SI 5 "=&d"))] (clobber (match_scratch:SI 5 "=&d"))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return (mips_output_sync_loop const char *loop = MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR);
(MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR))); return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "40")]) [(set_attr "length" "40")])
...@@ -321,8 +325,8 @@ ...@@ -321,8 +325,8 @@
(match_dup 4)] UNSPEC_SYNC_NEW_OP_12))] (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return (mips_output_sync_loop const char *loop = MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR);
(MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR))); return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "40")]) [(set_attr "length" "40")])
...@@ -334,7 +338,8 @@ ...@@ -334,7 +338,8 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>subu")); const char *loop = MIPS_SYNC_OP ("<d>", "<d>subu");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -348,10 +353,12 @@ ...@@ -348,10 +353,12 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addiu")); loop = MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
else else
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addu")); loop = MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -365,7 +372,8 @@ ...@@ -365,7 +372,8 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>subu")); const char *loop = MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -379,10 +387,12 @@ ...@@ -379,10 +387,12 @@
UNSPEC_SYNC_NEW_OP))] UNSPEC_SYNC_NEW_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addiu")); loop = MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
else else
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addu")); loop = MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -396,7 +406,8 @@ ...@@ -396,7 +406,8 @@
UNSPEC_SYNC_NEW_OP))] UNSPEC_SYNC_NEW_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>subu")); const char *loop = MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -408,10 +419,12 @@ ...@@ -408,10 +419,12 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<immediate_insn>")); loop = MIPS_SYNC_OP ("<d>", "<immediate_insn>");
else else
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<insn>")); loop = MIPS_SYNC_OP ("<d>", "<insn>");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -425,11 +438,12 @@ ...@@ -425,11 +438,12 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return (mips_output_sync_loop loop = MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
(MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>")));
else else
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<insn>")); loop = MIPS_SYNC_OLD_OP ("<d>", "<insn>");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -443,11 +457,12 @@ ...@@ -443,11 +457,12 @@
UNSPEC_SYNC_NEW_OP))] UNSPEC_SYNC_NEW_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return (mips_output_sync_loop loop = MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
(MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>")));
else else
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<insn>")); loop = MIPS_SYNC_NEW_OP ("<d>", "<insn>");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "28")]) [(set_attr "length" "28")])
...@@ -457,10 +472,12 @@ ...@@ -457,10 +472,12 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "andi")); loop = MIPS_SYNC_NAND ("<d>", "andi");
else else
return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "and")); loop = MIPS_SYNC_NAND ("<d>", "and");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "32")]) [(set_attr "length" "32")])
...@@ -472,10 +489,12 @@ ...@@ -472,10 +489,12 @@
UNSPEC_SYNC_OLD_OP))] UNSPEC_SYNC_OLD_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "andi")); loop = MIPS_SYNC_OLD_NAND ("<d>", "andi");
else else
return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "and")); loop = MIPS_SYNC_OLD_NAND ("<d>", "and");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "32")]) [(set_attr "length" "32")])
...@@ -487,10 +506,12 @@ ...@@ -487,10 +506,12 @@
UNSPEC_SYNC_NEW_OP))] UNSPEC_SYNC_NEW_OP))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "andi")); loop = MIPS_SYNC_NEW_NAND ("<d>", "andi");
else else
return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "and")); loop = MIPS_SYNC_NEW_NAND ("<d>", "and");
return mips_output_sync_loop (true, loop, operands);
} }
[(set_attr "length" "32")]) [(set_attr "length" "32")])
...@@ -502,10 +523,12 @@ ...@@ -502,10 +523,12 @@
UNSPEC_SYNC_EXCHANGE))] UNSPEC_SYNC_EXCHANGE))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "li")); loop = MIPS_SYNC_EXCHANGE ("<d>", "li");
else else
return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "move")); loop = MIPS_SYNC_EXCHANGE ("<d>", "move");
return mips_output_sync_loop (false, loop, operands);
} }
[(set_attr "length" "24")]) [(set_attr "length" "24")])
...@@ -532,11 +555,11 @@ ...@@ -532,11 +555,11 @@
UNSPEC_SYNC_EXCHANGE_12))] UNSPEC_SYNC_EXCHANGE_12))]
"GENERATE_LL_SC" "GENERATE_LL_SC"
{ {
const char *loop;
if (which_alternative == 0) if (which_alternative == 0)
return (mips_output_sync_loop loop = MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP);
(MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP)));
else else
return (mips_output_sync_loop loop = MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP);
(MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP))); return mips_output_sync_loop (false, loop, operands);
} }
[(set_attr "length" "28,24")]) [(set_attr "length" "28,24")])
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