mips.c
299 KB
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re PR target/16176 (Miscompilation of unaligned data in MIPS backend (SB1 flavor)) · f1526aaaPR target/16176 * config/mips/mips.c (mips_expand_unaligned_load): Use a temporary register for the destination of the lwl or ldl. From-SVN: r83668
Richard Sandiford committed