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macroplacement
Commit d0878691 by Ravi Varadarajan
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Add mempool_goup flows 

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>
parent 4e3c19ba
Showing with 578 additions and 0 deletions
Flows/NanGate45/mempool_group/README.md 0 → 100644
# **Synthesis, Place & Route (SP&R):**
Here we provide the setup to run SP&R of MemPool_tile on NanGate45 using commercial and open-source tools. MemPool tile is part of MemPool which is an open-source many-core system targeting image processing applications. It can be downloaded from [mempool](https://github.com/pulp-platform/mempool) GitHub repo.
### **Using Cadence Innovus:**
All the required scripts to run P\&R are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.
We use an unnamed commercial logic synthesis tool to synthesize the MemPool tile. The synthesized gate-level (standard cells and SRAM macros) netlist is available in [*./netlist/*](./netlist/) directory. We use this netlist for the P&R run.
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the gate-level netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Innovus requires a configuration file to run the macro placement flow. For this we use *proto_design -constraints mp_config.tcl* command. The configuration file [*mp_config.tcl*](./scripts/cadence/mp_config.tcl) is available in the [*./scripts/cadence/*](./scripts/cadence/) directory. Some details of the configuration files are as follows:
1. Provide the memory hierarchy name under the **SEED** section. If you do not provide the memory hierarchy here, then the macro placement constraints (e.g., cell orientation, spacing, etc.) related to that memory may be overlooked.
2. For each macro, valid orientation and spacing rules can be provided under the **MACRO** section. For example, we set valid macro orientation as *R0* for our run, horizontal spacing as *10um*, and vertical spacing as *5um*. Also, when you provide the cell name (ref name, not instance name) add the *isCell=true* option.
Below is the screenshot of the mempool_tile SP\&R databse.
<img src="./screenshots/mempool_tile_Innovus.png" alt="mempool_tile_invs" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
### **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:
1. Copy [*./scripts/OpenROAD/mempool_tile.tar.gz*](./scripts/OpenROAD/mempool_tile.tar.gz) directory to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
2. Use command *tar -xvf mempool_tile.tar.gz* to untar *mempool_tile.tar.gz*. This will generate *mempool_tile* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the below command
```
make DESIGN_CONFIG=./designs/nangate45/mempool_tile/config.mk
```
Below is the screenshot of the mempool_tile SP\&R database.
<img src="./screenshots/mempool_tile_ORFS_SPNR.png" alt="mempool_tile_orfs" width="400"/>
Flows/NanGate45/mempool_group/scripts/cadence/design_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN mempool_group_wrap
set rtldir ../../../../../Testcases/mempool/rtl
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/mempool_group_wrap_fp.def
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
Flows/NanGate45/mempool_group/scripts/cadence/gen_mp_config.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
puts "VERSION 1.0"
set mem_hier ""
foreach a [dbget [dbget top.insts.cell.name fakeram45_* -p2 ].name ] {
regexp {(.*)(/)([^/]*)} $a c b
lappend mem_hier $b
}
set unique_mem_hier [lsort -unique $mem_hier]
puts "BEGIN SEED"
foreach a $unique_mem_hier {
puts "name=$a"
}
puts "END SEED"
puts "BEGIN MACRO"
foreach a [dbget top.insts.cell.name fakeram45_* -u] {
puts "name=$a orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5"
}
puts "END MACRO"
puts "BEGIN CONSTRAINT"
puts "END CONSTRAINT"
Flows/NanGate45/mempool_group/scripts/cadence/lib_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
# lib and lef, RC setup
set libdir "../../../../../Enablements/NanGate45/lib"
set lefdir "../../../../../Enablements/NanGate45/lef"
set_db init_lib_search_path { \
${libdir} \
${lefdir} \
}
set libworst "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_256x32.lib \
${libdir}/fakeram45_64x64.lib \
"
set libbest "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_256x32.lib \
${libdir}/fakeram45_64x64.lib \
"
set lefs "
${lefdir}/NangateOpenCellLibrary.tech.lef \
${lefdir}/NangateOpenCellLibrary.macro.mod.lef \
${lefdir}/fakeram45_256x32.lef \
${lefdir}/fakeram45_64x64.lef \
"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
#set qrc_max "SigCmax/qrcTechFile"
#set qrc_min "SigCmin/qrcTechFile"
Flows/NanGate45/mempool_group/scripts/cadence/mmmc_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax
create_rc_corner -name Cmin
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
Flows/NanGate45/mempool_group/scripts/cadence/mp_config.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
VERSION 1.0
BEGIN SEED
name=i_tile/gen_banks_0__mem_bank
name=i_tile/gen_banks_10__mem_bank
name=i_tile/gen_banks_11__mem_bank
name=i_tile/gen_banks_12__mem_bank
name=i_tile/gen_banks_13__mem_bank
name=i_tile/gen_banks_14__mem_bank
name=i_tile/gen_banks_15__mem_bank
name=i_tile/gen_banks_1__mem_bank
name=i_tile/gen_banks_2__mem_bank
name=i_tile/gen_banks_3__mem_bank
name=i_tile/gen_banks_4__mem_bank
name=i_tile/gen_banks_5__mem_bank
name=i_tile/gen_banks_6__mem_bank
name=i_tile/gen_banks_7__mem_bank
name=i_tile/gen_banks_8__mem_bank
name=i_tile/gen_banks_9__mem_bank
name=i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data
END SEED
BEGIN MACRO
name=fakeram45_64x64 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
name=fakeram45_256x32 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
END MACRO
BEGIN CONSTRAINT
END CONSTRAINT
Flows/NanGate45/mempool_group/scripts/cadence/rtl_list.tcl 0 → 100644
set rtl_all { \
../../../../../Testcases/mempool/rtl/axi/src/axi_pkg.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/cf_math_pkg.sv \
../../../../../Testcases/mempool/rtl/snitch/src/riscv_instr.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_pkg.sv \
../../../../../Testcases/mempool/rtl/mempool_pkg.sv \
../../../../../Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_ipu.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_sram.sv \
../../../../../Testcases/mempool/rtl/axi/src/axi_id_prepend.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/spill_register.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/fall_through_register.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_xbar.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_demux.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_axi_adapter.sv \
../../../../../Testcases/mempool/rtl/axi/src/axi_mux.sv \
../../../../../Testcases/mempool/rtl/axi/src/axi_cut.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/spill_register_flushable.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/fifo_v2.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_demux.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/rr_arb_tree.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/lzc.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/fifo_v3.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter_flushable.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/onehot_to_bin.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_shared_muldiv.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/find_first_one.sv \
../../../../../Testcases/mempool/rtl/common_cells/src/isochronous_spill_register.sv \
../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_clk.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_regfile_ff.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_lsu.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch_onehot.sv \
../../../../../Testcases/mempool/rtl/snitch/src/snitch.sv \
../../../../../Testcases/mempool/rtl/address_scrambler.sv \
../../../../../Testcases/mempool/rtl/axi2mem.sv \
../../../../../Testcases/mempool/rtl/axi_hier_interco.sv \
../../../../../Testcases/mempool/rtl/axi_rab_wrap.sv \
../../../../../Testcases/mempool/rtl/bootrom.sv \
../../../../../Testcases/mempool/rtl/ctrl_registers.sv \
../../../../../Testcases/mempool/rtl/latch_scm.sv \
../../../../../Testcases/mempool/rtl/mempool_cc.sv \
../../../../../Testcases/mempool/rtl/mempool_cluster.sv \
../../../../../Testcases/mempool/rtl/mempool_cluster_wrap.sv \
../../../../../Testcases/mempool/rtl/mempool_group.sv \
../../../../../Testcases/mempool/rtl/mempool_system.sv \
../../../../../Testcases/mempool/rtl/mempool_tile.sv \
../../../../../Testcases/mempool/rtl/snitch_addr_demux.sv \
../../../../../Testcases/mempool/rtl/tcdm_adapter.sv \
../../../../../Testcases/mempool/rtl/tcdm_shim.sv \
}
Flows/NanGate45/mempool_group/scripts/cadence/run 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload innovus
module load innovus/21.1
mkdir -p log
innovus -64 -init run_invs.tcl -log log/run.log
Flows/NanGate45/mempool_group/scripts/cadence/run.sh 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload genus
module load genus/21.1
module unload innovus
module load innovus/21.1
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/NanGate45/mempool_group/scripts/cadence/run_genus.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db init_lib_search_path $libdir
set_db init_hdl_search_path $rtldir
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db auto_ungroup none
set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
}
elaborate $DESIGN
time_info Elaboration
read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/NanGate45/mempool_group/scripts/cadence/run_genus.tcl.old 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set top_module mempool_tile_wrap
set_db max_cpus_per_server 16
set libdir "../../../../../Enablements/NanGate45/lib/"
set libworst "
${libdir}/NangateOpenCellLibrary_typical.lib \
${libdir}/fakeram45_256x32.lib \
${libdir}/fakeram45_64x64.lib \
"
set list_lib "$libworst"
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db auto_ungroup none
set_db init_lib_search_path $libdir
set_db init_hdl_search_path "./rtl/"
set_db library $list_lib
# Start
if {[file exists template]} {
exec rm -rf template
}
exec mkdir template
if {![file exists gate]} {
exec mkdir gate
}
if {![file exists rpt]} {
exec mkdir rpt
}
# Compiler drectives
set compile_effort "high"
set compile_flatten_all 1
set compile_no_new_cells_at_top_level false
# read RTL
source rtl_list.tcl
foreach rtl_file $rtl_all {
if {$top_module == "jpeg_encoder"} {
read_hdl -sv $rtl_file
} else {
read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
}
}
elaborate $top_module
# Default SDC Constraints
read_sdc ./${top_module}.sdc
syn_generic
syn_map
write_sdc > gate/${top_module}.sdc
write_hdl > gate/${top_module}.v
write_script > constraints.g
# Write Reports
redirect [format "%s%s%s" rpt/ $top_module _area.rep] { report_area }
redirect [format "%s%s%s" rpt/ $top_module _cell.rep] { report_gates }
redirect [format "%s%s%s" rpt/ $top_module _timing.rep] { report_timing }
exit
Flows/NanGate45/mempool_group/scripts/cadence/run_invs.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "../../netlist/$DESIGN.v"
set sdc "../../constraints/$DESIGN.sdc"
#set netlist "./syn_handoff/$DESIGN.v"
#set sdc "./syn_handoff/$DESIGN.sdc"
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set rptDir summaryReport/
set encDir enc/
if {![file exists $rptDir/]} {
exec mkdir $rptDir/
}
if {![file exists $encDir/]} {
exec mkdir $encDir/
}
# default settings
set init_pwr_net VDD
set init_gnd_net VSS
# default settings
set init_verilog "$netlist"
set init_design_netlisttype "Verilog"
set init_design_settop 1
set init_top_cell "$DESIGN"
set init_lef_file "$lefs"
# MCMM setup
init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 45
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
globalNetConnect VSS -type pgpin -pin VSS -inst * -override
globalNetConnect VDD -type tiehi -inst * -override
globalNetConnect VSS -type tielo -inst * -override
setOptMode -powerEffort low -leakageToDynamicRatio 0.5
setGenerateViaMode -auto true
generateVias
# basic path groups
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
#setPlaceMode -placeIoPins true
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name Layer_2 -edge 1
createPinBlkg -name Layer_3 -edge 2
createPinBlkg -name Layer_4 -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setPlaceMode -placeIoPins true
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
defOut -netlist -floorplan ${DESIGN}_placed.def
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
create_ccopt_clock_tree_spec
ccopt_design
set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
setNanoRouteMode -routeWithViaInPin "1:1"
setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -dbCheckRule true
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
setDelayCalMode -reset
setDelayCalMode -SIAware true
setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
setAnalysisMode -analysisType onChipVariation -cppr both
# routeOpt
#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
#extractRC
deselectAll
selectNet -clock
reportSelect > summaryReport/clock_net_length.post_route
deselectAll
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
exit
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