Update scripts for mempool_tile

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>

Flows/NanGate45/mempool_tile/scripts/cadence/design_setup.tcl

@@ -2,6 +2,7 @@
 # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
 
 set DESIGN mempool_tile_wrap 
+set rtldir ../../../../../Testcases/mempool/rtl
 set sdc  ../../constraints/${DESIGN}.sdc
 
 # def file with die size and placed IO pins

Flows/NanGate45/mempool_tile/scripts/cadence/rtl_list.tcl

+set rtl_all {  \
+../../../../../Testcases/mempool/rtl/axi/src/axi_pkg.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/cf_math_pkg.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/riscv_instr.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_pkg.sv \
+../../../../../Testcases/mempool/rtl/mempool_pkg.sv \
+../../../../../Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_ipu.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache.sv \
+../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_sram.sv \
+../../../../../Testcases/mempool/rtl/axi/src/axi_id_prepend.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/spill_register.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/fall_through_register.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/stream_xbar.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_demux.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_axi_adapter.sv \
+../../../../../Testcases/mempool/rtl/axi/src/axi_mux.sv \
+../../../../../Testcases/mempool/rtl/axi/src/axi_cut.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/spill_register_flushable.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/fifo_v2.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/stream_demux.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/rr_arb_tree.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/lzc.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/fifo_v3.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/stream_arbiter_flushable.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/onehot_to_bin.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_shared_muldiv.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/deprecated/find_first_one.sv \
+../../../../../Testcases/mempool/rtl/common_cells/src/isochronous_spill_register.sv \
+../../../../../Testcases/mempool/rtl/tech_cells_generic/src/rtl/tc_clk.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_regfile_ff.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_lsu.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch_onehot.sv \
+../../../../../Testcases/mempool/rtl/snitch/src/snitch.sv \
+../../../../../Testcases/mempool/rtl/address_scrambler.sv \
+../../../../../Testcases/mempool/rtl/axi2mem.sv \
+../../../../../Testcases/mempool/rtl/axi_hier_interco.sv \
+../../../../../Testcases/mempool/rtl/axi_rab_wrap.sv \
+../../../../../Testcases/mempool/rtl/bootrom.sv \
+../../../../../Testcases/mempool/rtl/ctrl_registers.sv \
+../../../../../Testcases/mempool/rtl/latch_scm.sv \
+../../../../../Testcases/mempool/rtl/mempool_cc.sv \
+../../../../../Testcases/mempool/rtl/mempool_cluster.sv \
+../../../../../Testcases/mempool/rtl/mempool_cluster_wrap.sv \
+../../../../../Testcases/mempool/rtl/mempool_group.sv \
+../../../../../Testcases/mempool/rtl/mempool_system.sv \
+../../../../../Testcases/mempool/rtl/mempool_tile.sv \
+../../../../../Testcases/mempool/rtl/snitch_addr_demux.sv \
+../../../../../Testcases/mempool/rtl/tcdm_adapter.sv \
+../../../../../Testcases/mempool/rtl/tcdm_shim.sv \
+} 

Flows/NanGate45/mempool_tile/scripts/cadence/run.sh

@@ -7,5 +7,5 @@ module unload innovus
 module load innovus/21.1
 
 mkdir log -p
-#genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
+genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
 innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log

Flows/NanGate45/mempool_tile/scripts/cadence/run_genus.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+set_db init_lib_search_path $libdir
+set_db init_hdl_search_path $rtldir 
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set path
+set_db auto_ungroup none
+
+set_db library $list_lib
+
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+source rtl_list.tcl
+
+foreach rtl_file $rtl_all {
+    read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
+}
+
+elaborate $DESIGN
+time_info Elaboration
+
+read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+