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Commit c272ca46 by sakundu
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Updated flow scripts and def 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent 344f9b3d
Showing with 86 additions and 158 deletions
Flows/NanGate45/ariane133/def/ariane133_fp.def
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Flows/NanGate45/ariane133/rtl/ariane.v
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Flows/NanGate45/ariane133/scripts/cadence/design_setup.tcl
...@@ -3,6 +3,7 @@ ...@@ -3,6 +3,7 @@
set DESIGN ariane set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../../../../Testcases/ariane133/rtl
# #
# DEF file for floorplan initialization # DEF file for floorplan initialization
...@@ -20,3 +21,7 @@ set GEN_EFF medium ...@@ -20,3 +21,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage # Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low # possible values are : high, medium or low
set MAP_EFF high set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/ariane133/scripts/cadence/run.sh 100644 → 100755
File mode changed from 100644 to 100755
Flows/NanGate45/ariane133/scripts/cadence/run_genus_hybrid.tcl
...@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} { ...@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
################################################# #################################################
# Load Design and Initialize # Load Design and Initialize
################################################# #################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl source rtl_list.tcl
foreach rtl_file $rtl_all { foreach rtl_file $rtl_all {
...@@ -90,6 +90,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -90,6 +90,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical syn_generic -physical
} else { } else {
syn_generic syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
} }
time_info GENERIC time_info GENERIC
......
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
...@@ -12,8 +12,6 @@ set handoff_dir "./syn_handoff" ...@@ -12,8 +12,6 @@ set handoff_dir "./syn_handoff"
set netlist ${handoff_dir}/${DESIGN}.v set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc set sdc ${handoff_dir}/${DESIGN}.sdc
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set rptDir summaryReport/ set rptDir summaryReport/
set encDir enc/ set encDir enc/
...@@ -63,7 +61,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -63,7 +61,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
defIn ${handoff_dir}/${DESIGN}.def defIn ${handoff_dir}/${DESIGN}.def
} else { } else {
defIn $floorplan_def defIn $floorplan_def
addHaloToBlock -allMacro 5 5 5 5 addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros place_design -concurrent_macros
refine_macro_place refine_macro_place
} }
...@@ -72,7 +70,7 @@ saveDesign ${encDir}/${DESIGN}_floorplan.enc ...@@ -72,7 +70,7 @@ saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true setFillerMode -fitGap true
setDesignMode -topRoutingLayer 10 setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2 setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place place_opt_design -out_dir $rptDir -prefix place
......
Flows/NanGate45/ariane136/scripts/cadence/design_setup.tcl
...@@ -3,6 +3,7 @@ ...@@ -3,6 +3,7 @@
set DESIGN ariane set DESIGN ariane
set sdc ../../constraints/${DESIGN}.sdc set sdc ../../constraints/${DESIGN}.sdc
set rtldir ../../../../../Testcases/ariane136/rtl
# #
# DEF file for floorplan initialization # DEF file for floorplan initialization
......
Flows/NanGate45/ariane136/scripts/cadence/run_genus_hybrid.tcl
...@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} { ...@@ -53,7 +53,7 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
################################################# #################################################
# Load Design and Initialize # Load Design and Initialize
################################################# #################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl source rtl_list.tcl
foreach rtl_file $rtl_all { foreach rtl_file $rtl_all {
...@@ -90,6 +90,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -90,6 +90,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical syn_generic -physical
} else { } else {
syn_generic syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
} }
time_info GENERIC time_info GENERIC
......
Flows/NanGate45/mempool_tile/def/mempool_tile_wrap_fp.def
...@@ -1306,49 +1306,6 @@ GCELLGRID Y 1797740 DO 2 STEP 2380 ; ...@@ -1306,49 +1306,6 @@ GCELLGRID Y 1797740 DO 2 STEP 2380 ;
GCELLGRID Y 140 DO 643 STEP 2800 ; GCELLGRID Y 140 DO 643 STEP 2800 ;
GCELLGRID Y 0 DO 2 STEP 140 ; GCELLGRID Y 0 DO 2 STEP 140 ;
COMPONENTS 20 ;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance0 fakeram45_64x64
;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance1 fakeram45_64x64
;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance2 fakeram45_64x64
;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance3 fakeram45_64x64
;
- i_tile/gen_banks_0__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_1__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_2__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_3__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_4__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_5__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_6__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_7__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_8__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_9__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_10__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_11__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_12__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_13__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_14__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_15__mem_bank/genblk1_sram_instance fakeram45_256x32
;
END COMPONENTS
PINS 1272 ; PINS 1272 ;
- clk_i + NET clk_i + DIRECTION INPUT + USE SIGNAL - clk_i + NET clk_i + DIRECTION INPUT + USE SIGNAL
+ LAYER metal3 ( -70 0 ) ( 70 140 ) + LAYER metal3 ( -70 0 ) ( 70 140 )
......
Flows/NanGate45/mempool_tile/scripts/cadence/design_setup.tcl
...@@ -6,7 +6,11 @@ set rtldir ../../../../../Testcases/mempool/rtl ...@@ -6,7 +6,11 @@ set rtldir ../../../../../Testcases/mempool/rtl
set sdc ../../constraints/${DESIGN}.sdc set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins # def file with die size and placed IO pins
set floorplan_def ../../def/mempool_tile_wrap_fp.def if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
} else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
# #
# Effort level during optimization in syn_generic -physical (or called generic) stage # Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low # possible values are : high, medium or low
...@@ -15,3 +19,7 @@ set GEN_EFF medium ...@@ -15,3 +19,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage # Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low # possible values are : high, medium or low
set MAP_EFF high set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/mempool_tile/scripts/cadence/lib_setup.tcl
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
set libdir "../../../../../Enablements/NanGate45/lib" set libdir "../../../../../Enablements/NanGate45/lib"
set lefdir "../../../../../Enablements/NanGate45/lef" set lefdir "../../../../../Enablements/NanGate45/lef"
set qrcdir "../../../../../Enablements/NanGate45/qrc"
set_db init_lib_search_path { \ set_db init_lib_search_path { \
${libdir} \ ${libdir} \
...@@ -33,6 +34,5 @@ set lefs " ...@@ -33,6 +34,5 @@ set lefs "
# Ensures proper and consistent library handling between Genus and Innovus # Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true #set_db library_setup_ispatial true
set qrc_max "${qrcdir}/NG45.tch"
#set qrc_max "SigCmax/qrcTechFile" set qrc_min "${qrcdir}/NG45.tch"
#set qrc_min "SigCmin/qrcTechFile"
Flows/NanGate45/mempool_tile/scripts/cadence/run deleted 100644 → 0
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload innovus
module load innovus/21.1
mkdir -p log
innovus -64 -init run_invs.tcl -log log/run.log
Flows/NanGate45/mempool_tile/scripts/cadence/run.sh 100644 → 100755
...@@ -6,6 +6,10 @@ module load genus/21.1 ...@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus module unload innovus
module load innovus/21.1 module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl
...@@ -53,11 +53,11 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} { ...@@ -53,11 +53,11 @@ if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
################################################# #################################################
# Load Design and Initialize # Load Design and Initialize
################################################# #################################################
set_db init_hdl_search_path $rtldir
source rtl_list.tcl source rtl_list.tcl
foreach rtl_file $rtl_all { foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file read_hdl -language sv -define TARGET_SYNTHESIS -define XPULPIMG=1 $rtl_file
} }
elaborate $DESIGN elaborate $DESIGN
...@@ -90,6 +90,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} { ...@@ -90,6 +90,7 @@ if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical syn_generic -physical
} else { } else {
syn_generic syn_generic
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
} }
time_info GENERIC time_info GENERIC
......
Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl
...@@ -7,12 +7,10 @@ source mmmc_setup.tcl ...@@ -7,12 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16 setMultiCpuUsage -localCpu 16
set util 0.3 set util 0.3
set netlist "../../netlist/$DESIGN.v" set handoff_dir "./syn_handoff"
set sdc "../../constraints/$DESIGN.sdc"
#set netlist "./syn_handoff/$DESIGN.v"
#set sdc "./syn_handoff/$DESIGN.sdc"
set site "FreePDK45_38x28_10R_NP_162NW_34O" set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/ set rptDir summaryReport/
set encDir enc/ set encDir enc/
...@@ -58,56 +56,25 @@ generateVias ...@@ -58,56 +56,25 @@ generateVias
createBasicPathGroups -expanded createBasicPathGroups -expanded
## Generate the floorplan ## ## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
#setPlaceMode -placeIoPins true
place_opt_design -out_dir $rptDir -prefix place if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
saveDesign $encDir/${DESIGN}_placed.enc defIn ${handoff_dir}/${DESIGN}.def
} else {
defIn $floorplan_def
addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
## Creating Pin Blcokage for lower and upper pin layers ## saveDesign ${encDir}/${DESIGN}_floorplan.enc
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
createPinBlkg -name Layer_2 -edge 1
createPinBlkg -name Layer_3 -edge 2
createPinBlkg -name Layer_4 -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true setFillerMode -fitGap true
setNanoRouteMode -routeTopRoutingLayer 10 setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setNanoRouteMode -routeBottomRoutingLayer 2 setDesignMode -bottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true
setPlaceMode -placeIoPins true
place_opt_design -out_dir $rptDir -prefix place place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc saveDesign $encDir/${DESIGN}_placed.enc
defOut -netlist -floorplan ${DESIGN}_placed.def
set_ccopt_property post_conditioning_enable_routing_eco 1 set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
...@@ -123,12 +90,10 @@ set_clock_propagation propagated ...@@ -123,12 +90,10 @@ set_clock_propagation propagated
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
# Routing # Routing
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
setNanoRouteMode -routeTopRoutingLayer 10
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -drouteVerboseViolationSummary 1 setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeExpUseAutoVia true setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners ##Recommended by lib owners
# Prevent router modifying M1 pins shapes # Prevent router modifying M1 pins shapes
...@@ -137,7 +102,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1" ...@@ -137,7 +102,6 @@ setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1) ## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1" setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -dbCheckRule true
setNanoRouteMode -drouteAutoStop false setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true setNanoRouteMode -routeExpAdvancedTechnology true
...@@ -145,24 +109,11 @@ setNanoRouteMode -routeExpAdvancedTechnology true ...@@ -145,24 +109,11 @@ setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR #SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def defOut -netlist -floorplan -routing ${DESIGN}_route.def
setDelayCalMode -reset
setDelayCalMode -SIAware true
setExtractRCMode -engine postRoute -coupled true -tQuantusForPostRoute false
setAnalysisMode -analysisType onChipVariation -cppr both
# routeOpt
#optDesign -postRoute -setup -hold -prefix postRoute -expandedViews
#extractRC
deselectAll
selectNet -clock
reportSelect > summaryReport/clock_net_length.post_route
deselectAll
summaryReport -noHtml -outfile summaryReport/post_route.sum summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def defOut -netlist -floorplan -routing ${DESIGN}.def
......
Flows/NanGate45/nvdla/scripts/cadence/design_setup.tcl
...@@ -2,12 +2,15 @@ ...@@ -2,12 +2,15 @@
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators. # We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN NV_NVDLA_partition_c set DESIGN NV_NVDLA_partition_c
set rtldir ../../../../../Testcases/nvdla/rtl
set sdc ../../constraints/${DESIGN}.sdc set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins # def file with die size and placed IO pins
set floorplan_def ../../def/${DESIGN}_fp.def if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set floorplan_def ../../def/${DESIGN}_fp_placed_macros.def
set rtl_path ../../../../../Testcases/nvdla/rtl/ } else {
set floorplan_def ../../def/${DESIGN}_fp.def
}
# #
# Effort level during optimization in syn_generic -physical (or called generic) stage # Effort level during optimization in syn_generic -physical (or called generic) stage
...@@ -17,3 +20,7 @@ set GEN_EFF medium ...@@ -17,3 +20,7 @@ set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage # Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low # possible values are : high, medium or low
set MAP_EFF high set MAP_EFF high
#
set SITE "FreePDK45_38x28_10R_NP_162NW_34O"
set HALO_WIDTH 5
set TOP_ROUTING_LAYER 10
Flows/NanGate45/nvdla/scripts/cadence/rtl_list.tcl
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
+libext+.gv +libext+.gv
+define+DISABLE_TESTPOINTS +define+DISABLE_TESTPOINTS
+define+NV_SYNTHESIS +define+NV_SYNTHESIS
+define+SYNTHESIS
//+define+RAM_INTERFACE //+define+RAM_INTERFACE
NV_nvdla.v NV_nvdla.v
...@@ -371,7 +372,7 @@ nv_ram_rwsthp_80x15.v ...@@ -371,7 +372,7 @@ nv_ram_rwsthp_80x15.v
nv_ram_rwsthp_80x17.v nv_ram_rwsthp_80x17.v
nv_ram_rwsthp_80x72.v nv_ram_rwsthp_80x72.v
nv_ram_rwsthp_80x9.v nv_ram_rwsthp_80x9.v
fakeram_256x64_dp.v fakeram45_256x64_dp.v
-v NV_NVDLA_XXIF_libs.v -v NV_NVDLA_XXIF_libs.v
Flows/NanGate45/nvdla/scripts/cadence/run.sh 100644 → 100755
...@@ -6,6 +6,10 @@ module load genus/21.1 ...@@ -6,6 +6,10 @@ module load genus/21.1
module unload innovus module unload innovus
module load innovus/21.1 module load innovus/21.1
#
# To run the Physical Synthesis (iSpatial) flow - flow2
export PHY_SYNTH=1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus_hybrid.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log innovus -64 -overwrite -log log/innovus.log -files run_invs.tcl
Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
...@@ -7,10 +7,10 @@ source mmmc_setup.tcl ...@@ -7,10 +7,10 @@ source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16 setMultiCpuUsage -localCpu 16
set util 0.3 set util 0.3
set netlist "./syn_handoff/$DESIGN.v" set handoff_dir "./syn_handoff"
set sdc "./syn_handoff/$DESIGN.sdc"
set site "FreePDK45_38x28_10R_NP_162NW_34O" set netlist ${handoff_dir}/${DESIGN}.v
set sdc ${handoff_dir}/${DESIGN}.sdc
set rptDir summaryReport/ set rptDir summaryReport/
set encDir enc/ set encDir enc/
...@@ -56,26 +56,21 @@ generateVias ...@@ -56,26 +56,21 @@ generateVias
createBasicPathGroups -expanded createBasicPathGroups -expanded
## Generate the floorplan ## ## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 5 5 5 5
place_design -concurrent_macros
refine_macro_place
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ## if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0 defIn ${handoff_dir}/${DESIGN}.def
createPinBlkg -name side_top -edge 1 } else {
createPinBlkg -name side_right -edge 2 defIn $floorplan_def
createPinBlkg -name side_bottom -edge 3 addHaloToBlock -allMacro $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH $HALO_WIDTH
place_design -concurrent_macros
refine_macro_place
}
saveDesign ${encDir}/${DESIGN}_floorplan.enc
setPlaceMode -place_detail_legalization_inst_gap 1 setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true setFillerMode -fitGap true
setDesignMode -topRoutingLayer 10 setDesignMode -topRoutingLayer $TOP_ROUTING_LAYER
setDesignMode -bottomRoutingLayer 2 setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place place_opt_design -out_dir $rptDir -prefix place
......
Flows/SKY130HD/ariane133/rtl/ariane.v
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Flows/SKY130HD/ariane133/scripts/cadence/run.sh
...@@ -7,5 +7,5 @@ module unload innovus ...@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1 module load innovus/21.1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/SKY130HD/ariane136/scripts/cadence/run.sh 100644 → 100755
...@@ -7,5 +7,5 @@ module unload innovus ...@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1 module load innovus/21.1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/SKY130HD/nvdla/scripts/cadence/run.sh
...@@ -7,5 +7,5 @@ module unload innovus ...@@ -7,5 +7,5 @@ module unload innovus
module load innovus/21.1 module load innovus/21.1
mkdir log -p mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Testcases/README.md
...@@ -5,3 +5,5 @@ Testcases currently include the following designs. ...@@ -5,3 +5,5 @@ Testcases currently include the following designs.
- [133 macro version](./ariane133/): The netlist of the 136-macro version is modified to generate the Ariane design with 133 macros. This is explained [here](./ariane133/). - [133 macro version](./ariane133/): The netlist of the 136-macro version is modified to generate the Ariane design with 133 macros. This is explained [here](./ariane133/).
- [MemPool](https://github.com/pulp-platform/mempool): The MemPool design is downloaded from the [mempool](https://github.com/pulp-platform/mempool) GitHub repository. - [MemPool](https://github.com/pulp-platform/mempool): The MemPool design is downloaded from the [mempool](https://github.com/pulp-platform/mempool) GitHub repository.
- [tile](./mempool_tile/): MemPool tile is part of MemPool which is an open-source many-core system. - [tile](./mempool_tile/): MemPool tile is part of MemPool which is an open-source many-core system.
- [NVDLA](https://github.com/nvdla/hw/tree/nv_small): The NVDLA design is downloaded from the [nvdla/hw](https://github.com/nvdla/hw/tree/nv_small) GitHub repository.
- [NVDLA nv_small](./nvdla/): We compile the RTL using the nv_small.spec available in the [nvdla/hw](https://github.com/nvdla/hw/tree/nv_small) GitHub repository. Only partition *c* has the memory macros, so we run all our flow only for partition *c*.
Testcases/ariane133/rtl/ariane.v
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