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Commit c148f72d by sakundu
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Added report generation scripts, Updated sdc 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent f763a5d7
Showing with 163 additions and 24 deletions
Flows/ASAP7/ariane133/scripts/cadence/run_invs.tcl
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
......@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -87,6 +93,11 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -112,6 +123,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/ASAP7/ariane136/scripts/cadence/run_invs.tcl
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
......@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -87,6 +93,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -112,6 +122,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/ASAP7/mempool_tile/scripts/cadence/run_invs.tcl
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
......@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -87,6 +93,11 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -112,6 +123,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc
......@@ -12,11 +12,11 @@ set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
set_ideal_network [get_ports test_mode]
create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45}
set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
create_clock [get_ports nvdla_core_clk] -period 900.0 -waveform {0 450.0}
set_clock_transition -max -rise 50 [get_clocks nvdla_core_clk]
set_clock_transition -max -fall 50 [get_clocks nvdla_core_clk]
set_clock_transition -min -rise 50 [get_clocks nvdla_core_clk]
set_clock_transition -min -fall 50 [get_clocks nvdla_core_clk]
set_false_path -from [get_ports direct_reset_]
set_false_path -from [get_ports dla_reset_rstn]
set_false_path -from [get_ports test_mode]
......
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
setLibraryUnit -time 1.0ps
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
......@@ -76,6 +77,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -87,6 +93,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -112,6 +122,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/NanGate45/ariane133/scripts/cadence/run_invs.tcl
......@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/NanGate45/ariane136/scripts/cadence/run_invs.tcl
......@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/NanGate45/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl
......@@ -75,6 +75,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -86,6 +91,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -111,6 +120,8 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/SKY130HD/ariane133/constraints/ariane.sdc
#period set in nano-seconds - currently: 4ns = 250 MHz freq
create_clock [get_ports clk_i] -name core_clock -period 4
create_clock [get_ports clk_i] -name core_clock -period 6
Flows/SKY130HD/ariane133/scripts/cadence/run_invs.tcl
......@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/SKY130HD/ariane136/constraints/ariane.sdc
# ####################################################################
# Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Fri Jul 01 20:44:40 PDT 2022
# ####################################################################
set sdc_version 2.0
set_units -capacitance 1000fF
set_units -time 1000ps
# Set the current design
current_design ariane
create_clock -name "core_clock" -period 8.0 -waveform {0.0 4.0} [get_ports clk_i]
set_clock_gating_check -setup 0.0
set_wire_load_mode "top"
#period set in nano-seconds - currently: 4ns = 250 MHz freq
create_clock [get_ports clk_i] -name core_clock -period 6
Flows/SKY130HD/ariane136/scripts/cadence/run_invs.tcl
......@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/SKY130HD/mempool_tile/scripts/cadence/run_invs.tcl
......@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
Flows/SKY130HD/nvdla/constraints/NV_NVDLA_partition_c.sdc
......@@ -12,7 +12,7 @@ set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
set_ideal_network [get_ports test_mode]
create_clock [get_ports nvdla_core_clk] -period 6.0 -waveform {0 3.0}
create_clock [get_ports nvdla_core_clk] -period 5.0 -waveform {0 2.5}
set_clock_transition -max -rise 0.15 [get_clocks nvdla_core_clk]
set_clock_transition -max -fall 0.15 [get_clocks nvdla_core_clk]
set_clock_transition -min -rise 0.15 [get_clocks nvdla_core_clk]
......
Flows/SKY130HD/nvdla/scripts/cadence/run_invs.tcl
......@@ -74,6 +74,11 @@ setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
echo "stage,core_area,standard_cell_area,macro_area,total_power,wire_length,wns,tns,h_c,v_c" > ${DESIGN}_DETAILS.rpt
source ../../../../util/extract_report.tcl
set rpt_pre_cts [extract_report preCTS]
echo "$rpt_pre_cts" >> ${DESIGN}_DETAILS.rpt
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
......@@ -85,6 +90,10 @@ set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
saveDesign $encDir/${DESIGN}_cts.enc
set rpt_post_cts [extract_report postCTS]
echo "$rpt_post_cts" >> ${DESIGN}_DETAILS.rpt
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
......@@ -110,6 +119,10 @@ setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
set rpt_post_route [extract_report postRoute]
echo "$rpt_post_route" >> ${DESIGN}_DETAILS.rpt
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
......
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