Update sdc for mempool_tile NG45

Signed-off-by: Ravi Varadarajan <rvaradarajan@ucsd.edu>

Flows/NanGate45/mempool_tile/constraints/mempool_tile.sdc

 set sdc_version 2.0
 set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
 
-set clock_cycle 4
+set clock_cycle 6.8
 set uncertainty 0.08
 set io_delay 0
 set maxFanout 16
@@ -11,8 +11,8 @@ set clock_port_mempool_tile clk_i
 
 create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
 set_clock_uncertainty $uncertainty [all_clocks]
-set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
-set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
+#set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
+#set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
 set_max_transition $maxTransition -clock_path [get_clocks clk_i]
 set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
 #set_propagated_clock [get_clocks clk_i]
@@ -20,7 +20,7 @@ set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
 
 # Create virtual clock.
 create_clock -name "vclk_i" -period $clock_cycle
-set_clock_uncertainty $clk_uncertainty [get_clocks vclk_i]
+set_clock_uncertainty $uncertainty [get_clocks vclk_i]
 set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
 set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
 
@@ -34,26 +34,26 @@ set_max_fanout $maxFanout [current_design]
 set_false_path -from tile_id_i
 
 # TCDM Master
-set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_master_*req_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*req_*"]
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*req_*"]
 
-set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_master_*resp_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_master_*resp_*"]
+set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_master_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_master_*resp_*"]
 
 # TCDM Slave
-set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_slave_*req_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*req_*"]
+set_input_delay  [expr 0.65*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*req_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*req_*"]
 
-set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ tcdm_slave_*resp_*"] 
-set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ tcdm_slave_*resp_*"]
+set_input_delay  [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ tcdm_slave_*resp_*"] 
+set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ tcdm_slave_*resp_*"]
 
 # Refill port
-set_input_delay  [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "hierarchical_name =~ refill_*"] 
-set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "hierarchical_name =~ refill_*"]
+#set_input_delay  [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_inputs]  "name =~ refill_*"] 
+#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [filter_collection [all_outputs] "name =~ refill_*"]
 
 # Reset
 set_input_delay  [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
 
 # Critical range
 # Depending on the synthesis tool used, this can be helpful.
-set_critical_range 0.100 [current_design]
+#set_critical_range 0.100 [current_design]

Flows/NanGate45/mempool_tile/constraints/mempool_tile_wrap.sdc

 set sdc_version 2.0
 set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
 
-set clock_cycle 4
+set clock_cycle 6.8
 set uncertainty 0.08
 set io_delay 0
 set maxFanout 16
@@ -11,9 +11,9 @@ set clock_port_mempool_tile clk_i
 
 create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
 set_clock_uncertainty $uncertainty [all_clocks]
-set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
-set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
-set_max_transition $maxTransition -clock_path [get_clocks clk_i]
+#set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
+#set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
+#set_max_transition $maxTransition -clock_path [get_clocks clk_i]
 set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
 #set_propagated_clock [get_clocks clk_i]