-[RTL files for Ariane design with 136 macros](./Testcases/ariane136/) version is generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
-[RTL files for Ariane designs with 133 macros](./Testcases/ariane133/) version is generated by updating the memory connection of 136 macro version.
-[RTL files for Ariane design with 136 macros](./Testcases/ariane136/), which are generated by instantiating 16-bit memories in Ariane netlist availabe in [lowRISC](https://github.com/lowRISC/ariane) GitHub repository.
-[RTL files for Ariane designs with 133 macros](./Testcases/ariane133/), which are generated by updating the memory connection of 136 macro version.
- MemPool (RTL)
-[RTL files for Mempool tile design](./Testcases/mempool_tile/)
- RTL files for Mempool group design
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@@ -64,16 +64,10 @@ We will rectify such errors as soon as possible after being made aware of them.
-[Gridding](./CodeElements/Gridding/) determines a dissection of the layout canvas into some number of rows (n_rows) and some number of columns (n_cols) of gridcells. In Circuit Training, the purpose of gridding is to control the size of the macro placement solution space,
thus allowing RL to train within reasonable runtimes. Gridding enables hard macros to find locations consistent with high solution quality,
while allowing soft macros (standard-cell clusters) to also find good locations.
-[Grouping](./CodeElements/Grouping/) ensureS that closely-related logic is kept close to hard macros and to clumps of IOs. The clumps of IOs are induced by IO locations with respect to the row and column coordinates in the gridded layout canvas.
-[Hypergraph clustering](./CodeElements/Clustering/) clusters millions of standard cells into a few thousand clusters. In Circuit Training, the purpose of clustering is to generate an approximate but fast standard cell placement that facilitates policy networks.
-[Force-directed placement](./CodeElements/FDPlacement/) places the center of each standard cell cluster onto centers of gridcells generated by [Gridding](./CodeElements/Gridding/).
-[Simulated annealing](./CodeElements/SimulatedAnnealing/) places the center of each macro onto centers of gridcells generated by [Gridding](./CodeElements/Gridding/). In Circuit Training, simulated annealing is used as a baseline to show the relative sample efficiency of RL.
-[LEF/DEF and Bookshelf (OpenDB, RosettaStone) translators](./CodeElements/FormatTranslators/) ease the translation between different representations of the same netlist.
