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Commit 5d3cbda9 by sakundu
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Added NVDLA details and updated the README 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent 6f2cd19a
Showing with 1248 additions and 89 deletions
Enablements/ASAP7/lib/sram_asap7_64x256_1rw.lib
......@@ -2,7 +2,7 @@ library(sram_asap7_64x256_1rw) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-06-13 17:29:18Z";
date : "2022-07-02 07:14:59Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
......@@ -383,77 +383,6 @@ cell(sram_asap7_64x256_1rw) {
}
}
}
bus(w_mask_in) {
bus_type : sram_asap7_64x256_1rw_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
internal_power(){
when : "(we_in)";
rise_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
}
cell_leakage_power : 128.900;
}
......
Enablements/SKY130HD/README.md
# SKY130HD FakeStack (SKY130HD library, bsg_fakeram memory generation, 9M FkaeStack)
The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases. In this enablement each of the five routing layers and four cut layers has different lef properties (.e.g, minimum spacing, width, enclosure, etc.).
The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases.
Consider the five metal stacks are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as our one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x1Ma_x2Mb_x3Mc_x4Md_1Me, where xi is greater or equal to one.
In this enablement each of the five routing layers and four cut layers has different lef properties (.e.g, minimum spacing, width, enclosure, etc.). Consider the five layrs of the metal stack are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as our one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x<sub>1</sub>Ma_x<sub>2</sub>Mb_x<sub>3</sub>Mc_x<sub>4</sub>Md_1Me, where x<sub>i</sub> is greater or equal to one.
We use the bsg_fakeram memory generator available in the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) GitHub repo to generate the required SRAMs. The [sky130hd.cfg](./util/sky130hd.cfg) is the configuration file used to generate all the required memories.
......
Flows/ASAP7/nvdla/README.md 0 → 100644
# **Synthesis, Place \& Route (SP\&R):**
Here we provide the setup to run SP&R of NVDLA design with 128 memory macros on ASAP7 using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
## **SP\&R Flow:**
We implement [NVDLA](../../../Testcases/nvdla/) on the ASAP7 platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/asap7). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the ASAP7 platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/ASAP7*](../../../Enablements/ASAP7/) directory.
### **Using Cadence Genus and Innovus:**
All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.
**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
```
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
```
We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow.
<img src="./screenshots/nvdla_Innovus_asap7.png" alt="nvdla_cadence" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
<!--
### **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:
1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the below command
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
```
4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.
<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
-->
\ No newline at end of file
Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc 0 → 100644
# ===================================================================
# File: syn/cons/NV_NVDLA_partition_c.sdc
# NVDLA Open Source Project
#
# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the
# NVDLA Open Hardware License; see the "LICENSE.txt" file that came
# with this distribution for more information.
# ===================================================================
set_max_area 0
set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
set_ideal_network [get_ports test_mode]
create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45}
set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
set_false_path -from [get_ports direct_reset_]
set_false_path -from [get_ports dla_reset_rstn]
set_false_path -from [get_ports test_mode]
set_false_path -from [get_ports pwrbus_ram_pd*]
set_false_path -from [get_ports tmc2slcg_disable_clock_gating]
set_false_path -from [get_ports global_clk_ovr_on]
set_false_path -from [get_ports nvdla_clk_ovr_on]
Flows/ASAP7/nvdla/def/NV_NVDLA_partition_c_fp.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/nvdla/scripts/cadence/design_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN NV_NVDLA_partition_c
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/${DESIGN}_fp.def
set rtl_path ../../../../../Testcases/nvdla/rtl/
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
Flows/ASAP7/nvdla/scripts/cadence/gen_mp_config.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
puts "VERSION 1.0"
set mem_hier ""
foreach a [dbget [dbget top.insts.cell.name fakeram45_* -p2 ].name ] {
regexp {(.*)(/)([^/]*)} $a c b
lappend mem_hier $b
}
set unique_mem_hier [lsort -unique $mem_hier]
puts "BEGIN SEED"
foreach a $unique_mem_hier {
puts "name=$a util=$util"
}
puts "END SEED"
puts "BEGIN MACRO"
foreach a [dbget top.insts.cell.name fakeram45_* -u] {
puts "name=$a orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5"
}
puts "END MACRO"
puts "BEGIN CONSTRAINT"
puts "END CONSTRAINT"
Flows/ASAP7/nvdla/scripts/cadence/lib_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
# lib and lef, RC setup
set libdir "../../../../../Enablements/ASAP7/lib"
set lefdir "../../../../../Enablements/ASAP7/lef"
set qrcdir "../../../../../Enablements/ASAP7/qrc"
set_db init_lib_search_path { \
${libdir} \
${lefdir} \
}
set libworst [glob ${libdir}/*.lib]
set libbest $libworst
set lefs "
${lefdir}/asap7_tech_1x_201209.lef \
${lefdir}/asap7sc7p5t_27_R_1x_201211.lef \
${lefdir}/sram_asap7_64x256_1rw.lef \
"
set qrc_max "${qrcdir}/ASAP7.tch"
set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
Flows/ASAP7/nvdla/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/ASAP7/nvdla/scripts/cadence/mmmc_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
Flows/ASAP7/nvdla/scripts/cadence/mp_config.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
##########################################
# Masterplan User Constraint File Template
##########################################
###########################################################
# Syntax Convention: #
# [] means optional #
# <> means filling with real value or name in your design #
# () indicates the unit name for your value #
# | means OR #
# {} is used to enclose a group of names (one or more) #
# ... means more similar items #
###########################################################
###########################################################
# Version section (required on and after Innovus 10.1) #
# If not provided, will be parsed as older format #
# VERSION <N.N> #
# For example: #
###########################################################
VERSION 1.0
######################################################################
# Seed Section (optional) : one single line per seed #
# name=<seedName> [util=<float>] [createFence=true]\ #
# [minWHRatio=<float>] [maxWHRatio=<float>]\ #
# [minFenceToFenceSpace=<(um)>] [minFenceToCoreSpace=<(um)>]\ #
# [minFenceToInsideMacroSpace=<(um)>]\ #
# [minFenceToOutsideMacroSpace=<(um)>]\ #
# [minInsideFenceMacroToMacroSpace=<(um)>]\ #
# [master=<nameOrOtherName>] [cloneOrient={R0|MX|MY|R180}] #
# For example: #
######################################################################
BEGIN SEED
name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_0__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_1__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_2__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_3__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_0__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_1__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_2__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_3__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_4__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_5__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_6__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_7__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/valid_dirty_sram/genblk1_0__i_ram
END SEED
######################################################################
# MACRO section syntax : one single line per macro #
# name=<InstOrCell> [minLeftSpace=<(um)>] [minRightSpace=<(um)>]\ #
# [minTopSpace=<(um)>] [minBottomSpace=<(um)>]\ #
# [orient={R0|MX|MY|R180|MX90|R90|R270|MY90}]\ #
# [isCell=true] [minMacroToCoreSpace=<(um)>] #
# For example: #
######################################################################
BEGIN MACRO
name=fakeram45_256x16 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
END MACRO
#################################################################################
# relative placement CONSTRAINT section syntax #
# name=<HInstOrGroupOrHM> loc=<T|B|R|L|TL|TR|BL|BR|(x,y)> #
# name=<NewName> members={<Module1> <Module2> <Module3>..} [strength=Soft|Hard] #
# For example: #
#################################################################################
BEGIN CONSTRAINT
END CONSTRAINT
Flows/ASAP7/nvdla/scripts/cadence/rtl_list.tcl 0 → 100644
#-y nv_small/src
#+incdir+nv_small/src
+libext+.v
+libext+.sv
+libext+.gv
+define+DISABLE_TESTPOINTS
+define+NV_SYNTHESIS
//+define+RAM_INTERFACE
NV_nvdla.v
NV_NVDLA_apb2csb.v
NV_NVDLA_partition_c.v
NV_NVDLA_partition_a.v
NV_NVDLA_partition_p.v
NV_NVDLA_partition_o.v
NV_NVDLA_partition_m.v
NV_NVDLA_CFGROM_rom.v
NV_NVDLA_sync3d.v
NV_NVDLA_cfgrom.v
NV_NVDLA_glb.v
NV_NVDLA_core_reset.v
NV_NVDLA_sync3d_s.v
NV_NVDLA_mcif.v
NV_NVDLA_cdp.v
NV_NVDLA_csb_master.v
NV_NVDLA_pdp.v
NV_NVDLA_reset.v
NV_NVDLA_PDP_rdma.v
NV_NVDLA_CDP_rdma.v
NV_NVDLA_CDP_DP_nan.v
NV_NVDLA_PDP_slcg.v
NV_NVDLA_PDP_core.v
NV_NVDLA_CDP_slcg.v
NV_NVDLA_MCIF_csb.v
NV_NVDLA_PDP_nan.v
NV_NVDLA_CDP_wdma.v
NV_NVDLA_PDP_wdma.v
NV_NVDLA_PDP_reg.v
NV_NVDLA_GLB_ic.v
NV_NVDLA_CDP_reg.v
NV_NVDLA_GLB_csb.v
NV_NVDLA_CDP_dp.v
NV_NVDLA_MCIF_read.v
NV_NVDLA_MCIF_write.v
NV_NVDLA_MCIF_CSB_reg.v
NV_NVDLA_MCIF_WRITE_ig.v
NV_NVDLA_MCIF_READ_ig.v
NV_NVDLA_MCIF_WRITE_cq.v
NV_NVDLA_MCIF_READ_eg.v
NV_NVDLA_MCIF_WRITE_eg.v
NV_NVDLA_MCIF_READ_IG_arb.v
NV_NVDLA_MCIF_READ_IG_bpt.v
NV_NVDLA_MCIF_READ_IG_cvt.v
NV_NVDLA_MCIF_WRITE_IG_bpt.v
NV_NVDLA_MCIF_WRITE_IG_cvt.v
NV_NVDLA_MCIF_WRITE_IG_arb.v
NV_CLK_gate_power.v
CKLNQD12.v
CKLNQD12PO4.v
NV_BLKBOX_SRC0_X.v
AN2D4PO4.v
NV_NVDLA_CDP_RDMA_eg.v
NV_NVDLA_CDP_DP_cvtout.v
NV_NVDLA_CDP_DP_sum.v
NV_NVDLA_CDP_RDMA_ig.v
NV_NVDLA_CDP_DP_lut.v
NV_NVDLA_CDP_DP_LUT_ctrl.v
NV_NVDLA_CDP_REG_single.v
NV_NVDLA_CDP_RDMA_reg.v
NV_NVDLA_CDP_DP_cvtin.v
NV_NVDLA_CDP_RDMA_cq.v
NV_NVDLA_CDP_DP_bufferin_tp1.v
NV_NVDLA_CDP_DP_mul.v
NV_NVDLA_CDP_REG_dual.v
NV_NVDLA_CDP_DP_syncfifo.v
NV_NVDLA_CDP_DP_intp.v
NV_NVDLA_CDP_DP_LUT_CTRL_unit.v
NV_NVDLA_CDP_DP_INTP_unit.v
NV_NVDLA_CDP_DP_MUL_unit.v
sync_reset.v
NV_BLKBOX_SRC0.v
OR2D1.v
p_SSYNC2DO_C_PP.v
MUX2D4.v
MUX2HDD2.v
sync3d_s_ppp.v
sync3d.v
p_SSYNC3DO_S_PPP.v
p_SSYNC3DO.v
NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v
NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
oneHotClk_async_read_clock.v
p_STRICTSYNC3DOTM_C_PPP.v
oneHotClk_async_write_clock.v
p_SSYNC3DO_C_PPP.v
NV_NVDLA_XXIF_libs.v
NV_NVDLA_DMAIF_rdreq.v
NV_BLKBOX_SINK.v
NV_NVDLA_CDP_RDMA_lat_fifo.v
NV_NVDLA_CDP_RDMA_REG_single.v
NV_NVDLA_CDP_RDMA_ro_fifo.v
NV_NVDLA_CDP_RDMA_REG_dual.v
NV_NVDLA_DMAIF_rdrsp.v
NV_NVDLA_CDP_WDMA_dat_fifo.v
NV_NVDLA_DMAIF_wr.v
HLS_cdp_ocvt.v
HLS_cdp_icvt.v
NV_NVDLA_CDP_DP_data_fifo.v
NV_NVDLA_CDP_DP_intpinfo_fifo.v
NV_NVDLA_CDP_DP_sumpd_fifo.v
int_sum_block_tp1.v
NV_NVDLA_HLS_shiftrightsu.v
NV_NVDLA_PDP_CORE_preproc.v
NV_NVDLA_PDP_WDMA_dat.v
NV_NVDLA_PDP_CORE_cal2d.v
NV_NVDLA_PDP_RDMA_cq.v
NV_NVDLA_PDP_CORE_cal1d.v
NV_NVDLA_PDP_RDMA_REG_single.v
NV_NVDLA_PDP_RDMA_eg.v
NV_NVDLA_PDP_WDMA_cmd.v
NV_NVDLA_PDP_REG_dual.v
NV_NVDLA_PDP_REG_single.v
NV_NVDLA_PDP_RDMA_REG_dual.v
NV_NVDLA_PDP_RDMA_ig.v
NV_NVDLA_PDP_RDMA_reg.v
NV_NVDLA_PDP_RDMA_lat_fifo.v
NV_NVDLA_PDP_RDMA_ro_fifo.v
NV_NVDLA_PDP_WDMA_DAT_fifo.v
NV_NVDLA_PDP_CORE_unit1d.v
NV_NVDLA_GLB_CSB_reg.v
NV_NVDLA_sync3d_c.v
sync3d_c_ppp.v
NV_NVDLA_cdma.v
NV_NVDLA_csc.v
NV_NVDLA_cbuf.v
NV_NVDLA_CDMA_status.v
NV_NVDLA_CDMA_regfile.v
NV_NVDLA_CDMA_cvt.v
NV_NVDLA_CDMA_dc.v
NV_NVDLA_CDMA_dma_mux.v
NV_NVDLA_CDMA_shared_buffer.v
NV_NVDLA_CDMA_img.v
NV_NVDLA_CDMA_slcg.v
NV_NVDLA_CDMA_wt.v
NV_NVDLA_CDMA_WT_8ATMM_fifo.v
NV_NVDLA_CDMA_CVT_cell.v
NV_NVDLA_CDMA_IMG_ctrl.v
NV_NVDLA_CDMA_IMG_pack.v
NV_NVDLA_CDMA_IMG_sg.v
NV_NVDLA_CDMA_single_reg.v
NV_NVDLA_CDMA_WT_fifo.v
NV_NVDLA_CDMA_dual_reg.v
NV_NVDLA_CDMA_DC_fifo.v
NV_NVDLA_HLS_saturate.v
NV_NVDLA_CDMA_IMG_fifo.v
NV_NVDLA_CDMA_IMG_sg2pack_fifo.v
NV_NVDLA_CSC_regfile.v
NV_NVDLA_CSC_wl.v
NV_NVDLA_CSC_WL_dec.v
NV_NVDLA_CSC_sg.v
NV_NVDLA_CSC_dl.v
NV_NVDLA_CSC_slcg.v
NV_NVDLA_CSC_SG_dat_fifo.v
NV_NVDLA_CSC_SG_wt_fifo.v
NV_NVDLA_CSC_dual_reg.v
NV_NVDLA_CSC_single_reg.v
NV_NVDLA_CACC_assembly_ctrl.v
NV_NVDLA_CACC_dual_reg.v
NV_NVDLA_CMAC_CORE_slcg.v
NV_NVDLA_CACC_assembly_buffer.v
NV_NVDLA_CACC_slcg.v
NV_NVDLA_cacc.v
NV_NVDLA_CACC_single_reg.v
NV_NVDLA_CACC_calculator.v
NV_NVDLA_CMAC_core.v
NV_NVDLA_CACC_delivery_buffer.v
NV_NVDLA_CACC_CALC_int8.v
NV_NVDLA_CACC_regfile.v
NV_NVDLA_CMAC_CORE_rt_in.v
NV_NVDLA_CMAC_REG_dual.v
NV_NVDLA_CACC_delivery_ctrl.v
NV_NVDLA_CMAC_reg.v
NV_NVDLA_cmac.v
NV_NVDLA_CMAC_CORE_active.v
NV_NVDLA_CMAC_CORE_cfg.v
NV_NVDLA_CMAC_CORE_mac.v
NV_NVDLA_CMAC_REG_single.v
NV_NVDLA_CMAC_CORE_rt_out.v
NV_NVDLA_sdp.v
NV_NVDLA_SDP_rdma.v
NV_NVDLA_SDP_wdma.v
NV_NVDLA_SDP_reg.v
NV_NVDLA_SDP_core.v
NV_NVDLA_SDP_HLS_x1_int.v
NV_NVDLA_SDP_WDMA_cmd.v
NV_NVDLA_SDP_RDMA_REG_dual.v
NV_NVDLA_SDP_RDMA_reg.v
NV_NVDLA_SDP_CORE_unpack.v
NV_NVDLA_SDP_REG_dual.v
NV_NVDLA_SDP_RDMA_pack.v
NV_NVDLA_SDP_WDMA_gate.v
NV_NVDLA_SDP_HLS_c.v
NV_NVDLA_SDP_nrdma.v
NV_NVDLA_SDP_WDMA_DAT_out.v
NV_NVDLA_SDP_CORE_pack.v
NV_NVDLA_SDP_WDMA_intr.v
NV_NVDLA_SDP_cmux.v
NV_NVDLA_SDP_CORE_gate.v
NV_NVDLA_SDP_WDMA_dat.v
NV_NVDLA_SDP_REG_single.v
NV_NVDLA_SDP_RDMA_REG_single.v
NV_NVDLA_SDP_brdma.v
NV_NVDLA_SDP_WDMA_DAT_in.v
NV_NVDLA_SDP_mrdma.v
NV_NVDLA_SDP_HLS_x2_int.v
NV_NVDLA_SDP_MRDMA_eg.v
NV_NVDLA_SDP_MRDMA_gate.v
NV_NVDLA_SDP_NRDMA_gate.v
NV_NVDLA_SDP_MRDMA_ig.v
NV_NVDLA_SDP_RDMA_ig.v
NV_NVDLA_SDP_RDMA_eg.v
NV_NVDLA_SDP_BRDMA_gate.v
NV_NVDLA_SDP_RDMA_dmaif.v
NV_NVDLA_SDP_HLS_X_int_relu.v
NV_NVDLA_SDP_HLS_C_int.v
NV_NVDLA_SDP_HLS_X_int_alu.v
NV_NVDLA_SDP_HLS_X_int_mul.v
NV_NVDLA_SDP_HLS_X_int_trt.v
NV_NVDLA_SDP_HLS_relu.v
NV_NVDLA_SDP_HLS_prelu.v
NV_NVDLA_SDP_HLS_sync2data.v
NV_NVDLA_HLS_shiftleftsu.v
NV_NVDLA_HLS_shiftrightsatsu.v
NV_NVDLA_SDP_NRDMA_cq_lib.v
NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v
NV_NVDLA_SDP_BRDMA_cq_lib.v
NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v
NV_NVDLA_SDP_MRDMA_cq_lib.v
NV_NVDLA_SDP_MRDMA_EG_din.v
NV_NVDLA_SDP_MRDMA_EG_dout.v
NV_NVDLA_SDP_MRDMA_EG_cmd.v
NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v
NV_NVDLA_SDP_RDMA_unpack.v
NV_NVDLA_SDP_RDMA_EG_ro.v
NV_BLKBOX_BUFFER.v
SDFQD1.v
RAMDP_128X6_GL_M2_E2.v
RAMDP_128X11_GL_M2_E2.v
RAMDP_16X64_GL_M1_E2.v
RAMPDP_256X64_GL_M2_D2.v
RAMDP_16X272_GL_M1_E2.v
RAMDP_16X66_GL_M1_E2.v
RAMDP_16X256_GL_M1_E2.v
RAMDP_16X14_GL_M1_E2.v
RAMDP_16X16_GL_M1_E2.v
ScanShareSel_JTAG_reg_ext_cg.v
sync2d_c_pp.v
p_SDFCNQD1PO4.v
RAMDP_256X4_GL_M2_E2.v
RAMDP_256X8_GL_M2_E2.v
RAMDP_8X66_GL_M1_E2.v
RAMDP_80X9_GL_M2_E2.v
RAMPDP_80X17_GL_M2_D2.v
RAMDP_60X22_GL_M1_E2.v
RAMPDP_128X18_GL_M2_D2.v
nv_ram_rws_128x18_logic.v
nv_ram_rws_128x256_logic.v
nv_ram_rws_128x64_logic.v
nv_ram_rws_16x256_logic.v
nv_ram_rws_16x272_logic.v
nv_ram_rws_16x64_logic.v
nv_ram_rws_256x3_logic.v
nv_ram_rws_256x512_logic.v
nv_ram_rws_256x64_logic.v
nv_ram_rws_256x7_logic.v
nv_ram_rws_32x16_logic.v
nv_ram_rws_32x512_logic.v
nv_ram_rws_32x544_logic.v
nv_ram_rws_32x768_logic.v
nv_ram_rws_512x256_logic.v
nv_ram_rws_512x512_logic.v
nv_ram_rws_512x64_logic.v
nv_ram_rws_64x1024_logic.v
nv_ram_rws_64x1088_logic.v
nv_ram_rws_64x10_logic.v
nv_ram_rws_64x116_logic.v
nv_ram_rws_64x18_logic.v
nv_ram_rwsp_128x11_logic.v
nv_ram_rwsp_128x6_logic.v
nv_ram_rwsp_160x16_logic.v
nv_ram_rwsp_160x514_logic.v
nv_ram_rwsp_160x65_logic.v
nv_ram_rwsp_16x14_logic.v
nv_ram_rwsp_16x16_logic.v
nv_ram_rwsp_16x65_logic.v
nv_ram_rwsp_20x289_logic.v
nv_ram_rwsp_245x514_logic.v
nv_ram_rwsp_256x11_logic.v
nv_ram_rwsp_32x32_logic.v
nv_ram_rwsp_61x514_logic.v
nv_ram_rwsp_61x64_logic.v
nv_ram_rwsp_61x65_logic.v
nv_ram_rwsp_80x14_logic.v
nv_ram_rwsp_80x16_logic.v
nv_ram_rwsp_80x256_logic.v
nv_ram_rwsp_80x514_logic.v
nv_ram_rwsp_80x65_logic.v
nv_ram_rwsp_8x65_logic.v
nv_ram_rwst_256x8_logic.v
nv_ram_rwsthp_19x32_logic.v
nv_ram_rwsthp_19x4_logic.v
nv_ram_rwsthp_19x80_logic.v
nv_ram_rwsthp_20x4_logic.v
nv_ram_rwsthp_60x168_logic.v
nv_ram_rwsthp_60x21_logic.v
nv_ram_rwsthp_80x15_logic.v
nv_ram_rwsthp_80x17_logic.v
nv_ram_rwsthp_80x72_logic.v
nv_ram_rwsthp_80x9_logic.v
nv_ram_rws_128x18.v
nv_ram_rws_128x256.v
nv_ram_rws_128x64.v
nv_ram_rws_16x256.v
nv_ram_rws_16x272.v
nv_ram_rws_16x64.v
nv_ram_rws_256x3.v
nv_ram_rws_256x512.v
nv_ram_rws_256x64.v
nv_ram_rws_256x7.v
nv_ram_rws_32x16.v
nv_ram_rws_32x512.v
nv_ram_rws_32x544.v
nv_ram_rws_32x768.v
nv_ram_rws_512x256.v
nv_ram_rws_512x512.v
nv_ram_rws_512x64.v
nv_ram_rws_64x1024.v
nv_ram_rws_64x1088.v
nv_ram_rws_64x10.v
nv_ram_rws_64x116.v
nv_ram_rws_64x18.v
nv_ram_rwsp_128x11.v
nv_ram_rwsp_128x6.v
nv_ram_rwsp_160x16.v
nv_ram_rwsp_160x514.v
nv_ram_rwsp_160x65.v
nv_ram_rwsp_16x14.v
nv_ram_rwsp_16x16.v
nv_ram_rwsp_16x65.v
nv_ram_rwsp_20x289.v
nv_ram_rwsp_245x514.v
nv_ram_rwsp_256x11.v
nv_ram_rwsp_32x32.v
nv_ram_rwsp_61x514.v
nv_ram_rwsp_61x64.v
nv_ram_rwsp_61x65.v
nv_ram_rwsp_80x14.v
nv_ram_rwsp_80x16.v
nv_ram_rwsp_80x256.v
nv_ram_rwsp_80x514.v
nv_ram_rwsp_80x65.v
nv_ram_rwsp_8x65.v
nv_ram_rwst_256x8.v
nv_ram_rwsthp_19x32.v
nv_ram_rwsthp_19x4.v
nv_ram_rwsthp_19x80.v
nv_ram_rwsthp_20x4.v
nv_ram_rwsthp_60x168.v
nv_ram_rwsthp_60x21.v
nv_ram_rwsthp_80x15.v
nv_ram_rwsthp_80x17.v
nv_ram_rwsthp_80x72.v
nv_ram_rwsthp_80x9.v
fakeram7_256x64_dp.v
-v NV_NVDLA_XXIF_libs.v
Flows/NanGate45/mempool_group/scripts/cadence/run → Flows/ASAP7/nvdla/scripts/cadence/run.sh
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload genus
module load genus/21.1
module unload innovus
module load innovus/21.1
mkdir -p log
innovus -64 -init run_invs.tcl -log log/run.log
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/ASAP7/nvdla/scripts/cadence/run_genus.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
set_db library $list_lib
set_db init_hdl_search_path [list . ../../../../../Testcases/nvdla/rtl/]
#################################################
# Load Design and Initialize
#################################################
read_hdl -f rtl_list.tcl
elaborate $DESIGN
time_info Elaboration
read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic
time_info GENERIC
# generate a summary for the current stage of synthesis
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/ASAP7/nvdla/scripts/cadence/run_genus_iSpatial.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
read_mmmc mmmc_iSpatial_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
# Target library
set link_library $list_lib
set target_library $list_lib
set_db init_hdl_search_path [list . $rtl_path]
# set path
set_db auto_ungroup none
#set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
read_hdl -f rtl_list.tcl
elaborate $DESIGN
time_info Elaboration
#read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
read_def $floorplan_def
check_floorplan -detailed
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic -physical
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map -physical
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt -spatial
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set site "asap7sc7p5t"
set rptDir summaryReport/
set encDir enc/
if {![file exists $rptDir/]} {
exec mkdir $rptDir/
}
if {![file exists $encDir/]} {
exec mkdir $encDir/
}
# default settings
set init_pwr_net VDD
set init_gnd_net VSS
# default settings
set init_verilog "$netlist"
set init_design_netlisttype "Verilog"
set init_design_settop 1
set init_top_cell "$DESIGN"
set init_lef_file "$lefs"
# MCMM setup
init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
globalNetConnect VSS -type pgpin -pin VSS -inst * -override
globalNetConnect VDD -type tiehi -inst * -override
globalNetConnect VSS -type tielo -inst * -override
setOptMode -powerEffort low -leakageToDynamicRatio 0.5
setGenerateViaMode -auto true
generateVias
# basic path groups
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 1 1 1 1
setFPlanMode -snapBlockGrid LayerTrack
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {M2 M3 M7 M8 M9 Pad} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 7
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
create_ccopt_clock_tree_spec
ccopt_design
set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
setNanoRouteMode -routeWithViaInPin "1:1"
setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
exit
Flows/NanGate45/ariane136/scripts/cadence/run.sh 100644 → 100755
File mode changed from 100644 to 100755
Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/NanGate45/nvdla/README.md 0 → 100644
# **Synthesis, Place \& Route (SP\&R):**
Here we provide the setup to run SP&R of NVDLA design with 128 macros on NanGate45 using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
## **SP\&R Flow:**
We implement [NVDLA](../../../Testcases/nvdla/) on the NanGate45 platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/nangate45). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the NanGate45 platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/NanGate45*](../../../Enablements/NanGate45/) directory.
### **Using Cadence Genus and Innovus:**
All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.
**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
```
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
```
We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow.
<img src="./screenshots/nvdla_Innovus_ng45.png" alt="nvdla_cadence" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
<!--
### **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:
1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the below command
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
```
4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.
<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
-->
\ No newline at end of file
Flows/SKY130HD/ariane136/README.md
......@@ -2,10 +2,9 @@
Here we provide the setup to run SP&R of Ariane design with 136 macros on SKY130HD using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
- [**OpenROAD tools**](#using-openroad-flow-scripts)
## **SP\&R Flow:**
We implement Ariane design with [136 macros](../../../Testcases/ariane136/) on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.
We implement Ariane design with [136 macros](../../../Testcases/ariane136/) on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.
### **Using Cadence Genus and Innovus:**
......@@ -19,10 +18,7 @@ We also generate a synthesized netlist, which is available in the [*./netlist/*]
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Innovus requires a configuration file to run the macro placement flow. For this we use *proto_design -constraints mp_config.tcl* command. The configuration file [*mp_config.tcl*](./scripts/cadence/mp_config.tcl) is available in the *./scripts/cadence/* directory. Some details of the configuration files are as follows.
1. Provide the memory hierarchy name under the **SEED** section. If you do not provide the memory hierarchy here, then the macro placement constraints (e.g., cell orientation, spacing, etc.) related to that memory may be overlooked.
2. For each macro, valid orientation and spacing rules can be provided under the **MACRO** section. For example, we set valid macro orientation as *R0* for our run, horizontal spacing as *10um*, and vertical spacing as *5um*. Also, when you provide the cell name (ref name, not instance name) add the *isCell=true* option.
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using Cadence flow.
<img src="./screenshots/Ariane136_Innovus_Genus.png" alt="ariane136_cadence" width="400"/>
......
Flows/SKY130HD/nvdla/README.md 0 → 100644
# **Synthesis, Place \& Route (SP\&R):**
Here we provide the setup to run SP&R of NVDLA design with 128 macros on SKY130HD using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
## **SP\&R Flow:**
We implement [NVDLA](../../../Testcases/nvdla/) on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.
### **Using Cadence Genus and Innovus:**
All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.
**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
```
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
```
We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow. The 256x64 SRAM memory dimension is weird. This is the memory we have generated using the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) memory compiler.
<img src="./screenshots/nvdla_Innovus_sky130hd.png" alt="nvdla_cadence" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
<!--
### **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:
1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the below command
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
```
4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.
<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
-->
\ No newline at end of file
Testcases/nvdla/README.md
# Netlist preparation of NVDLA
We generate the RTL of NVDLA testcase using the steps given in [NVDLA/hw](https://github.com/nvdla/hw/tree/nv_small) GitHub repo. First we clone the **nv_small** branch and then we follow the steps givne in the [Integrator's Manual](http://nvdla.org/hw/v1/integration_guide.html). The [nv_small.spec](https://github.com/nvdla/hw/blob/nv_small/spec/defs/nv_small.spec) is used as the configuration file to generate the testcase.
We generate the RTL of the NVDLA testcase using the steps given in the [NVDLA/hw](https://github.com/nvdla/hw/tree/nv_small) GitHub repo. First, we clone the **nv_small** branch and then we follow the steps givne in the [Integrator's Manual](http://nvdla.org/hw/v1/integration_guide.html). The [nv_small.spec](https://github.com/nvdla/hw/blob/nv_small/spec/defs/nv_small.spec) is used as the configuration file to generate the testcase. As NVDLA partition *c* has macros, our testcase only includes the partition *c*.
All the generated verilogs are copied to the [*rtl*](./rtl/) directory. NVDLA design uses dual port 256x64 bit SRAM. All our enablements currently support only single port SRAMS so we use two single port 256x64 SRAMs (One for reading from the read address and another for writing to the write address. We understand this do not replicated the actual functionality). We added fakeram_256x64_dp wrapper module to replace the dual port SRAMS with two single port SRAM and instantiate this wrapper in the [nv_ram_rws_256x64.v](./rtl/nv_ram_rws_256x64.v) file in the placeof behavioral model of the dual port ram (*nv_ram_rws_256x64_logic*).
All the generated verilogs are copied to the [*rtl*](./rtl/) directory. NVDLA design uses dual-port 256x64 bit SRAM. All our enablements currently support only single-port SRAM. So we use two single-port 256x64 bit SRAMs (One for reading from the read address and another for writing to the write address. We understand this does not replicate the actual functionality). We added the *fakeram_256x64_dp* wrapper module to replace the dual-port SRAM with two single-port SRAMs and instantiate this wrapper in the [nv_ram_rws_256x64.v](./rtl/nv_ram_rws_256x64.v) file in place of the behavioral model of the dual-port SRAM (*nv_ram_rws_256x64_logic*). The *fakeram_256x64_dp* wrapper module is available in the *fakeram<7|45|130>_256x64_dp.v*.
During synthesis stageg if one of the memory output is not connected to anything then during optimization it will be removed. So we add this below logic for reading from the memory:
During the synthesis stage if the memory outputs are not connected to anything then they will be removed during optimization. So we add the following logic for the reading operation.
```
genvar k;
generate
......@@ -14,6 +14,6 @@ endgenerate
```
Problem faced:
Note:
- Clone the **nv_small** branch. For the default branch, generated RTL will have more than million instances.
- To fix the problem of missing perl package use the *cpan* command.
\ No newline at end of file
- To install the missing perl packages use the *cpan* command.
\ No newline at end of file
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