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macroplacement
Commit 5d3cbda9 by sakundu
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Added NVDLA details and updated the README 

Signed-off-by: sakundu <sakundu@ucsd.edu>
parent 6f2cd19a
Showing with 4404 additions and 1309 deletions
Enablements/ASAP7/lef/sram_asap7_64x256_1rw.lef
......@@ -3,591 +3,15 @@ BUSBITCHARS "[]" ;
MACRO sram_asap7_64x256_1rw
FOREIGN sram_asap7_64x256_1rw 0 0 ;
SYMMETRY X Y R90 ;
SIZE 8.360 BY 67.200 ;
SIZE 16.720 BY 33.600 ;
CLASS BLOCK ;
PIN w_mask_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 0.192 0.005 0.197 ;
END
END w_mask_in[0]
PIN w_mask_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 0.384 0.005 0.389 ;
END
END w_mask_in[1]
PIN w_mask_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 0.576 0.005 0.581 ;
END
END w_mask_in[2]
PIN w_mask_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 0.768 0.005 0.773 ;
END
END w_mask_in[3]
PIN w_mask_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 0.960 0.005 0.965 ;
END
END w_mask_in[4]
PIN w_mask_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 1.152 0.005 1.157 ;
END
END w_mask_in[5]
PIN w_mask_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 1.344 0.005 1.349 ;
END
END w_mask_in[6]
PIN w_mask_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 1.536 0.005 1.541 ;
END
END w_mask_in[7]
PIN w_mask_in[8]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 1.728 0.005 1.733 ;
END
END w_mask_in[8]
PIN w_mask_in[9]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 1.920 0.005 1.925 ;
END
END w_mask_in[9]
PIN w_mask_in[10]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 2.112 0.005 2.117 ;
END
END w_mask_in[10]
PIN w_mask_in[11]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 2.304 0.005 2.309 ;
END
END w_mask_in[11]
PIN w_mask_in[12]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 2.496 0.005 2.501 ;
END
END w_mask_in[12]
PIN w_mask_in[13]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 2.688 0.005 2.693 ;
END
END w_mask_in[13]
PIN w_mask_in[14]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 2.880 0.005 2.885 ;
END
END w_mask_in[14]
PIN w_mask_in[15]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 3.072 0.005 3.077 ;
END
END w_mask_in[15]
PIN w_mask_in[16]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 3.264 0.005 3.269 ;
END
END w_mask_in[16]
PIN w_mask_in[17]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 3.456 0.005 3.461 ;
END
END w_mask_in[17]
PIN w_mask_in[18]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 3.648 0.005 3.653 ;
END
END w_mask_in[18]
PIN w_mask_in[19]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 3.840 0.005 3.845 ;
END
END w_mask_in[19]
PIN w_mask_in[20]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 4.032 0.005 4.037 ;
END
END w_mask_in[20]
PIN w_mask_in[21]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 4.224 0.005 4.229 ;
END
END w_mask_in[21]
PIN w_mask_in[22]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 4.416 0.005 4.421 ;
END
END w_mask_in[22]
PIN w_mask_in[23]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 4.608 0.005 4.613 ;
END
END w_mask_in[23]
PIN w_mask_in[24]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 4.800 0.005 4.805 ;
END
END w_mask_in[24]
PIN w_mask_in[25]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 4.992 0.005 4.997 ;
END
END w_mask_in[25]
PIN w_mask_in[26]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 5.184 0.005 5.189 ;
END
END w_mask_in[26]
PIN w_mask_in[27]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 5.376 0.005 5.381 ;
END
END w_mask_in[27]
PIN w_mask_in[28]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 5.568 0.005 5.573 ;
END
END w_mask_in[28]
PIN w_mask_in[29]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 5.760 0.005 5.765 ;
END
END w_mask_in[29]
PIN w_mask_in[30]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 5.952 0.005 5.957 ;
END
END w_mask_in[30]
PIN w_mask_in[31]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 6.144 0.005 6.149 ;
END
END w_mask_in[31]
PIN w_mask_in[32]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 6.336 0.005 6.341 ;
END
END w_mask_in[32]
PIN w_mask_in[33]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 6.528 0.005 6.533 ;
END
END w_mask_in[33]
PIN w_mask_in[34]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 6.720 0.005 6.725 ;
END
END w_mask_in[34]
PIN w_mask_in[35]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 6.912 0.005 6.917 ;
END
END w_mask_in[35]
PIN w_mask_in[36]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 7.104 0.005 7.109 ;
END
END w_mask_in[36]
PIN w_mask_in[37]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 7.296 0.005 7.301 ;
END
END w_mask_in[37]
PIN w_mask_in[38]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 7.488 0.005 7.493 ;
END
END w_mask_in[38]
PIN w_mask_in[39]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 7.680 0.005 7.685 ;
END
END w_mask_in[39]
PIN w_mask_in[40]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 7.872 0.005 7.877 ;
END
END w_mask_in[40]
PIN w_mask_in[41]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 8.064 0.005 8.069 ;
END
END w_mask_in[41]
PIN w_mask_in[42]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 8.256 0.005 8.261 ;
END
END w_mask_in[42]
PIN w_mask_in[43]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 8.448 0.005 8.453 ;
END
END w_mask_in[43]
PIN w_mask_in[44]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 8.640 0.005 8.645 ;
END
END w_mask_in[44]
PIN w_mask_in[45]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 8.832 0.005 8.837 ;
END
END w_mask_in[45]
PIN w_mask_in[46]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 9.024 0.005 9.029 ;
END
END w_mask_in[46]
PIN w_mask_in[47]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 9.216 0.005 9.221 ;
END
END w_mask_in[47]
PIN w_mask_in[48]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 9.408 0.005 9.413 ;
END
END w_mask_in[48]
PIN w_mask_in[49]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 9.600 0.005 9.605 ;
END
END w_mask_in[49]
PIN w_mask_in[50]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 9.792 0.005 9.797 ;
END
END w_mask_in[50]
PIN w_mask_in[51]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 9.984 0.005 9.989 ;
END
END w_mask_in[51]
PIN w_mask_in[52]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 10.176 0.005 10.181 ;
END
END w_mask_in[52]
PIN w_mask_in[53]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 10.368 0.005 10.373 ;
END
END w_mask_in[53]
PIN w_mask_in[54]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 10.560 0.005 10.565 ;
END
END w_mask_in[54]
PIN w_mask_in[55]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 10.752 0.005 10.757 ;
END
END w_mask_in[55]
PIN w_mask_in[56]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 10.944 0.005 10.949 ;
END
END w_mask_in[56]
PIN w_mask_in[57]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 11.136 0.005 11.141 ;
END
END w_mask_in[57]
PIN w_mask_in[58]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 11.328 0.005 11.333 ;
END
END w_mask_in[58]
PIN w_mask_in[59]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 11.520 0.005 11.525 ;
END
END w_mask_in[59]
PIN w_mask_in[60]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 11.712 0.005 11.717 ;
END
END w_mask_in[60]
PIN w_mask_in[61]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 11.904 0.005 11.909 ;
END
END w_mask_in[61]
PIN w_mask_in[62]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 12.096 0.005 12.101 ;
END
END w_mask_in[62]
PIN w_mask_in[63]
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 12.288 0.005 12.293 ;
END
END w_mask_in[63]
PIN rd_out[0]
DIRECTION OUTPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 19.200 0.005 19.205 ;
RECT 0.000 0.048 0.024 0.072 ;
END
END rd_out[0]
PIN rd_out[1]
......@@ -596,7 +20,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 19.392 0.005 19.397 ;
RECT 0.000 0.288 0.024 0.312 ;
END
END rd_out[1]
PIN rd_out[2]
......@@ -605,7 +29,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 19.584 0.005 19.589 ;
RECT 0.000 0.528 0.024 0.552 ;
END
END rd_out[2]
PIN rd_out[3]
......@@ -614,7 +38,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 19.776 0.005 19.781 ;
RECT 0.000 0.768 0.024 0.792 ;
END
END rd_out[3]
PIN rd_out[4]
......@@ -623,7 +47,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 19.968 0.005 19.973 ;
RECT 0.000 1.008 0.024 1.032 ;
END
END rd_out[4]
PIN rd_out[5]
......@@ -632,7 +56,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 20.160 0.005 20.165 ;
RECT 0.000 1.248 0.024 1.272 ;
END
END rd_out[5]
PIN rd_out[6]
......@@ -641,7 +65,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 20.352 0.005 20.357 ;
RECT 0.000 1.488 0.024 1.512 ;
END
END rd_out[6]
PIN rd_out[7]
......@@ -650,7 +74,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 20.544 0.005 20.549 ;
RECT 0.000 1.728 0.024 1.752 ;
END
END rd_out[7]
PIN rd_out[8]
......@@ -659,7 +83,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 20.736 0.005 20.741 ;
RECT 0.000 1.968 0.024 1.992 ;
END
END rd_out[8]
PIN rd_out[9]
......@@ -668,7 +92,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 20.928 0.005 20.933 ;
RECT 0.000 2.208 0.024 2.232 ;
END
END rd_out[9]
PIN rd_out[10]
......@@ -677,7 +101,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 21.120 0.005 21.125 ;
RECT 0.000 2.448 0.024 2.472 ;
END
END rd_out[10]
PIN rd_out[11]
......@@ -686,7 +110,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 21.312 0.005 21.317 ;
RECT 0.000 2.688 0.024 2.712 ;
END
END rd_out[11]
PIN rd_out[12]
......@@ -695,7 +119,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 21.504 0.005 21.509 ;
RECT 0.000 2.928 0.024 2.952 ;
END
END rd_out[12]
PIN rd_out[13]
......@@ -704,7 +128,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 21.696 0.005 21.701 ;
RECT 0.000 3.168 0.024 3.192 ;
END
END rd_out[13]
PIN rd_out[14]
......@@ -713,7 +137,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 21.888 0.005 21.893 ;
RECT 0.000 3.408 0.024 3.432 ;
END
END rd_out[14]
PIN rd_out[15]
......@@ -722,7 +146,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 22.080 0.005 22.085 ;
RECT 0.000 3.648 0.024 3.672 ;
END
END rd_out[15]
PIN rd_out[16]
......@@ -731,7 +155,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 22.272 0.005 22.277 ;
RECT 0.000 3.888 0.024 3.912 ;
END
END rd_out[16]
PIN rd_out[17]
......@@ -740,7 +164,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 22.464 0.005 22.469 ;
RECT 0.000 4.128 0.024 4.152 ;
END
END rd_out[17]
PIN rd_out[18]
......@@ -749,7 +173,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 22.656 0.005 22.661 ;
RECT 0.000 4.368 0.024 4.392 ;
END
END rd_out[18]
PIN rd_out[19]
......@@ -758,7 +182,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 22.848 0.005 22.853 ;
RECT 0.000 4.608 0.024 4.632 ;
END
END rd_out[19]
PIN rd_out[20]
......@@ -767,7 +191,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 23.040 0.005 23.045 ;
RECT 0.000 4.848 0.024 4.872 ;
END
END rd_out[20]
PIN rd_out[21]
......@@ -776,7 +200,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 23.232 0.005 23.237 ;
RECT 0.000 5.088 0.024 5.112 ;
END
END rd_out[21]
PIN rd_out[22]
......@@ -785,7 +209,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 23.424 0.005 23.429 ;
RECT 0.000 5.328 0.024 5.352 ;
END
END rd_out[22]
PIN rd_out[23]
......@@ -794,7 +218,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 23.616 0.005 23.621 ;
RECT 0.000 5.568 0.024 5.592 ;
END
END rd_out[23]
PIN rd_out[24]
......@@ -803,7 +227,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 23.808 0.005 23.813 ;
RECT 0.000 5.808 0.024 5.832 ;
END
END rd_out[24]
PIN rd_out[25]
......@@ -812,7 +236,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 24.000 0.005 24.005 ;
RECT 0.000 6.048 0.024 6.072 ;
END
END rd_out[25]
PIN rd_out[26]
......@@ -821,7 +245,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 24.192 0.005 24.197 ;
RECT 0.000 6.288 0.024 6.312 ;
END
END rd_out[26]
PIN rd_out[27]
......@@ -830,7 +254,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 24.384 0.005 24.389 ;
RECT 0.000 6.528 0.024 6.552 ;
END
END rd_out[27]
PIN rd_out[28]
......@@ -839,7 +263,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 24.576 0.005 24.581 ;
RECT 0.000 6.768 0.024 6.792 ;
END
END rd_out[28]
PIN rd_out[29]
......@@ -848,7 +272,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 24.768 0.005 24.773 ;
RECT 0.000 7.008 0.024 7.032 ;
END
END rd_out[29]
PIN rd_out[30]
......@@ -857,7 +281,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 24.960 0.005 24.965 ;
RECT 0.000 7.248 0.024 7.272 ;
END
END rd_out[30]
PIN rd_out[31]
......@@ -866,7 +290,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 25.152 0.005 25.157 ;
RECT 0.000 7.488 0.024 7.512 ;
END
END rd_out[31]
PIN rd_out[32]
......@@ -875,7 +299,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 25.344 0.005 25.349 ;
RECT 0.000 7.728 0.024 7.752 ;
END
END rd_out[32]
PIN rd_out[33]
......@@ -884,7 +308,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 25.536 0.005 25.541 ;
RECT 0.000 7.968 0.024 7.992 ;
END
END rd_out[33]
PIN rd_out[34]
......@@ -893,7 +317,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 25.728 0.005 25.733 ;
RECT 0.000 8.208 0.024 8.232 ;
END
END rd_out[34]
PIN rd_out[35]
......@@ -902,7 +326,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 25.920 0.005 25.925 ;
RECT 0.000 8.448 0.024 8.472 ;
END
END rd_out[35]
PIN rd_out[36]
......@@ -911,7 +335,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 26.112 0.005 26.117 ;
RECT 0.000 8.688 0.024 8.712 ;
END
END rd_out[36]
PIN rd_out[37]
......@@ -920,7 +344,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 26.304 0.005 26.309 ;
RECT 0.000 8.928 0.024 8.952 ;
END
END rd_out[37]
PIN rd_out[38]
......@@ -929,7 +353,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 26.496 0.005 26.501 ;
RECT 0.000 9.168 0.024 9.192 ;
END
END rd_out[38]
PIN rd_out[39]
......@@ -938,7 +362,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 26.688 0.005 26.693 ;
RECT 0.000 9.408 0.024 9.432 ;
END
END rd_out[39]
PIN rd_out[40]
......@@ -947,7 +371,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 26.880 0.005 26.885 ;
RECT 0.000 9.648 0.024 9.672 ;
END
END rd_out[40]
PIN rd_out[41]
......@@ -956,7 +380,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 27.072 0.005 27.077 ;
RECT 0.000 9.888 0.024 9.912 ;
END
END rd_out[41]
PIN rd_out[42]
......@@ -965,7 +389,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 27.264 0.005 27.269 ;
RECT 0.000 10.128 0.024 10.152 ;
END
END rd_out[42]
PIN rd_out[43]
......@@ -974,7 +398,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 27.456 0.005 27.461 ;
RECT 0.000 10.368 0.024 10.392 ;
END
END rd_out[43]
PIN rd_out[44]
......@@ -983,7 +407,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 27.648 0.005 27.653 ;
RECT 0.000 10.608 0.024 10.632 ;
END
END rd_out[44]
PIN rd_out[45]
......@@ -992,7 +416,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 27.840 0.005 27.845 ;
RECT 0.000 10.848 0.024 10.872 ;
END
END rd_out[45]
PIN rd_out[46]
......@@ -1001,7 +425,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 28.032 0.005 28.037 ;
RECT 0.000 11.088 0.024 11.112 ;
END
END rd_out[46]
PIN rd_out[47]
......@@ -1010,7 +434,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 28.224 0.005 28.229 ;
RECT 0.000 11.328 0.024 11.352 ;
END
END rd_out[47]
PIN rd_out[48]
......@@ -1019,7 +443,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 28.416 0.005 28.421 ;
RECT 0.000 11.568 0.024 11.592 ;
END
END rd_out[48]
PIN rd_out[49]
......@@ -1028,7 +452,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 28.608 0.005 28.613 ;
RECT 0.000 11.808 0.024 11.832 ;
END
END rd_out[49]
PIN rd_out[50]
......@@ -1037,7 +461,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 28.800 0.005 28.805 ;
RECT 0.000 12.048 0.024 12.072 ;
END
END rd_out[50]
PIN rd_out[51]
......@@ -1046,7 +470,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 28.992 0.005 28.997 ;
RECT 0.000 12.288 0.024 12.312 ;
END
END rd_out[51]
PIN rd_out[52]
......@@ -1055,7 +479,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 29.184 0.005 29.189 ;
RECT 0.000 12.528 0.024 12.552 ;
END
END rd_out[52]
PIN rd_out[53]
......@@ -1064,7 +488,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 29.376 0.005 29.381 ;
RECT 0.000 12.768 0.024 12.792 ;
END
END rd_out[53]
PIN rd_out[54]
......@@ -1073,7 +497,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 29.568 0.005 29.573 ;
RECT 0.000 13.008 0.024 13.032 ;
END
END rd_out[54]
PIN rd_out[55]
......@@ -1082,7 +506,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 29.760 0.005 29.765 ;
RECT 0.000 13.248 0.024 13.272 ;
END
END rd_out[55]
PIN rd_out[56]
......@@ -1091,7 +515,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 29.952 0.005 29.957 ;
RECT 0.000 13.488 0.024 13.512 ;
END
END rd_out[56]
PIN rd_out[57]
......@@ -1100,7 +524,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 30.144 0.005 30.149 ;
RECT 0.000 13.728 0.024 13.752 ;
END
END rd_out[57]
PIN rd_out[58]
......@@ -1109,7 +533,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 30.336 0.005 30.341 ;
RECT 0.000 13.968 0.024 13.992 ;
END
END rd_out[58]
PIN rd_out[59]
......@@ -1118,7 +542,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 30.528 0.005 30.533 ;
RECT 0.000 14.208 0.024 14.232 ;
END
END rd_out[59]
PIN rd_out[60]
......@@ -1127,7 +551,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 30.720 0.005 30.725 ;
RECT 0.000 14.448 0.024 14.472 ;
END
END rd_out[60]
PIN rd_out[61]
......@@ -1136,7 +560,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 30.912 0.005 30.917 ;
RECT 0.000 14.688 0.024 14.712 ;
END
END rd_out[61]
PIN rd_out[62]
......@@ -1145,7 +569,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 31.104 0.005 31.109 ;
RECT 0.000 14.928 0.024 14.952 ;
END
END rd_out[62]
PIN rd_out[63]
......@@ -1154,7 +578,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 31.296 0.005 31.301 ;
RECT 0.000 15.168 0.024 15.192 ;
END
END rd_out[63]
PIN wd_in[0]
......@@ -1163,7 +587,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 38.208 0.005 38.213 ;
RECT 0.000 15.216 0.024 15.240 ;
END
END wd_in[0]
PIN wd_in[1]
......@@ -1172,7 +596,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 38.400 0.005 38.405 ;
RECT 0.000 15.456 0.024 15.480 ;
END
END wd_in[1]
PIN wd_in[2]
......@@ -1181,7 +605,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 38.592 0.005 38.597 ;
RECT 0.000 15.696 0.024 15.720 ;
END
END wd_in[2]
PIN wd_in[3]
......@@ -1190,7 +614,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 38.784 0.005 38.789 ;
RECT 0.000 15.936 0.024 15.960 ;
END
END wd_in[3]
PIN wd_in[4]
......@@ -1199,7 +623,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 38.976 0.005 38.981 ;
RECT 0.000 16.176 0.024 16.200 ;
END
END wd_in[4]
PIN wd_in[5]
......@@ -1208,7 +632,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 39.168 0.005 39.173 ;
RECT 0.000 16.416 0.024 16.440 ;
END
END wd_in[5]
PIN wd_in[6]
......@@ -1217,7 +641,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 39.360 0.005 39.365 ;
RECT 0.000 16.656 0.024 16.680 ;
END
END wd_in[6]
PIN wd_in[7]
......@@ -1226,7 +650,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 39.552 0.005 39.557 ;
RECT 0.000 16.896 0.024 16.920 ;
END
END wd_in[7]
PIN wd_in[8]
......@@ -1235,7 +659,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 39.744 0.005 39.749 ;
RECT 0.000 17.136 0.024 17.160 ;
END
END wd_in[8]
PIN wd_in[9]
......@@ -1244,7 +668,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 39.936 0.005 39.941 ;
RECT 0.000 17.376 0.024 17.400 ;
END
END wd_in[9]
PIN wd_in[10]
......@@ -1253,7 +677,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 40.128 0.005 40.133 ;
RECT 0.000 17.616 0.024 17.640 ;
END
END wd_in[10]
PIN wd_in[11]
......@@ -1262,7 +686,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 40.320 0.005 40.325 ;
RECT 0.000 17.856 0.024 17.880 ;
END
END wd_in[11]
PIN wd_in[12]
......@@ -1271,7 +695,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 40.512 0.005 40.517 ;
RECT 0.000 18.096 0.024 18.120 ;
END
END wd_in[12]
PIN wd_in[13]
......@@ -1280,7 +704,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 40.704 0.005 40.709 ;
RECT 0.000 18.336 0.024 18.360 ;
END
END wd_in[13]
PIN wd_in[14]
......@@ -1289,7 +713,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 40.896 0.005 40.901 ;
RECT 0.000 18.576 0.024 18.600 ;
END
END wd_in[14]
PIN wd_in[15]
......@@ -1298,7 +722,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 41.088 0.005 41.093 ;
RECT 0.000 18.816 0.024 18.840 ;
END
END wd_in[15]
PIN wd_in[16]
......@@ -1307,7 +731,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 41.280 0.005 41.285 ;
RECT 0.000 19.056 0.024 19.080 ;
END
END wd_in[16]
PIN wd_in[17]
......@@ -1316,7 +740,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 41.472 0.005 41.477 ;
RECT 0.000 19.296 0.024 19.320 ;
END
END wd_in[17]
PIN wd_in[18]
......@@ -1325,7 +749,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 41.664 0.005 41.669 ;
RECT 0.000 19.536 0.024 19.560 ;
END
END wd_in[18]
PIN wd_in[19]
......@@ -1334,7 +758,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 41.856 0.005 41.861 ;
RECT 0.000 19.776 0.024 19.800 ;
END
END wd_in[19]
PIN wd_in[20]
......@@ -1343,7 +767,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 42.048 0.005 42.053 ;
RECT 0.000 20.016 0.024 20.040 ;
END
END wd_in[20]
PIN wd_in[21]
......@@ -1352,7 +776,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 42.240 0.005 42.245 ;
RECT 0.000 20.256 0.024 20.280 ;
END
END wd_in[21]
PIN wd_in[22]
......@@ -1361,7 +785,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 42.432 0.005 42.437 ;
RECT 0.000 20.496 0.024 20.520 ;
END
END wd_in[22]
PIN wd_in[23]
......@@ -1370,7 +794,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 42.624 0.005 42.629 ;
RECT 0.000 20.736 0.024 20.760 ;
END
END wd_in[23]
PIN wd_in[24]
......@@ -1379,7 +803,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 42.816 0.005 42.821 ;
RECT 0.000 20.976 0.024 21.000 ;
END
END wd_in[24]
PIN wd_in[25]
......@@ -1388,7 +812,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 43.008 0.005 43.013 ;
RECT 0.000 21.216 0.024 21.240 ;
END
END wd_in[25]
PIN wd_in[26]
......@@ -1397,7 +821,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 43.200 0.005 43.205 ;
RECT 0.000 21.456 0.024 21.480 ;
END
END wd_in[26]
PIN wd_in[27]
......@@ -1406,7 +830,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 43.392 0.005 43.397 ;
RECT 0.000 21.696 0.024 21.720 ;
END
END wd_in[27]
PIN wd_in[28]
......@@ -1415,7 +839,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 43.584 0.005 43.589 ;
RECT 0.000 21.936 0.024 21.960 ;
END
END wd_in[28]
PIN wd_in[29]
......@@ -1424,7 +848,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 43.776 0.005 43.781 ;
RECT 0.000 22.176 0.024 22.200 ;
END
END wd_in[29]
PIN wd_in[30]
......@@ -1433,7 +857,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 43.968 0.005 43.973 ;
RECT 0.000 22.416 0.024 22.440 ;
END
END wd_in[30]
PIN wd_in[31]
......@@ -1442,7 +866,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 44.160 0.005 44.165 ;
RECT 0.000 22.656 0.024 22.680 ;
END
END wd_in[31]
PIN wd_in[32]
......@@ -1451,7 +875,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 44.352 0.005 44.357 ;
RECT 0.000 22.896 0.024 22.920 ;
END
END wd_in[32]
PIN wd_in[33]
......@@ -1460,7 +884,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 44.544 0.005 44.549 ;
RECT 0.000 23.136 0.024 23.160 ;
END
END wd_in[33]
PIN wd_in[34]
......@@ -1469,7 +893,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 44.736 0.005 44.741 ;
RECT 0.000 23.376 0.024 23.400 ;
END
END wd_in[34]
PIN wd_in[35]
......@@ -1478,7 +902,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 44.928 0.005 44.933 ;
RECT 0.000 23.616 0.024 23.640 ;
END
END wd_in[35]
PIN wd_in[36]
......@@ -1487,7 +911,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 45.120 0.005 45.125 ;
RECT 0.000 23.856 0.024 23.880 ;
END
END wd_in[36]
PIN wd_in[37]
......@@ -1496,7 +920,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 45.312 0.005 45.317 ;
RECT 0.000 24.096 0.024 24.120 ;
END
END wd_in[37]
PIN wd_in[38]
......@@ -1505,7 +929,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 45.504 0.005 45.509 ;
RECT 0.000 24.336 0.024 24.360 ;
END
END wd_in[38]
PIN wd_in[39]
......@@ -1514,7 +938,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 45.696 0.005 45.701 ;
RECT 0.000 24.576 0.024 24.600 ;
END
END wd_in[39]
PIN wd_in[40]
......@@ -1523,7 +947,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 45.888 0.005 45.893 ;
RECT 0.000 24.816 0.024 24.840 ;
END
END wd_in[40]
PIN wd_in[41]
......@@ -1532,7 +956,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 46.080 0.005 46.085 ;
RECT 0.000 25.056 0.024 25.080 ;
END
END wd_in[41]
PIN wd_in[42]
......@@ -1541,7 +965,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 46.272 0.005 46.277 ;
RECT 0.000 25.296 0.024 25.320 ;
END
END wd_in[42]
PIN wd_in[43]
......@@ -1550,7 +974,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 46.464 0.005 46.469 ;
RECT 0.000 25.536 0.024 25.560 ;
END
END wd_in[43]
PIN wd_in[44]
......@@ -1559,7 +983,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 46.656 0.005 46.661 ;
RECT 0.000 25.776 0.024 25.800 ;
END
END wd_in[44]
PIN wd_in[45]
......@@ -1568,7 +992,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 46.848 0.005 46.853 ;
RECT 0.000 26.016 0.024 26.040 ;
END
END wd_in[45]
PIN wd_in[46]
......@@ -1577,7 +1001,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 47.040 0.005 47.045 ;
RECT 0.000 26.256 0.024 26.280 ;
END
END wd_in[46]
PIN wd_in[47]
......@@ -1586,7 +1010,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 47.232 0.005 47.237 ;
RECT 0.000 26.496 0.024 26.520 ;
END
END wd_in[47]
PIN wd_in[48]
......@@ -1595,7 +1019,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 47.424 0.005 47.429 ;
RECT 0.000 26.736 0.024 26.760 ;
END
END wd_in[48]
PIN wd_in[49]
......@@ -1604,7 +1028,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 47.616 0.005 47.621 ;
RECT 0.000 26.976 0.024 27.000 ;
END
END wd_in[49]
PIN wd_in[50]
......@@ -1613,7 +1037,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 47.808 0.005 47.813 ;
RECT 0.000 27.216 0.024 27.240 ;
END
END wd_in[50]
PIN wd_in[51]
......@@ -1622,7 +1046,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 48.000 0.005 48.005 ;
RECT 0.000 27.456 0.024 27.480 ;
END
END wd_in[51]
PIN wd_in[52]
......@@ -1631,7 +1055,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 48.192 0.005 48.197 ;
RECT 0.000 27.696 0.024 27.720 ;
END
END wd_in[52]
PIN wd_in[53]
......@@ -1640,7 +1064,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 48.384 0.005 48.389 ;
RECT 0.000 27.936 0.024 27.960 ;
END
END wd_in[53]
PIN wd_in[54]
......@@ -1649,7 +1073,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 48.576 0.005 48.581 ;
RECT 0.000 28.176 0.024 28.200 ;
END
END wd_in[54]
PIN wd_in[55]
......@@ -1658,7 +1082,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 48.768 0.005 48.773 ;
RECT 0.000 28.416 0.024 28.440 ;
END
END wd_in[55]
PIN wd_in[56]
......@@ -1667,7 +1091,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 48.960 0.005 48.965 ;
RECT 0.000 28.656 0.024 28.680 ;
END
END wd_in[56]
PIN wd_in[57]
......@@ -1676,7 +1100,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 49.152 0.005 49.157 ;
RECT 0.000 28.896 0.024 28.920 ;
END
END wd_in[57]
PIN wd_in[58]
......@@ -1685,7 +1109,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 49.344 0.005 49.349 ;
RECT 0.000 29.136 0.024 29.160 ;
END
END wd_in[58]
PIN wd_in[59]
......@@ -1694,7 +1118,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 49.536 0.005 49.541 ;
RECT 0.000 29.376 0.024 29.400 ;
END
END wd_in[59]
PIN wd_in[60]
......@@ -1703,7 +1127,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 49.728 0.005 49.733 ;
RECT 0.000 29.616 0.024 29.640 ;
END
END wd_in[60]
PIN wd_in[61]
......@@ -1712,7 +1136,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 49.920 0.005 49.925 ;
RECT 0.000 29.856 0.024 29.880 ;
END
END wd_in[61]
PIN wd_in[62]
......@@ -1721,7 +1145,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 50.112 0.005 50.117 ;
RECT 0.000 30.096 0.024 30.120 ;
END
END wd_in[62]
PIN wd_in[63]
......@@ -1730,7 +1154,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 50.304 0.005 50.309 ;
RECT 0.000 30.336 0.024 30.360 ;
END
END wd_in[63]
PIN addr_in[0]
......@@ -1739,7 +1163,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 57.216 0.005 57.221 ;
RECT 0.000 30.384 0.024 30.408 ;
END
END addr_in[0]
PIN addr_in[1]
......@@ -1748,7 +1172,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 57.408 0.005 57.413 ;
RECT 0.000 30.624 0.024 30.648 ;
END
END addr_in[1]
PIN addr_in[2]
......@@ -1757,7 +1181,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 57.600 0.005 57.605 ;
RECT 0.000 30.864 0.024 30.888 ;
END
END addr_in[2]
PIN addr_in[3]
......@@ -1766,7 +1190,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 57.792 0.005 57.797 ;
RECT 0.000 31.104 0.024 31.128 ;
END
END addr_in[3]
PIN addr_in[4]
......@@ -1775,7 +1199,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 57.984 0.005 57.989 ;
RECT 0.000 31.344 0.024 31.368 ;
END
END addr_in[4]
PIN addr_in[5]
......@@ -1784,7 +1208,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 58.176 0.005 58.181 ;
RECT 0.000 31.584 0.024 31.608 ;
END
END addr_in[5]
PIN addr_in[6]
......@@ -1793,7 +1217,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 58.368 0.005 58.373 ;
RECT 0.000 31.824 0.024 31.848 ;
END
END addr_in[6]
PIN addr_in[7]
......@@ -1802,7 +1226,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 58.560 0.005 58.565 ;
RECT 0.000 32.064 0.024 32.088 ;
END
END addr_in[7]
PIN we_in
......@@ -1811,7 +1235,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 65.472 0.005 65.477 ;
RECT 0.000 32.112 0.024 32.136 ;
END
END we_in
PIN ce_in
......@@ -1820,7 +1244,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 65.664 0.005 65.669 ;
RECT 0.000 32.352 0.024 32.376 ;
END
END ce_in
PIN clk
......@@ -1829,7 +1253,7 @@ MACRO sram_asap7_64x256_1rw
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 65.856 0.005 65.861 ;
RECT 0.000 32.592 0.024 32.616 ;
END
END clk
PIN VSS
......@@ -1837,28 +1261,50 @@ MACRO sram_asap7_64x256_1rw
USE GROUND ;
PORT
LAYER M4 ;
RECT 0.192 0.182 8.168 0.202 ;
RECT 0.192 3.254 8.168 3.274 ;
RECT 0.192 6.326 8.168 6.346 ;
RECT 0.192 9.398 8.168 9.418 ;
RECT 0.192 12.470 8.168 12.490 ;
RECT 0.192 15.542 8.168 15.562 ;
RECT 0.192 18.614 8.168 18.634 ;
RECT 0.192 21.686 8.168 21.706 ;
RECT 0.192 24.758 8.168 24.778 ;
RECT 0.192 27.830 8.168 27.850 ;
RECT 0.192 30.902 8.168 30.922 ;
RECT 0.192 33.974 8.168 33.994 ;
RECT 0.192 37.046 8.168 37.066 ;
RECT 0.192 40.118 8.168 40.138 ;
RECT 0.192 43.190 8.168 43.210 ;
RECT 0.192 46.262 8.168 46.282 ;
RECT 0.192 49.334 8.168 49.354 ;
RECT 0.192 52.406 8.168 52.426 ;
RECT 0.192 55.478 8.168 55.498 ;
RECT 0.192 58.550 8.168 58.570 ;
RECT 0.192 61.622 8.168 61.642 ;
RECT 0.192 64.694 8.168 64.714 ;
RECT 0.048 0.000 16.672 0.096 ;
RECT 0.048 0.768 16.672 0.864 ;
RECT 0.048 1.536 16.672 1.632 ;
RECT 0.048 2.304 16.672 2.400 ;
RECT 0.048 3.072 16.672 3.168 ;
RECT 0.048 3.840 16.672 3.936 ;
RECT 0.048 4.608 16.672 4.704 ;
RECT 0.048 5.376 16.672 5.472 ;
RECT 0.048 6.144 16.672 6.240 ;
RECT 0.048 6.912 16.672 7.008 ;
RECT 0.048 7.680 16.672 7.776 ;
RECT 0.048 8.448 16.672 8.544 ;
RECT 0.048 9.216 16.672 9.312 ;
RECT 0.048 9.984 16.672 10.080 ;
RECT 0.048 10.752 16.672 10.848 ;
RECT 0.048 11.520 16.672 11.616 ;
RECT 0.048 12.288 16.672 12.384 ;
RECT 0.048 13.056 16.672 13.152 ;
RECT 0.048 13.824 16.672 13.920 ;
RECT 0.048 14.592 16.672 14.688 ;
RECT 0.048 15.360 16.672 15.456 ;
RECT 0.048 16.128 16.672 16.224 ;
RECT 0.048 16.896 16.672 16.992 ;
RECT 0.048 17.664 16.672 17.760 ;
RECT 0.048 18.432 16.672 18.528 ;
RECT 0.048 19.200 16.672 19.296 ;
RECT 0.048 19.968 16.672 20.064 ;
RECT 0.048 20.736 16.672 20.832 ;
RECT 0.048 21.504 16.672 21.600 ;
RECT 0.048 22.272 16.672 22.368 ;
RECT 0.048 23.040 16.672 23.136 ;
RECT 0.048 23.808 16.672 23.904 ;
RECT 0.048 24.576 16.672 24.672 ;
RECT 0.048 25.344 16.672 25.440 ;
RECT 0.048 26.112 16.672 26.208 ;
RECT 0.048 26.880 16.672 26.976 ;
RECT 0.048 27.648 16.672 27.744 ;
RECT 0.048 28.416 16.672 28.512 ;
RECT 0.048 29.184 16.672 29.280 ;
RECT 0.048 29.952 16.672 30.048 ;
RECT 0.048 30.720 16.672 30.816 ;
RECT 0.048 31.488 16.672 31.584 ;
RECT 0.048 32.256 16.672 32.352 ;
RECT 0.048 33.024 16.672 33.120 ;
END
END VSS
PIN VDD
......@@ -1866,291 +1312,357 @@ MACRO sram_asap7_64x256_1rw
USE POWER ;
PORT
LAYER M4 ;
RECT 0.192 1.718 8.168 1.738 ;
RECT 0.192 4.790 8.168 4.810 ;
RECT 0.192 7.862 8.168 7.882 ;
RECT 0.192 10.934 8.168 10.954 ;
RECT 0.192 14.006 8.168 14.026 ;
RECT 0.192 17.078 8.168 17.098 ;
RECT 0.192 20.150 8.168 20.170 ;
RECT 0.192 23.222 8.168 23.242 ;
RECT 0.192 26.294 8.168 26.314 ;
RECT 0.192 29.366 8.168 29.386 ;
RECT 0.192 32.438 8.168 32.458 ;
RECT 0.192 35.510 8.168 35.530 ;
RECT 0.192 38.582 8.168 38.602 ;
RECT 0.192 41.654 8.168 41.674 ;
RECT 0.192 44.726 8.168 44.746 ;
RECT 0.192 47.798 8.168 47.818 ;
RECT 0.192 50.870 8.168 50.890 ;
RECT 0.192 53.942 8.168 53.962 ;
RECT 0.192 57.014 8.168 57.034 ;
RECT 0.192 60.086 8.168 60.106 ;
RECT 0.192 63.158 8.168 63.178 ;
RECT 0.192 66.230 8.168 66.250 ;
RECT 0.048 0.384 16.672 0.480 ;
RECT 0.048 1.152 16.672 1.248 ;
RECT 0.048 1.920 16.672 2.016 ;
RECT 0.048 2.688 16.672 2.784 ;
RECT 0.048 3.456 16.672 3.552 ;
RECT 0.048 4.224 16.672 4.320 ;
RECT 0.048 4.992 16.672 5.088 ;
RECT 0.048 5.760 16.672 5.856 ;
RECT 0.048 6.528 16.672 6.624 ;
RECT 0.048 7.296 16.672 7.392 ;
RECT 0.048 8.064 16.672 8.160 ;
RECT 0.048 8.832 16.672 8.928 ;
RECT 0.048 9.600 16.672 9.696 ;
RECT 0.048 10.368 16.672 10.464 ;
RECT 0.048 11.136 16.672 11.232 ;
RECT 0.048 11.904 16.672 12.000 ;
RECT 0.048 12.672 16.672 12.768 ;
RECT 0.048 13.440 16.672 13.536 ;
RECT 0.048 14.208 16.672 14.304 ;
RECT 0.048 14.976 16.672 15.072 ;
RECT 0.048 15.744 16.672 15.840 ;
RECT 0.048 16.512 16.672 16.608 ;
RECT 0.048 17.280 16.672 17.376 ;
RECT 0.048 18.048 16.672 18.144 ;
RECT 0.048 18.816 16.672 18.912 ;
RECT 0.048 19.584 16.672 19.680 ;
RECT 0.048 20.352 16.672 20.448 ;
RECT 0.048 21.120 16.672 21.216 ;
RECT 0.048 21.888 16.672 21.984 ;
RECT 0.048 22.656 16.672 22.752 ;
RECT 0.048 23.424 16.672 23.520 ;
RECT 0.048 24.192 16.672 24.288 ;
RECT 0.048 24.960 16.672 25.056 ;
RECT 0.048 25.728 16.672 25.824 ;
RECT 0.048 26.496 16.672 26.592 ;
RECT 0.048 27.264 16.672 27.360 ;
RECT 0.048 28.032 16.672 28.128 ;
RECT 0.048 28.800 16.672 28.896 ;
RECT 0.048 29.568 16.672 29.664 ;
RECT 0.048 30.336 16.672 30.432 ;
RECT 0.048 31.104 16.672 31.200 ;
RECT 0.048 31.872 16.672 31.968 ;
RECT 0.048 32.640 16.672 32.736 ;
RECT 0.048 33.408 16.672 33.504 ;
END
END VDD
OBS
LAYER M1 ;
RECT 0 0 8.360 67.200 ;
RECT 0 0 16.720 33.600 ;
LAYER M2 ;
RECT 0 0 8.360 67.200 ;
RECT 0 0 16.720 33.600 ;
LAYER M3 ;
RECT 0 0 8.360 67.200 ;
RECT 0 0 16.720 33.600 ;
LAYER M4 ;
RECT 0.005 0 0.192 67.200 ;
RECT 8.168 0 8.360 67.200 ;
RECT 0.192 0.000 8.168 0.182 ;
RECT 0.192 0.202 8.168 1.718 ;
RECT 0.192 1.738 8.168 3.254 ;
RECT 0.192 3.274 8.168 4.790 ;
RECT 0.192 4.810 8.168 6.326 ;
RECT 0.192 6.346 8.168 7.862 ;
RECT 0.192 7.882 8.168 9.398 ;
RECT 0.192 9.418 8.168 10.934 ;
RECT 0.192 10.954 8.168 12.470 ;
RECT 0.192 12.490 8.168 14.006 ;
RECT 0.192 14.026 8.168 15.542 ;
RECT 0.192 15.562 8.168 17.078 ;
RECT 0.192 17.098 8.168 18.614 ;
RECT 0.192 18.634 8.168 20.150 ;
RECT 0.192 20.170 8.168 21.686 ;
RECT 0.192 21.706 8.168 23.222 ;
RECT 0.192 23.242 8.168 24.758 ;
RECT 0.192 24.778 8.168 26.294 ;
RECT 0.192 26.314 8.168 27.830 ;
RECT 0.192 27.850 8.168 29.366 ;
RECT 0.192 29.386 8.168 30.902 ;
RECT 0.192 30.922 8.168 32.438 ;
RECT 0.192 32.458 8.168 33.974 ;
RECT 0.192 33.994 8.168 35.510 ;
RECT 0.192 35.530 8.168 37.046 ;
RECT 0.192 37.066 8.168 38.582 ;
RECT 0.192 38.602 8.168 40.118 ;
RECT 0.192 40.138 8.168 41.654 ;
RECT 0.192 41.674 8.168 43.190 ;
RECT 0.192 43.210 8.168 44.726 ;
RECT 0.192 44.746 8.168 46.262 ;
RECT 0.192 46.282 8.168 47.798 ;
RECT 0.192 47.818 8.168 49.334 ;
RECT 0.192 49.354 8.168 50.870 ;
RECT 0.192 50.890 8.168 52.406 ;
RECT 0.192 52.426 8.168 53.942 ;
RECT 0.192 53.962 8.168 55.478 ;
RECT 0.192 55.498 8.168 57.014 ;
RECT 0.192 57.034 8.168 58.550 ;
RECT 0.192 58.570 8.168 60.086 ;
RECT 0.192 60.106 8.168 61.622 ;
RECT 0.192 61.642 8.168 63.158 ;
RECT 0.192 63.178 8.168 64.694 ;
RECT 0.192 64.714 8.168 66.230 ;
RECT 0.192 66.250 8.168 67.200 ;
RECT 0 0.000 0.005 0.192 ;
RECT 0 0.197 0.005 0.384 ;
RECT 0 0.389 0.005 0.576 ;
RECT 0 0.581 0.005 0.768 ;
RECT 0 0.773 0.005 0.960 ;
RECT 0 0.965 0.005 1.152 ;
RECT 0 1.157 0.005 1.344 ;
RECT 0 1.349 0.005 1.536 ;
RECT 0 1.541 0.005 1.728 ;
RECT 0 1.733 0.005 1.920 ;
RECT 0 1.925 0.005 2.112 ;
RECT 0 2.117 0.005 2.304 ;
RECT 0 2.309 0.005 2.496 ;
RECT 0 2.501 0.005 2.688 ;
RECT 0 2.693 0.005 2.880 ;
RECT 0 2.885 0.005 3.072 ;
RECT 0 3.077 0.005 3.264 ;
RECT 0 3.269 0.005 3.456 ;
RECT 0 3.461 0.005 3.648 ;
RECT 0 3.653 0.005 3.840 ;
RECT 0 3.845 0.005 4.032 ;
RECT 0 4.037 0.005 4.224 ;
RECT 0 4.229 0.005 4.416 ;
RECT 0 4.421 0.005 4.608 ;
RECT 0 4.613 0.005 4.800 ;
RECT 0 4.805 0.005 4.992 ;
RECT 0 4.997 0.005 5.184 ;
RECT 0 5.189 0.005 5.376 ;
RECT 0 5.381 0.005 5.568 ;
RECT 0 5.573 0.005 5.760 ;
RECT 0 5.765 0.005 5.952 ;
RECT 0 5.957 0.005 6.144 ;
RECT 0 6.149 0.005 6.336 ;
RECT 0 6.341 0.005 6.528 ;
RECT 0 6.533 0.005 6.720 ;
RECT 0 6.725 0.005 6.912 ;
RECT 0 6.917 0.005 7.104 ;
RECT 0 7.109 0.005 7.296 ;
RECT 0 7.301 0.005 7.488 ;
RECT 0 7.493 0.005 7.680 ;
RECT 0 7.685 0.005 7.872 ;
RECT 0 7.877 0.005 8.064 ;
RECT 0 8.069 0.005 8.256 ;
RECT 0 8.261 0.005 8.448 ;
RECT 0 8.453 0.005 8.640 ;
RECT 0 8.645 0.005 8.832 ;
RECT 0 8.837 0.005 9.024 ;
RECT 0 9.029 0.005 9.216 ;
RECT 0 9.221 0.005 9.408 ;
RECT 0 9.413 0.005 9.600 ;
RECT 0 9.605 0.005 9.792 ;
RECT 0 9.797 0.005 9.984 ;
RECT 0 9.989 0.005 10.176 ;
RECT 0 10.181 0.005 10.368 ;
RECT 0 10.373 0.005 10.560 ;
RECT 0 10.565 0.005 10.752 ;
RECT 0 10.757 0.005 10.944 ;
RECT 0 10.949 0.005 11.136 ;
RECT 0 11.141 0.005 11.328 ;
RECT 0 11.333 0.005 11.520 ;
RECT 0 11.525 0.005 11.712 ;
RECT 0 11.717 0.005 11.904 ;
RECT 0 11.909 0.005 12.096 ;
RECT 0 12.101 0.005 12.288 ;
RECT 0 12.293 0.005 19.200 ;
RECT 0 19.205 0.005 19.392 ;
RECT 0 19.397 0.005 19.584 ;
RECT 0 19.589 0.005 19.776 ;
RECT 0 19.781 0.005 19.968 ;
RECT 0 19.973 0.005 20.160 ;
RECT 0 20.165 0.005 20.352 ;
RECT 0 20.357 0.005 20.544 ;
RECT 0 20.549 0.005 20.736 ;
RECT 0 20.741 0.005 20.928 ;
RECT 0 20.933 0.005 21.120 ;
RECT 0 21.125 0.005 21.312 ;
RECT 0 21.317 0.005 21.504 ;
RECT 0 21.509 0.005 21.696 ;
RECT 0 21.701 0.005 21.888 ;
RECT 0 21.893 0.005 22.080 ;
RECT 0 22.085 0.005 22.272 ;
RECT 0 22.277 0.005 22.464 ;
RECT 0 22.469 0.005 22.656 ;
RECT 0 22.661 0.005 22.848 ;
RECT 0 22.853 0.005 23.040 ;
RECT 0 23.045 0.005 23.232 ;
RECT 0 23.237 0.005 23.424 ;
RECT 0 23.429 0.005 23.616 ;
RECT 0 23.621 0.005 23.808 ;
RECT 0 23.813 0.005 24.000 ;
RECT 0 24.005 0.005 24.192 ;
RECT 0 24.197 0.005 24.384 ;
RECT 0 24.389 0.005 24.576 ;
RECT 0 24.581 0.005 24.768 ;
RECT 0 24.773 0.005 24.960 ;
RECT 0 24.965 0.005 25.152 ;
RECT 0 25.157 0.005 25.344 ;
RECT 0 25.349 0.005 25.536 ;
RECT 0 25.541 0.005 25.728 ;
RECT 0 25.733 0.005 25.920 ;
RECT 0 25.925 0.005 26.112 ;
RECT 0 26.117 0.005 26.304 ;
RECT 0 26.309 0.005 26.496 ;
RECT 0 26.501 0.005 26.688 ;
RECT 0 26.693 0.005 26.880 ;
RECT 0 26.885 0.005 27.072 ;
RECT 0 27.077 0.005 27.264 ;
RECT 0 27.269 0.005 27.456 ;
RECT 0 27.461 0.005 27.648 ;
RECT 0 27.653 0.005 27.840 ;
RECT 0 27.845 0.005 28.032 ;
RECT 0 28.037 0.005 28.224 ;
RECT 0 28.229 0.005 28.416 ;
RECT 0 28.421 0.005 28.608 ;
RECT 0 28.613 0.005 28.800 ;
RECT 0 28.805 0.005 28.992 ;
RECT 0 28.997 0.005 29.184 ;
RECT 0 29.189 0.005 29.376 ;
RECT 0 29.381 0.005 29.568 ;
RECT 0 29.573 0.005 29.760 ;
RECT 0 29.765 0.005 29.952 ;
RECT 0 29.957 0.005 30.144 ;
RECT 0 30.149 0.005 30.336 ;
RECT 0 30.341 0.005 30.528 ;
RECT 0 30.533 0.005 30.720 ;
RECT 0 30.725 0.005 30.912 ;
RECT 0 30.917 0.005 31.104 ;
RECT 0 31.109 0.005 31.296 ;
RECT 0 31.301 0.005 38.208 ;
RECT 0 38.213 0.005 38.400 ;
RECT 0 38.405 0.005 38.592 ;
RECT 0 38.597 0.005 38.784 ;
RECT 0 38.789 0.005 38.976 ;
RECT 0 38.981 0.005 39.168 ;
RECT 0 39.173 0.005 39.360 ;
RECT 0 39.365 0.005 39.552 ;
RECT 0 39.557 0.005 39.744 ;
RECT 0 39.749 0.005 39.936 ;
RECT 0 39.941 0.005 40.128 ;
RECT 0 40.133 0.005 40.320 ;
RECT 0 40.325 0.005 40.512 ;
RECT 0 40.517 0.005 40.704 ;
RECT 0 40.709 0.005 40.896 ;
RECT 0 40.901 0.005 41.088 ;
RECT 0 41.093 0.005 41.280 ;
RECT 0 41.285 0.005 41.472 ;
RECT 0 41.477 0.005 41.664 ;
RECT 0 41.669 0.005 41.856 ;
RECT 0 41.861 0.005 42.048 ;
RECT 0 42.053 0.005 42.240 ;
RECT 0 42.245 0.005 42.432 ;
RECT 0 42.437 0.005 42.624 ;
RECT 0 42.629 0.005 42.816 ;
RECT 0 42.821 0.005 43.008 ;
RECT 0 43.013 0.005 43.200 ;
RECT 0 43.205 0.005 43.392 ;
RECT 0 43.397 0.005 43.584 ;
RECT 0 43.589 0.005 43.776 ;
RECT 0 43.781 0.005 43.968 ;
RECT 0 43.973 0.005 44.160 ;
RECT 0 44.165 0.005 44.352 ;
RECT 0 44.357 0.005 44.544 ;
RECT 0 44.549 0.005 44.736 ;
RECT 0 44.741 0.005 44.928 ;
RECT 0 44.933 0.005 45.120 ;
RECT 0 45.125 0.005 45.312 ;
RECT 0 45.317 0.005 45.504 ;
RECT 0 45.509 0.005 45.696 ;
RECT 0 45.701 0.005 45.888 ;
RECT 0 45.893 0.005 46.080 ;
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LAYER OVERLAP ;
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RECT 0 0 16.720 33.600 ;
END
END sram_asap7_64x256_1rw
......
Enablements/ASAP7/lib/sram_asap7_64x256_1rw.lib
......@@ -2,7 +2,7 @@ library(sram_asap7_64x256_1rw) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2022-06-13 17:29:18Z";
date : "2022-07-02 07:14:59Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
......@@ -383,77 +383,6 @@ cell(sram_asap7_64x256_1rw) {
}
}
}
bus(w_mask_in) {
bus_type : sram_asap7_64x256_1rw_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 0.005;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
fall_constraint(sram_asap7_64x256_1rw_constraint_template) {
index_1 ("0.009, 0.227");
index_2 ("0.009, 0.227");
values ( \
"0.050, 0.050", \
"0.050, 0.050" \
)
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
internal_power(){
when : "(we_in)";
rise_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
fall_power(sram_asap7_64x256_1rw_energy_template_sigslew) {
index_1 ("0.009, 0.227");
values ("0.013, 0.013")
}
}
}
cell_leakage_power : 128.900;
}
......
Enablements/SKY130HD/README.md
# SKY130HD FakeStack (SKY130HD library, bsg_fakeram memory generation, 9M FkaeStack)
The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases. In this enablement each of the five routing layers and four cut layers has different lef properties (.e.g, minimum spacing, width, enclosure, etc.).
The SKY130HD enablement available in the OpenROAD-flow-script [GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd) is a five-metal stack enablement. However, memory macro has blockage till metal four, so a five-metal stack is not enough to route our macro dominant testcases.
Consider the five metal stacks are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as our one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x1Ma_x2Mb_x3Mc_x4Md_1Me, where xi is greater or equal to one.
In this enablement each of the five routing layers and four cut layers has different lef properties (.e.g, minimum spacing, width, enclosure, etc.). Consider the five layrs of the metal stack are Ma, Mb, Mc, Md and Me, and the stack configuration is named as 1Ma_1Mb_1Mc_1Md_1Me. We replicate the first four metal layers to generate the nine-metal layer FakeStack where the configuration is 2Ma_2Mb_2Mc_2Md_1Me. We use this nine-metal layer FakeStack of SKY130HD as our one of the enablements. The [getTechLef.tcl](./lef/genTechLef.tcl) can be used to generate a FakeStack of layer configuration x<sub>1</sub>Ma_x<sub>2</sub>Mb_x<sub>3</sub>Mc_x<sub>4</sub>Md_1Me, where x<sub>i</sub> is greater or equal to one.
We use the bsg_fakeram memory generator available in the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) GitHub repo to generate the required SRAMs. The [sky130hd.cfg](./util/sky130hd.cfg) is the configuration file used to generate all the required memories.
......
Flows/ASAP7/nvdla/README.md 0 → 100644
# **Synthesis, Place \& Route (SP\&R):**
Here we provide the setup to run SP&R of NVDLA design with 128 memory macros on ASAP7 using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
## **SP\&R Flow:**
We implement [NVDLA](../../../Testcases/nvdla/) on the ASAP7 platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/asap7). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the ASAP7 platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/ASAP7*](../../../Enablements/ASAP7/) directory.
### **Using Cadence Genus and Innovus:**
All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.
**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
```
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
```
We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow.
<img src="./screenshots/nvdla_Innovus_asap7.png" alt="nvdla_cadence" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
<!--
### **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:
1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the below command
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
```
4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.
<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
-->
\ No newline at end of file
Flows/ASAP7/nvdla/constraints/NV_NVDLA_partition_c.sdc 0 → 100644
# ===================================================================
# File: syn/cons/NV_NVDLA_partition_c.sdc
# NVDLA Open Source Project
#
# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the
# NVDLA Open Hardware License; see the "LICENSE.txt" file that came
# with this distribution for more information.
# ===================================================================
set_max_area 0
set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
set_ideal_network [get_ports test_mode]
create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45}
set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
set_false_path -from [get_ports direct_reset_]
set_false_path -from [get_ports dla_reset_rstn]
set_false_path -from [get_ports test_mode]
set_false_path -from [get_ports pwrbus_ram_pd*]
set_false_path -from [get_ports tmc2slcg_disable_clock_gating]
set_false_path -from [get_ports global_clk_ovr_on]
set_false_path -from [get_ports nvdla_clk_ovr_on]
Flows/ASAP7/nvdla/def/NV_NVDLA_partition_c_fp.def 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Flows/ASAP7/nvdla/scripts/cadence/design_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
set DESIGN NV_NVDLA_partition_c
set sdc ../../constraints/${DESIGN}.sdc
# def file with die size and placed IO pins
set floorplan_def ../../def/${DESIGN}_fp.def
set rtl_path ../../../../../Testcases/nvdla/rtl/
#
# Effort level during optimization in syn_generic -physical (or called generic) stage
# possible values are : high, medium or low
set GEN_EFF medium
# Effort level during optimization in syn_map -physical (or called mapping) stage
# possible values are : high, medium or low
set MAP_EFF high
Flows/ASAP7/nvdla/scripts/cadence/gen_mp_config.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
puts "VERSION 1.0"
set mem_hier ""
foreach a [dbget [dbget top.insts.cell.name fakeram45_* -p2 ].name ] {
regexp {(.*)(/)([^/]*)} $a c b
lappend mem_hier $b
}
set unique_mem_hier [lsort -unique $mem_hier]
puts "BEGIN SEED"
foreach a $unique_mem_hier {
puts "name=$a util=$util"
}
puts "END SEED"
puts "BEGIN MACRO"
foreach a [dbget top.insts.cell.name fakeram45_* -u] {
puts "name=$a orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5"
}
puts "END MACRO"
puts "BEGIN CONSTRAINT"
puts "END CONSTRAINT"
Flows/ASAP7/nvdla/scripts/cadence/lib_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
# lib and lef, RC setup
set libdir "../../../../../Enablements/ASAP7/lib"
set lefdir "../../../../../Enablements/ASAP7/lef"
set qrcdir "../../../../../Enablements/ASAP7/qrc"
set_db init_lib_search_path { \
${libdir} \
${lefdir} \
}
set libworst [glob ${libdir}/*.lib]
set libbest $libworst
set lefs "
${lefdir}/asap7_tech_1x_201209.lef \
${lefdir}/asap7sc7p5t_27_R_1x_201211.lef \
${lefdir}/sram_asap7_64x256_1rw.lef \
"
set qrc_max "${qrcdir}/ASAP7.tch"
set qrc_min "${qrcdir}/ASAP7.tch"
#
# Ensures proper and consistent library handling between Genus and Innovus
#set_db library_setup_ispatial true
Flows/ASAP7/nvdla/scripts/cadence/mmmc_iSpatial_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
create_timing_condition -name timing_wc -library_sets { WC_LIB }
create_timing_condition -name timing_bc -library_sets { BC_LIB }
create_rc_corner -name Cmax -qrc_tech $qrc_max
create_rc_corner -name Cmin -qrc_tech $qrc_min
create_delay_corner -name WC -early_timing_condition { timing_wc } \
-late_timing_condition { timing_wc } \
-early_rc_corner Cmax \
-late_rc_corner Cmax
create_delay_corner -name BC -early_timing_condition { timing_bc } \
-late_timing_condition { timing_bc } \
-early_rc_corner Cmin \
-late_rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
set_analysis_view -setup WC_VIEW -hold BC_VIEW
Flows/ASAP7/nvdla/scripts/cadence/mmmc_setup.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
create_library_set -name WC_LIB -timing $libworst
create_library_set -name BC_LIB -timing $libbest
create_rc_corner -name Cmax -qx_tech_file $qrc_max
create_rc_corner -name Cmin -qx_tech_file $qrc_min
create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
create_constraint_mode -name CON -sdc_file $sdc
create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
Flows/ASAP7/nvdla/scripts/cadence/mp_config.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
##########################################
# Masterplan User Constraint File Template
##########################################
###########################################################
# Syntax Convention: #
# [] means optional #
# <> means filling with real value or name in your design #
# () indicates the unit name for your value #
# | means OR #
# {} is used to enclose a group of names (one or more) #
# ... means more similar items #
###########################################################
###########################################################
# Version section (required on and after Innovus 10.1) #
# If not provided, will be parsed as older format #
# VERSION <N.N> #
# For example: #
###########################################################
VERSION 1.0
######################################################################
# Seed Section (optional) : one single line per seed #
# name=<seedName> [util=<float>] [createFence=true]\ #
# [minWHRatio=<float>] [maxWHRatio=<float>]\ #
# [minFenceToFenceSpace=<(um)>] [minFenceToCoreSpace=<(um)>]\ #
# [minFenceToInsideMacroSpace=<(um)>]\ #
# [minFenceToOutsideMacroSpace=<(um)>]\ #
# [minInsideFenceMacroToMacroSpace=<(um)>]\ #
# [master=<nameOrOtherName>] [cloneOrient={R0|MX|MY|R180}] #
# For example: #
######################################################################
BEGIN SEED
name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_0__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_1__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_2__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_icache/sram_block_3__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_0__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_1__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_2__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_3__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_4__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_5__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_6__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_1__i_ram
name=i_cache_subsystem/i_nbdcache/sram_block_7__tag_sram/genblk1_0__i_ram
name=i_cache_subsystem/i_nbdcache/valid_dirty_sram/genblk1_0__i_ram
END SEED
######################################################################
# MACRO section syntax : one single line per macro #
# name=<InstOrCell> [minLeftSpace=<(um)>] [minRightSpace=<(um)>]\ #
# [minTopSpace=<(um)>] [minBottomSpace=<(um)>]\ #
# [orient={R0|MX|MY|R180|MX90|R90|R270|MY90}]\ #
# [isCell=true] [minMacroToCoreSpace=<(um)>] #
# For example: #
######################################################################
BEGIN MACRO
name=fakeram45_256x16 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
END MACRO
#################################################################################
# relative placement CONSTRAINT section syntax #
# name=<HInstOrGroupOrHM> loc=<T|B|R|L|TL|TR|BL|BR|(x,y)> #
# name=<NewName> members={<Module1> <Module2> <Module3>..} [strength=Soft|Hard] #
# For example: #
#################################################################################
BEGIN CONSTRAINT
END CONSTRAINT
Flows/ASAP7/nvdla/scripts/cadence/rtl_list.tcl 0 → 100644
#-y nv_small/src
#+incdir+nv_small/src
+libext+.v
+libext+.sv
+libext+.gv
+define+DISABLE_TESTPOINTS
+define+NV_SYNTHESIS
//+define+RAM_INTERFACE
NV_nvdla.v
NV_NVDLA_apb2csb.v
NV_NVDLA_partition_c.v
NV_NVDLA_partition_a.v
NV_NVDLA_partition_p.v
NV_NVDLA_partition_o.v
NV_NVDLA_partition_m.v
NV_NVDLA_CFGROM_rom.v
NV_NVDLA_sync3d.v
NV_NVDLA_cfgrom.v
NV_NVDLA_glb.v
NV_NVDLA_core_reset.v
NV_NVDLA_sync3d_s.v
NV_NVDLA_mcif.v
NV_NVDLA_cdp.v
NV_NVDLA_csb_master.v
NV_NVDLA_pdp.v
NV_NVDLA_reset.v
NV_NVDLA_PDP_rdma.v
NV_NVDLA_CDP_rdma.v
NV_NVDLA_CDP_DP_nan.v
NV_NVDLA_PDP_slcg.v
NV_NVDLA_PDP_core.v
NV_NVDLA_CDP_slcg.v
NV_NVDLA_MCIF_csb.v
NV_NVDLA_PDP_nan.v
NV_NVDLA_CDP_wdma.v
NV_NVDLA_PDP_wdma.v
NV_NVDLA_PDP_reg.v
NV_NVDLA_GLB_ic.v
NV_NVDLA_CDP_reg.v
NV_NVDLA_GLB_csb.v
NV_NVDLA_CDP_dp.v
NV_NVDLA_MCIF_read.v
NV_NVDLA_MCIF_write.v
NV_NVDLA_MCIF_CSB_reg.v
NV_NVDLA_MCIF_WRITE_ig.v
NV_NVDLA_MCIF_READ_ig.v
NV_NVDLA_MCIF_WRITE_cq.v
NV_NVDLA_MCIF_READ_eg.v
NV_NVDLA_MCIF_WRITE_eg.v
NV_NVDLA_MCIF_READ_IG_arb.v
NV_NVDLA_MCIF_READ_IG_bpt.v
NV_NVDLA_MCIF_READ_IG_cvt.v
NV_NVDLA_MCIF_WRITE_IG_bpt.v
NV_NVDLA_MCIF_WRITE_IG_cvt.v
NV_NVDLA_MCIF_WRITE_IG_arb.v
NV_CLK_gate_power.v
CKLNQD12.v
CKLNQD12PO4.v
NV_BLKBOX_SRC0_X.v
AN2D4PO4.v
NV_NVDLA_CDP_RDMA_eg.v
NV_NVDLA_CDP_DP_cvtout.v
NV_NVDLA_CDP_DP_sum.v
NV_NVDLA_CDP_RDMA_ig.v
NV_NVDLA_CDP_DP_lut.v
NV_NVDLA_CDP_DP_LUT_ctrl.v
NV_NVDLA_CDP_REG_single.v
NV_NVDLA_CDP_RDMA_reg.v
NV_NVDLA_CDP_DP_cvtin.v
NV_NVDLA_CDP_RDMA_cq.v
NV_NVDLA_CDP_DP_bufferin_tp1.v
NV_NVDLA_CDP_DP_mul.v
NV_NVDLA_CDP_REG_dual.v
NV_NVDLA_CDP_DP_syncfifo.v
NV_NVDLA_CDP_DP_intp.v
NV_NVDLA_CDP_DP_LUT_CTRL_unit.v
NV_NVDLA_CDP_DP_INTP_unit.v
NV_NVDLA_CDP_DP_MUL_unit.v
sync_reset.v
NV_BLKBOX_SRC0.v
OR2D1.v
p_SSYNC2DO_C_PP.v
MUX2D4.v
MUX2HDD2.v
sync3d_s_ppp.v
sync3d.v
p_SSYNC3DO_S_PPP.v
p_SSYNC3DO.v
NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v
NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
oneHotClk_async_read_clock.v
p_STRICTSYNC3DOTM_C_PPP.v
oneHotClk_async_write_clock.v
p_SSYNC3DO_C_PPP.v
NV_NVDLA_XXIF_libs.v
NV_NVDLA_DMAIF_rdreq.v
NV_BLKBOX_SINK.v
NV_NVDLA_CDP_RDMA_lat_fifo.v
NV_NVDLA_CDP_RDMA_REG_single.v
NV_NVDLA_CDP_RDMA_ro_fifo.v
NV_NVDLA_CDP_RDMA_REG_dual.v
NV_NVDLA_DMAIF_rdrsp.v
NV_NVDLA_CDP_WDMA_dat_fifo.v
NV_NVDLA_DMAIF_wr.v
HLS_cdp_ocvt.v
HLS_cdp_icvt.v
NV_NVDLA_CDP_DP_data_fifo.v
NV_NVDLA_CDP_DP_intpinfo_fifo.v
NV_NVDLA_CDP_DP_sumpd_fifo.v
int_sum_block_tp1.v
NV_NVDLA_HLS_shiftrightsu.v
NV_NVDLA_PDP_CORE_preproc.v
NV_NVDLA_PDP_WDMA_dat.v
NV_NVDLA_PDP_CORE_cal2d.v
NV_NVDLA_PDP_RDMA_cq.v
NV_NVDLA_PDP_CORE_cal1d.v
NV_NVDLA_PDP_RDMA_REG_single.v
NV_NVDLA_PDP_RDMA_eg.v
NV_NVDLA_PDP_WDMA_cmd.v
NV_NVDLA_PDP_REG_dual.v
NV_NVDLA_PDP_REG_single.v
NV_NVDLA_PDP_RDMA_REG_dual.v
NV_NVDLA_PDP_RDMA_ig.v
NV_NVDLA_PDP_RDMA_reg.v
NV_NVDLA_PDP_RDMA_lat_fifo.v
NV_NVDLA_PDP_RDMA_ro_fifo.v
NV_NVDLA_PDP_WDMA_DAT_fifo.v
NV_NVDLA_PDP_CORE_unit1d.v
NV_NVDLA_GLB_CSB_reg.v
NV_NVDLA_sync3d_c.v
sync3d_c_ppp.v
NV_NVDLA_cdma.v
NV_NVDLA_csc.v
NV_NVDLA_cbuf.v
NV_NVDLA_CDMA_status.v
NV_NVDLA_CDMA_regfile.v
NV_NVDLA_CDMA_cvt.v
NV_NVDLA_CDMA_dc.v
NV_NVDLA_CDMA_dma_mux.v
NV_NVDLA_CDMA_shared_buffer.v
NV_NVDLA_CDMA_img.v
NV_NVDLA_CDMA_slcg.v
NV_NVDLA_CDMA_wt.v
NV_NVDLA_CDMA_WT_8ATMM_fifo.v
NV_NVDLA_CDMA_CVT_cell.v
NV_NVDLA_CDMA_IMG_ctrl.v
NV_NVDLA_CDMA_IMG_pack.v
NV_NVDLA_CDMA_IMG_sg.v
NV_NVDLA_CDMA_single_reg.v
NV_NVDLA_CDMA_WT_fifo.v
NV_NVDLA_CDMA_dual_reg.v
NV_NVDLA_CDMA_DC_fifo.v
NV_NVDLA_HLS_saturate.v
NV_NVDLA_CDMA_IMG_fifo.v
NV_NVDLA_CDMA_IMG_sg2pack_fifo.v
NV_NVDLA_CSC_regfile.v
NV_NVDLA_CSC_wl.v
NV_NVDLA_CSC_WL_dec.v
NV_NVDLA_CSC_sg.v
NV_NVDLA_CSC_dl.v
NV_NVDLA_CSC_slcg.v
NV_NVDLA_CSC_SG_dat_fifo.v
NV_NVDLA_CSC_SG_wt_fifo.v
NV_NVDLA_CSC_dual_reg.v
NV_NVDLA_CSC_single_reg.v
NV_NVDLA_CACC_assembly_ctrl.v
NV_NVDLA_CACC_dual_reg.v
NV_NVDLA_CMAC_CORE_slcg.v
NV_NVDLA_CACC_assembly_buffer.v
NV_NVDLA_CACC_slcg.v
NV_NVDLA_cacc.v
NV_NVDLA_CACC_single_reg.v
NV_NVDLA_CACC_calculator.v
NV_NVDLA_CMAC_core.v
NV_NVDLA_CACC_delivery_buffer.v
NV_NVDLA_CACC_CALC_int8.v
NV_NVDLA_CACC_regfile.v
NV_NVDLA_CMAC_CORE_rt_in.v
NV_NVDLA_CMAC_REG_dual.v
NV_NVDLA_CACC_delivery_ctrl.v
NV_NVDLA_CMAC_reg.v
NV_NVDLA_cmac.v
NV_NVDLA_CMAC_CORE_active.v
NV_NVDLA_CMAC_CORE_cfg.v
NV_NVDLA_CMAC_CORE_mac.v
NV_NVDLA_CMAC_REG_single.v
NV_NVDLA_CMAC_CORE_rt_out.v
NV_NVDLA_sdp.v
NV_NVDLA_SDP_rdma.v
NV_NVDLA_SDP_wdma.v
NV_NVDLA_SDP_reg.v
NV_NVDLA_SDP_core.v
NV_NVDLA_SDP_HLS_x1_int.v
NV_NVDLA_SDP_WDMA_cmd.v
NV_NVDLA_SDP_RDMA_REG_dual.v
NV_NVDLA_SDP_RDMA_reg.v
NV_NVDLA_SDP_CORE_unpack.v
NV_NVDLA_SDP_REG_dual.v
NV_NVDLA_SDP_RDMA_pack.v
NV_NVDLA_SDP_WDMA_gate.v
NV_NVDLA_SDP_HLS_c.v
NV_NVDLA_SDP_nrdma.v
NV_NVDLA_SDP_WDMA_DAT_out.v
NV_NVDLA_SDP_CORE_pack.v
NV_NVDLA_SDP_WDMA_intr.v
NV_NVDLA_SDP_cmux.v
NV_NVDLA_SDP_CORE_gate.v
NV_NVDLA_SDP_WDMA_dat.v
NV_NVDLA_SDP_REG_single.v
NV_NVDLA_SDP_RDMA_REG_single.v
NV_NVDLA_SDP_brdma.v
NV_NVDLA_SDP_WDMA_DAT_in.v
NV_NVDLA_SDP_mrdma.v
NV_NVDLA_SDP_HLS_x2_int.v
NV_NVDLA_SDP_MRDMA_eg.v
NV_NVDLA_SDP_MRDMA_gate.v
NV_NVDLA_SDP_NRDMA_gate.v
NV_NVDLA_SDP_MRDMA_ig.v
NV_NVDLA_SDP_RDMA_ig.v
NV_NVDLA_SDP_RDMA_eg.v
NV_NVDLA_SDP_BRDMA_gate.v
NV_NVDLA_SDP_RDMA_dmaif.v
NV_NVDLA_SDP_HLS_X_int_relu.v
NV_NVDLA_SDP_HLS_C_int.v
NV_NVDLA_SDP_HLS_X_int_alu.v
NV_NVDLA_SDP_HLS_X_int_mul.v
NV_NVDLA_SDP_HLS_X_int_trt.v
NV_NVDLA_SDP_HLS_relu.v
NV_NVDLA_SDP_HLS_prelu.v
NV_NVDLA_SDP_HLS_sync2data.v
NV_NVDLA_HLS_shiftleftsu.v
NV_NVDLA_HLS_shiftrightsatsu.v
NV_NVDLA_SDP_NRDMA_cq_lib.v
NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v
NV_NVDLA_SDP_BRDMA_cq_lib.v
NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v
NV_NVDLA_SDP_MRDMA_cq_lib.v
NV_NVDLA_SDP_MRDMA_EG_din.v
NV_NVDLA_SDP_MRDMA_EG_dout.v
NV_NVDLA_SDP_MRDMA_EG_cmd.v
NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v
NV_NVDLA_SDP_RDMA_unpack.v
NV_NVDLA_SDP_RDMA_EG_ro.v
NV_BLKBOX_BUFFER.v
SDFQD1.v
RAMDP_128X6_GL_M2_E2.v
RAMDP_128X11_GL_M2_E2.v
RAMDP_16X64_GL_M1_E2.v
RAMPDP_256X64_GL_M2_D2.v
RAMDP_16X272_GL_M1_E2.v
RAMDP_16X66_GL_M1_E2.v
RAMDP_16X256_GL_M1_E2.v
RAMDP_16X14_GL_M1_E2.v
RAMDP_16X16_GL_M1_E2.v
ScanShareSel_JTAG_reg_ext_cg.v
sync2d_c_pp.v
p_SDFCNQD1PO4.v
RAMDP_256X4_GL_M2_E2.v
RAMDP_256X8_GL_M2_E2.v
RAMDP_8X66_GL_M1_E2.v
RAMDP_80X9_GL_M2_E2.v
RAMPDP_80X17_GL_M2_D2.v
RAMDP_60X22_GL_M1_E2.v
RAMPDP_128X18_GL_M2_D2.v
nv_ram_rws_128x18_logic.v
nv_ram_rws_128x256_logic.v
nv_ram_rws_128x64_logic.v
nv_ram_rws_16x256_logic.v
nv_ram_rws_16x272_logic.v
nv_ram_rws_16x64_logic.v
nv_ram_rws_256x3_logic.v
nv_ram_rws_256x512_logic.v
nv_ram_rws_256x64_logic.v
nv_ram_rws_256x7_logic.v
nv_ram_rws_32x16_logic.v
nv_ram_rws_32x512_logic.v
nv_ram_rws_32x544_logic.v
nv_ram_rws_32x768_logic.v
nv_ram_rws_512x256_logic.v
nv_ram_rws_512x512_logic.v
nv_ram_rws_512x64_logic.v
nv_ram_rws_64x1024_logic.v
nv_ram_rws_64x1088_logic.v
nv_ram_rws_64x10_logic.v
nv_ram_rws_64x116_logic.v
nv_ram_rws_64x18_logic.v
nv_ram_rwsp_128x11_logic.v
nv_ram_rwsp_128x6_logic.v
nv_ram_rwsp_160x16_logic.v
nv_ram_rwsp_160x514_logic.v
nv_ram_rwsp_160x65_logic.v
nv_ram_rwsp_16x14_logic.v
nv_ram_rwsp_16x16_logic.v
nv_ram_rwsp_16x65_logic.v
nv_ram_rwsp_20x289_logic.v
nv_ram_rwsp_245x514_logic.v
nv_ram_rwsp_256x11_logic.v
nv_ram_rwsp_32x32_logic.v
nv_ram_rwsp_61x514_logic.v
nv_ram_rwsp_61x64_logic.v
nv_ram_rwsp_61x65_logic.v
nv_ram_rwsp_80x14_logic.v
nv_ram_rwsp_80x16_logic.v
nv_ram_rwsp_80x256_logic.v
nv_ram_rwsp_80x514_logic.v
nv_ram_rwsp_80x65_logic.v
nv_ram_rwsp_8x65_logic.v
nv_ram_rwst_256x8_logic.v
nv_ram_rwsthp_19x32_logic.v
nv_ram_rwsthp_19x4_logic.v
nv_ram_rwsthp_19x80_logic.v
nv_ram_rwsthp_20x4_logic.v
nv_ram_rwsthp_60x168_logic.v
nv_ram_rwsthp_60x21_logic.v
nv_ram_rwsthp_80x15_logic.v
nv_ram_rwsthp_80x17_logic.v
nv_ram_rwsthp_80x72_logic.v
nv_ram_rwsthp_80x9_logic.v
nv_ram_rws_128x18.v
nv_ram_rws_128x256.v
nv_ram_rws_128x64.v
nv_ram_rws_16x256.v
nv_ram_rws_16x272.v
nv_ram_rws_16x64.v
nv_ram_rws_256x3.v
nv_ram_rws_256x512.v
nv_ram_rws_256x64.v
nv_ram_rws_256x7.v
nv_ram_rws_32x16.v
nv_ram_rws_32x512.v
nv_ram_rws_32x544.v
nv_ram_rws_32x768.v
nv_ram_rws_512x256.v
nv_ram_rws_512x512.v
nv_ram_rws_512x64.v
nv_ram_rws_64x1024.v
nv_ram_rws_64x1088.v
nv_ram_rws_64x10.v
nv_ram_rws_64x116.v
nv_ram_rws_64x18.v
nv_ram_rwsp_128x11.v
nv_ram_rwsp_128x6.v
nv_ram_rwsp_160x16.v
nv_ram_rwsp_160x514.v
nv_ram_rwsp_160x65.v
nv_ram_rwsp_16x14.v
nv_ram_rwsp_16x16.v
nv_ram_rwsp_16x65.v
nv_ram_rwsp_20x289.v
nv_ram_rwsp_245x514.v
nv_ram_rwsp_256x11.v
nv_ram_rwsp_32x32.v
nv_ram_rwsp_61x514.v
nv_ram_rwsp_61x64.v
nv_ram_rwsp_61x65.v
nv_ram_rwsp_80x14.v
nv_ram_rwsp_80x16.v
nv_ram_rwsp_80x256.v
nv_ram_rwsp_80x514.v
nv_ram_rwsp_80x65.v
nv_ram_rwsp_8x65.v
nv_ram_rwst_256x8.v
nv_ram_rwsthp_19x32.v
nv_ram_rwsthp_19x4.v
nv_ram_rwsthp_19x80.v
nv_ram_rwsthp_20x4.v
nv_ram_rwsthp_60x168.v
nv_ram_rwsthp_60x21.v
nv_ram_rwsthp_80x15.v
nv_ram_rwsthp_80x17.v
nv_ram_rwsthp_80x72.v
nv_ram_rwsthp_80x9.v
fakeram7_256x64_dp.v
-v NV_NVDLA_XXIF_libs.v
Flows/NanGate45/mempool_group/scripts/cadence/run → Flows/ASAP7/nvdla/scripts/cadence/run.sh
# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence.
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
#!/bin/tcsh
module unload genus
module load genus/21.1
module unload innovus
module load innovus/21.1
mkdir -p log
innovus -64 -init run_invs.tcl -log log/run.log
mkdir log -p
genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log
Flows/ASAP7/nvdla/scripts/cadence/run_genus.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
# Target library
set link_library $list_lib
set target_library $list_lib
# set path
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
set_db library $list_lib
set_db init_hdl_search_path [list . ../../../../../Testcases/nvdla/rtl/]
#################################################
# Load Design and Initialize
#################################################
read_hdl -f rtl_list.tcl
elaborate $DESIGN
time_info Elaboration
read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic
time_info GENERIC
# generate a summary for the current stage of synthesis
write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/ASAP7/nvdla/scripts/cadence/run_genus_iSpatial.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
read_mmmc mmmc_iSpatial_setup.tcl
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
# Target library
set link_library $list_lib
set target_library $list_lib
set_db init_hdl_search_path [list . $rtl_path]
# set path
set_db auto_ungroup none
#set_db library $list_lib
#################################################
# Load Design and Initialize
#################################################
read_hdl -f rtl_list.tcl
elaborate $DESIGN
time_info Elaboration
#read_sdc $sdc
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
read_def $floorplan_def
check_floorplan -detailed
# keep hierarchy during synthesis
set_db auto_ungroup none
syn_generic -physical
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
syn_map -physical
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
syn_opt -spatial
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
exit
Flows/ASAP7/nvdla/scripts/cadence/run_invs.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
source mmmc_setup.tcl
setMultiCpuUsage -localCpu 16
set util 0.3
set netlist "./syn_handoff/$DESIGN.v"
set sdc "./syn_handoff/$DESIGN.sdc"
set site "asap7sc7p5t"
set rptDir summaryReport/
set encDir enc/
if {![file exists $rptDir/]} {
exec mkdir $rptDir/
}
if {![file exists $encDir/]} {
exec mkdir $encDir/
}
# default settings
set init_pwr_net VDD
set init_gnd_net VSS
# default settings
set init_verilog "$netlist"
set init_design_netlisttype "Verilog"
set init_design_settop 1
set init_top_cell "$DESIGN"
set init_lef_file "$lefs"
# MCMM setup
init_design -setup {WC_VIEW} -hold {BC_VIEW}
set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
set_interactive_constraint_modes {CON}
setDesignMode -process 7
clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
globalNetConnect VSS -type pgpin -pin VSS -inst * -override
globalNetConnect VDD -type tiehi -inst * -override
globalNetConnect VSS -type tielo -inst * -override
setOptMode -powerEffort low -leakageToDynamicRatio 0.5
setGenerateViaMode -auto true
generateVias
# basic path groups
createBasicPathGroups -expanded
## Generate the floorplan ##
#floorPlan -r 1.0 $util 10 10 10 10
defIn $floorplan_def
## Macro Placement ##
#redirect mp_config.tcl {source gen_mp_config.tcl}
#proto_design -constraints mp_config.tcl
addHaloToBlock -allMacro 1 1 1 1
setFPlanMode -snapBlockGrid LayerTrack
place_design -concurrent_macros
refine_macro_place
snapFPlan -pin
saveDesign ${encDir}/${DESIGN}_floorplan.enc
## Creating Pin Blcokage for lower and upper pin layers ##
createPinBlkg -name Layer_1 -layer {M2 M3 M7 M8 M9 Pad} -edge 0
createPinBlkg -name side_top -edge 1
createPinBlkg -name side_right -edge 2
createPinBlkg -name side_bottom -edge 3
setPlaceMode -place_detail_legalization_inst_gap 1
setFillerMode -fitGap true
setDesignMode -topRoutingLayer 7
setDesignMode -bottomRoutingLayer 2
place_opt_design -out_dir $rptDir -prefix place
saveDesign $encDir/${DESIGN}_placed.enc
set_ccopt_property post_conditioning_enable_routing_eco 1
set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
setOptMode -unfixClkInstForOpt false
create_ccopt_clock_tree_spec
ccopt_design
set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks]
set_clock_propagation propagated
# ------------------------------------------------------------------------------
# Routing
# ------------------------------------------------------------------------------
setNanoRouteMode -drouteVerboseViolationSummary 1
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeUseAutoVia true
##Recommended by lib owners
# Prevent router modifying M1 pins shapes
setNanoRouteMode -routeWithViaInPin "1:1"
setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
## limit VIAs to ongrid only for VIA1 (S1)
setNanoRouteMode -drouteOnGridOnly "via 1:1"
setNanoRouteMode -drouteAutoStop false
setNanoRouteMode -drouteExpAdvancedMarFix true
setNanoRouteMode -routeExpAdvancedTechnology true
#SM suggestion for solving long extraction runtime during GR
setNanoRouteMode -grouteExpWithTimingDriven false
routeDesign
#route_opt_design
saveDesign ${encDir}/${DESIGN}_route.enc
defOut -netlist -floorplan -routing ${DESIGN}_route.def
summaryReport -noHtml -outfile summaryReport/post_route.sum
saveDesign ${encDir}/${DESIGN}.enc
defOut -netlist -floorplan -routing ${DESIGN}.def
exit
Flows/NanGate45/ariane136/scripts/cadence/run.sh 100644 → 100755
File mode changed from 100644 to 100755
Flows/NanGate45/mempool_tile/def/mempool_tile_wrap_fp.def
###############################################################
# Generated by: Cadence Innovus 21.11-s130_1
# OS: Linux x86_64(Host ID npc.ucsd.edu)
# Generated on: Sun Jul 3 10:54:36 2022
# Design: mempool_tile_wrap
# Command: defOut -floorplan ../../def/mempool_tile_wrap_fp.def
###############################################################
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
......@@ -14,6 +21,1334 @@ END PROPERTYDEFINITIONS
DIEAREA ( 0 0 ) ( 1800060 1800120 ) ;
ROW CORE_ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 20140 19880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 20140 22680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 20140 25480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 20140 28280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 20140 31080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 20140 33880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 20140 36680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 20140 39480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 20140 42280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 20140 45080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 20140 47880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 20140 50680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 20140 53480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 20140 56280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 20140 59080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 20140 61880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 20140 64680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 20140 67480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 20140 70280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 20140 73080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 20140 75880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 20140 78680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 20140 81480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 20140 84280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 20140 87080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 20140 89880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 20140 92680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 20140 95480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 20140 98280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 20140 101080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 20140 103880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 20140 106680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 20140 109480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 20140 112280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 20140 115080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 20140 117880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 20140 120680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 20140 123480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 20140 126280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 20140 129080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 20140 131880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 20140 134680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 20140 137480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 20140 140280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 20140 143080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 20140 145880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 20140 148680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 20140 151480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 20140 154280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 20140 157080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 20140 159880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 20140 162680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 20140 165480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 20140 168280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 20140 171080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 20140 173880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 20140 176680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 20140 179480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 20140 182280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 20140 185080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 20140 187880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 20140 190680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 20140 193480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 20140 196280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 20140 199080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 20140 201880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 20140 204680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 20140 207480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 20140 210280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 20140 213080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 20140 215880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 20140 218680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 20140 221480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 20140 224280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 20140 227080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 20140 229880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 20140 232680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 20140 235480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 20140 238280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 20140 241080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 20140 243880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 20140 246680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 20140 249480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 20140 252280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 20140 255080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 20140 257880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 20140 260680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 20140 263480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 20140 266280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_89 FreePDK45_38x28_10R_NP_162NW_34O 20140 269080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_90 FreePDK45_38x28_10R_NP_162NW_34O 20140 271880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_91 FreePDK45_38x28_10R_NP_162NW_34O 20140 274680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_92 FreePDK45_38x28_10R_NP_162NW_34O 20140 277480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_93 FreePDK45_38x28_10R_NP_162NW_34O 20140 280280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_94 FreePDK45_38x28_10R_NP_162NW_34O 20140 283080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_95 FreePDK45_38x28_10R_NP_162NW_34O 20140 285880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_96 FreePDK45_38x28_10R_NP_162NW_34O 20140 288680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_97 FreePDK45_38x28_10R_NP_162NW_34O 20140 291480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_98 FreePDK45_38x28_10R_NP_162NW_34O 20140 294280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_99 FreePDK45_38x28_10R_NP_162NW_34O 20140 297080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_100 FreePDK45_38x28_10R_NP_162NW_34O 20140 299880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_101 FreePDK45_38x28_10R_NP_162NW_34O 20140 302680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_102 FreePDK45_38x28_10R_NP_162NW_34O 20140 305480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_103 FreePDK45_38x28_10R_NP_162NW_34O 20140 308280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_104 FreePDK45_38x28_10R_NP_162NW_34O 20140 311080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_105 FreePDK45_38x28_10R_NP_162NW_34O 20140 313880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_106 FreePDK45_38x28_10R_NP_162NW_34O 20140 316680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_107 FreePDK45_38x28_10R_NP_162NW_34O 20140 319480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_108 FreePDK45_38x28_10R_NP_162NW_34O 20140 322280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_109 FreePDK45_38x28_10R_NP_162NW_34O 20140 325080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_110 FreePDK45_38x28_10R_NP_162NW_34O 20140 327880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_111 FreePDK45_38x28_10R_NP_162NW_34O 20140 330680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_112 FreePDK45_38x28_10R_NP_162NW_34O 20140 333480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_113 FreePDK45_38x28_10R_NP_162NW_34O 20140 336280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_114 FreePDK45_38x28_10R_NP_162NW_34O 20140 339080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_115 FreePDK45_38x28_10R_NP_162NW_34O 20140 341880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_116 FreePDK45_38x28_10R_NP_162NW_34O 20140 344680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_117 FreePDK45_38x28_10R_NP_162NW_34O 20140 347480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_118 FreePDK45_38x28_10R_NP_162NW_34O 20140 350280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_119 FreePDK45_38x28_10R_NP_162NW_34O 20140 353080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_120 FreePDK45_38x28_10R_NP_162NW_34O 20140 355880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_121 FreePDK45_38x28_10R_NP_162NW_34O 20140 358680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_122 FreePDK45_38x28_10R_NP_162NW_34O 20140 361480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_123 FreePDK45_38x28_10R_NP_162NW_34O 20140 364280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_124 FreePDK45_38x28_10R_NP_162NW_34O 20140 367080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_125 FreePDK45_38x28_10R_NP_162NW_34O 20140 369880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_126 FreePDK45_38x28_10R_NP_162NW_34O 20140 372680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_127 FreePDK45_38x28_10R_NP_162NW_34O 20140 375480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_128 FreePDK45_38x28_10R_NP_162NW_34O 20140 378280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_129 FreePDK45_38x28_10R_NP_162NW_34O 20140 381080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_130 FreePDK45_38x28_10R_NP_162NW_34O 20140 383880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_131 FreePDK45_38x28_10R_NP_162NW_34O 20140 386680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_132 FreePDK45_38x28_10R_NP_162NW_34O 20140 389480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_133 FreePDK45_38x28_10R_NP_162NW_34O 20140 392280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_134 FreePDK45_38x28_10R_NP_162NW_34O 20140 395080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_135 FreePDK45_38x28_10R_NP_162NW_34O 20140 397880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_136 FreePDK45_38x28_10R_NP_162NW_34O 20140 400680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_137 FreePDK45_38x28_10R_NP_162NW_34O 20140 403480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_138 FreePDK45_38x28_10R_NP_162NW_34O 20140 406280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_139 FreePDK45_38x28_10R_NP_162NW_34O 20140 409080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_140 FreePDK45_38x28_10R_NP_162NW_34O 20140 411880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_141 FreePDK45_38x28_10R_NP_162NW_34O 20140 414680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_142 FreePDK45_38x28_10R_NP_162NW_34O 20140 417480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_143 FreePDK45_38x28_10R_NP_162NW_34O 20140 420280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_144 FreePDK45_38x28_10R_NP_162NW_34O 20140 423080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_145 FreePDK45_38x28_10R_NP_162NW_34O 20140 425880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_146 FreePDK45_38x28_10R_NP_162NW_34O 20140 428680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_147 FreePDK45_38x28_10R_NP_162NW_34O 20140 431480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_148 FreePDK45_38x28_10R_NP_162NW_34O 20140 434280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_149 FreePDK45_38x28_10R_NP_162NW_34O 20140 437080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_150 FreePDK45_38x28_10R_NP_162NW_34O 20140 439880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_151 FreePDK45_38x28_10R_NP_162NW_34O 20140 442680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_152 FreePDK45_38x28_10R_NP_162NW_34O 20140 445480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_153 FreePDK45_38x28_10R_NP_162NW_34O 20140 448280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_154 FreePDK45_38x28_10R_NP_162NW_34O 20140 451080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_155 FreePDK45_38x28_10R_NP_162NW_34O 20140 453880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_156 FreePDK45_38x28_10R_NP_162NW_34O 20140 456680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_157 FreePDK45_38x28_10R_NP_162NW_34O 20140 459480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_158 FreePDK45_38x28_10R_NP_162NW_34O 20140 462280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_159 FreePDK45_38x28_10R_NP_162NW_34O 20140 465080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_160 FreePDK45_38x28_10R_NP_162NW_34O 20140 467880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_161 FreePDK45_38x28_10R_NP_162NW_34O 20140 470680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_162 FreePDK45_38x28_10R_NP_162NW_34O 20140 473480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_163 FreePDK45_38x28_10R_NP_162NW_34O 20140 476280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_164 FreePDK45_38x28_10R_NP_162NW_34O 20140 479080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_165 FreePDK45_38x28_10R_NP_162NW_34O 20140 481880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_166 FreePDK45_38x28_10R_NP_162NW_34O 20140 484680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_167 FreePDK45_38x28_10R_NP_162NW_34O 20140 487480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_168 FreePDK45_38x28_10R_NP_162NW_34O 20140 490280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_169 FreePDK45_38x28_10R_NP_162NW_34O 20140 493080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_170 FreePDK45_38x28_10R_NP_162NW_34O 20140 495880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_171 FreePDK45_38x28_10R_NP_162NW_34O 20140 498680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_172 FreePDK45_38x28_10R_NP_162NW_34O 20140 501480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_173 FreePDK45_38x28_10R_NP_162NW_34O 20140 504280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_174 FreePDK45_38x28_10R_NP_162NW_34O 20140 507080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_175 FreePDK45_38x28_10R_NP_162NW_34O 20140 509880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_176 FreePDK45_38x28_10R_NP_162NW_34O 20140 512680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_177 FreePDK45_38x28_10R_NP_162NW_34O 20140 515480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_178 FreePDK45_38x28_10R_NP_162NW_34O 20140 518280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_179 FreePDK45_38x28_10R_NP_162NW_34O 20140 521080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_180 FreePDK45_38x28_10R_NP_162NW_34O 20140 523880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_181 FreePDK45_38x28_10R_NP_162NW_34O 20140 526680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_182 FreePDK45_38x28_10R_NP_162NW_34O 20140 529480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_183 FreePDK45_38x28_10R_NP_162NW_34O 20140 532280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_184 FreePDK45_38x28_10R_NP_162NW_34O 20140 535080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_185 FreePDK45_38x28_10R_NP_162NW_34O 20140 537880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_186 FreePDK45_38x28_10R_NP_162NW_34O 20140 540680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_187 FreePDK45_38x28_10R_NP_162NW_34O 20140 543480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_188 FreePDK45_38x28_10R_NP_162NW_34O 20140 546280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_189 FreePDK45_38x28_10R_NP_162NW_34O 20140 549080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_190 FreePDK45_38x28_10R_NP_162NW_34O 20140 551880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_191 FreePDK45_38x28_10R_NP_162NW_34O 20140 554680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_192 FreePDK45_38x28_10R_NP_162NW_34O 20140 557480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_193 FreePDK45_38x28_10R_NP_162NW_34O 20140 560280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_194 FreePDK45_38x28_10R_NP_162NW_34O 20140 563080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_195 FreePDK45_38x28_10R_NP_162NW_34O 20140 565880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_196 FreePDK45_38x28_10R_NP_162NW_34O 20140 568680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_197 FreePDK45_38x28_10R_NP_162NW_34O 20140 571480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_198 FreePDK45_38x28_10R_NP_162NW_34O 20140 574280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_199 FreePDK45_38x28_10R_NP_162NW_34O 20140 577080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_200 FreePDK45_38x28_10R_NP_162NW_34O 20140 579880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_201 FreePDK45_38x28_10R_NP_162NW_34O 20140 582680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_202 FreePDK45_38x28_10R_NP_162NW_34O 20140 585480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_203 FreePDK45_38x28_10R_NP_162NW_34O 20140 588280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_204 FreePDK45_38x28_10R_NP_162NW_34O 20140 591080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_205 FreePDK45_38x28_10R_NP_162NW_34O 20140 593880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_206 FreePDK45_38x28_10R_NP_162NW_34O 20140 596680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_207 FreePDK45_38x28_10R_NP_162NW_34O 20140 599480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_208 FreePDK45_38x28_10R_NP_162NW_34O 20140 602280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_209 FreePDK45_38x28_10R_NP_162NW_34O 20140 605080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_210 FreePDK45_38x28_10R_NP_162NW_34O 20140 607880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_211 FreePDK45_38x28_10R_NP_162NW_34O 20140 610680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_212 FreePDK45_38x28_10R_NP_162NW_34O 20140 613480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_213 FreePDK45_38x28_10R_NP_162NW_34O 20140 616280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_214 FreePDK45_38x28_10R_NP_162NW_34O 20140 619080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_215 FreePDK45_38x28_10R_NP_162NW_34O 20140 621880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_216 FreePDK45_38x28_10R_NP_162NW_34O 20140 624680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_217 FreePDK45_38x28_10R_NP_162NW_34O 20140 627480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_218 FreePDK45_38x28_10R_NP_162NW_34O 20140 630280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_219 FreePDK45_38x28_10R_NP_162NW_34O 20140 633080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_220 FreePDK45_38x28_10R_NP_162NW_34O 20140 635880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_221 FreePDK45_38x28_10R_NP_162NW_34O 20140 638680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_222 FreePDK45_38x28_10R_NP_162NW_34O 20140 641480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_223 FreePDK45_38x28_10R_NP_162NW_34O 20140 644280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_224 FreePDK45_38x28_10R_NP_162NW_34O 20140 647080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_225 FreePDK45_38x28_10R_NP_162NW_34O 20140 649880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_226 FreePDK45_38x28_10R_NP_162NW_34O 20140 652680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_227 FreePDK45_38x28_10R_NP_162NW_34O 20140 655480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_228 FreePDK45_38x28_10R_NP_162NW_34O 20140 658280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_229 FreePDK45_38x28_10R_NP_162NW_34O 20140 661080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_230 FreePDK45_38x28_10R_NP_162NW_34O 20140 663880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_231 FreePDK45_38x28_10R_NP_162NW_34O 20140 666680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_232 FreePDK45_38x28_10R_NP_162NW_34O 20140 669480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_233 FreePDK45_38x28_10R_NP_162NW_34O 20140 672280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_234 FreePDK45_38x28_10R_NP_162NW_34O 20140 675080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_235 FreePDK45_38x28_10R_NP_162NW_34O 20140 677880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_236 FreePDK45_38x28_10R_NP_162NW_34O 20140 680680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_237 FreePDK45_38x28_10R_NP_162NW_34O 20140 683480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_238 FreePDK45_38x28_10R_NP_162NW_34O 20140 686280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_239 FreePDK45_38x28_10R_NP_162NW_34O 20140 689080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_240 FreePDK45_38x28_10R_NP_162NW_34O 20140 691880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_241 FreePDK45_38x28_10R_NP_162NW_34O 20140 694680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_242 FreePDK45_38x28_10R_NP_162NW_34O 20140 697480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_243 FreePDK45_38x28_10R_NP_162NW_34O 20140 700280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_244 FreePDK45_38x28_10R_NP_162NW_34O 20140 703080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_245 FreePDK45_38x28_10R_NP_162NW_34O 20140 705880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_246 FreePDK45_38x28_10R_NP_162NW_34O 20140 708680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_247 FreePDK45_38x28_10R_NP_162NW_34O 20140 711480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_248 FreePDK45_38x28_10R_NP_162NW_34O 20140 714280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_249 FreePDK45_38x28_10R_NP_162NW_34O 20140 717080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_250 FreePDK45_38x28_10R_NP_162NW_34O 20140 719880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_251 FreePDK45_38x28_10R_NP_162NW_34O 20140 722680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_252 FreePDK45_38x28_10R_NP_162NW_34O 20140 725480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_253 FreePDK45_38x28_10R_NP_162NW_34O 20140 728280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_254 FreePDK45_38x28_10R_NP_162NW_34O 20140 731080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_255 FreePDK45_38x28_10R_NP_162NW_34O 20140 733880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_256 FreePDK45_38x28_10R_NP_162NW_34O 20140 736680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_257 FreePDK45_38x28_10R_NP_162NW_34O 20140 739480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_258 FreePDK45_38x28_10R_NP_162NW_34O 20140 742280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_259 FreePDK45_38x28_10R_NP_162NW_34O 20140 745080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_260 FreePDK45_38x28_10R_NP_162NW_34O 20140 747880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_261 FreePDK45_38x28_10R_NP_162NW_34O 20140 750680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_262 FreePDK45_38x28_10R_NP_162NW_34O 20140 753480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_263 FreePDK45_38x28_10R_NP_162NW_34O 20140 756280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_264 FreePDK45_38x28_10R_NP_162NW_34O 20140 759080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_265 FreePDK45_38x28_10R_NP_162NW_34O 20140 761880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_266 FreePDK45_38x28_10R_NP_162NW_34O 20140 764680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_267 FreePDK45_38x28_10R_NP_162NW_34O 20140 767480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_268 FreePDK45_38x28_10R_NP_162NW_34O 20140 770280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_269 FreePDK45_38x28_10R_NP_162NW_34O 20140 773080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_270 FreePDK45_38x28_10R_NP_162NW_34O 20140 775880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_271 FreePDK45_38x28_10R_NP_162NW_34O 20140 778680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_272 FreePDK45_38x28_10R_NP_162NW_34O 20140 781480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_273 FreePDK45_38x28_10R_NP_162NW_34O 20140 784280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_274 FreePDK45_38x28_10R_NP_162NW_34O 20140 787080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_275 FreePDK45_38x28_10R_NP_162NW_34O 20140 789880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_276 FreePDK45_38x28_10R_NP_162NW_34O 20140 792680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_277 FreePDK45_38x28_10R_NP_162NW_34O 20140 795480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_278 FreePDK45_38x28_10R_NP_162NW_34O 20140 798280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_279 FreePDK45_38x28_10R_NP_162NW_34O 20140 801080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_280 FreePDK45_38x28_10R_NP_162NW_34O 20140 803880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_281 FreePDK45_38x28_10R_NP_162NW_34O 20140 806680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_282 FreePDK45_38x28_10R_NP_162NW_34O 20140 809480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_283 FreePDK45_38x28_10R_NP_162NW_34O 20140 812280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_284 FreePDK45_38x28_10R_NP_162NW_34O 20140 815080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_285 FreePDK45_38x28_10R_NP_162NW_34O 20140 817880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_286 FreePDK45_38x28_10R_NP_162NW_34O 20140 820680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_287 FreePDK45_38x28_10R_NP_162NW_34O 20140 823480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_288 FreePDK45_38x28_10R_NP_162NW_34O 20140 826280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_289 FreePDK45_38x28_10R_NP_162NW_34O 20140 829080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_290 FreePDK45_38x28_10R_NP_162NW_34O 20140 831880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_291 FreePDK45_38x28_10R_NP_162NW_34O 20140 834680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_292 FreePDK45_38x28_10R_NP_162NW_34O 20140 837480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_293 FreePDK45_38x28_10R_NP_162NW_34O 20140 840280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_294 FreePDK45_38x28_10R_NP_162NW_34O 20140 843080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_295 FreePDK45_38x28_10R_NP_162NW_34O 20140 845880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_296 FreePDK45_38x28_10R_NP_162NW_34O 20140 848680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_297 FreePDK45_38x28_10R_NP_162NW_34O 20140 851480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_298 FreePDK45_38x28_10R_NP_162NW_34O 20140 854280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_299 FreePDK45_38x28_10R_NP_162NW_34O 20140 857080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_300 FreePDK45_38x28_10R_NP_162NW_34O 20140 859880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_301 FreePDK45_38x28_10R_NP_162NW_34O 20140 862680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_302 FreePDK45_38x28_10R_NP_162NW_34O 20140 865480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_303 FreePDK45_38x28_10R_NP_162NW_34O 20140 868280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_304 FreePDK45_38x28_10R_NP_162NW_34O 20140 871080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_305 FreePDK45_38x28_10R_NP_162NW_34O 20140 873880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_306 FreePDK45_38x28_10R_NP_162NW_34O 20140 876680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_307 FreePDK45_38x28_10R_NP_162NW_34O 20140 879480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_308 FreePDK45_38x28_10R_NP_162NW_34O 20140 882280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_309 FreePDK45_38x28_10R_NP_162NW_34O 20140 885080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_310 FreePDK45_38x28_10R_NP_162NW_34O 20140 887880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_311 FreePDK45_38x28_10R_NP_162NW_34O 20140 890680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_312 FreePDK45_38x28_10R_NP_162NW_34O 20140 893480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_313 FreePDK45_38x28_10R_NP_162NW_34O 20140 896280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_314 FreePDK45_38x28_10R_NP_162NW_34O 20140 899080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_315 FreePDK45_38x28_10R_NP_162NW_34O 20140 901880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_316 FreePDK45_38x28_10R_NP_162NW_34O 20140 904680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_317 FreePDK45_38x28_10R_NP_162NW_34O 20140 907480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_318 FreePDK45_38x28_10R_NP_162NW_34O 20140 910280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_319 FreePDK45_38x28_10R_NP_162NW_34O 20140 913080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_320 FreePDK45_38x28_10R_NP_162NW_34O 20140 915880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_321 FreePDK45_38x28_10R_NP_162NW_34O 20140 918680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_322 FreePDK45_38x28_10R_NP_162NW_34O 20140 921480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_323 FreePDK45_38x28_10R_NP_162NW_34O 20140 924280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_324 FreePDK45_38x28_10R_NP_162NW_34O 20140 927080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_325 FreePDK45_38x28_10R_NP_162NW_34O 20140 929880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_326 FreePDK45_38x28_10R_NP_162NW_34O 20140 932680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_327 FreePDK45_38x28_10R_NP_162NW_34O 20140 935480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_328 FreePDK45_38x28_10R_NP_162NW_34O 20140 938280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_329 FreePDK45_38x28_10R_NP_162NW_34O 20140 941080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_330 FreePDK45_38x28_10R_NP_162NW_34O 20140 943880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_331 FreePDK45_38x28_10R_NP_162NW_34O 20140 946680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_332 FreePDK45_38x28_10R_NP_162NW_34O 20140 949480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_333 FreePDK45_38x28_10R_NP_162NW_34O 20140 952280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_334 FreePDK45_38x28_10R_NP_162NW_34O 20140 955080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_335 FreePDK45_38x28_10R_NP_162NW_34O 20140 957880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_336 FreePDK45_38x28_10R_NP_162NW_34O 20140 960680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_337 FreePDK45_38x28_10R_NP_162NW_34O 20140 963480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_338 FreePDK45_38x28_10R_NP_162NW_34O 20140 966280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_339 FreePDK45_38x28_10R_NP_162NW_34O 20140 969080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_340 FreePDK45_38x28_10R_NP_162NW_34O 20140 971880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_341 FreePDK45_38x28_10R_NP_162NW_34O 20140 974680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_342 FreePDK45_38x28_10R_NP_162NW_34O 20140 977480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_343 FreePDK45_38x28_10R_NP_162NW_34O 20140 980280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_344 FreePDK45_38x28_10R_NP_162NW_34O 20140 983080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_345 FreePDK45_38x28_10R_NP_162NW_34O 20140 985880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_346 FreePDK45_38x28_10R_NP_162NW_34O 20140 988680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_347 FreePDK45_38x28_10R_NP_162NW_34O 20140 991480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_348 FreePDK45_38x28_10R_NP_162NW_34O 20140 994280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_349 FreePDK45_38x28_10R_NP_162NW_34O 20140 997080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_350 FreePDK45_38x28_10R_NP_162NW_34O 20140 999880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_351 FreePDK45_38x28_10R_NP_162NW_34O 20140 1002680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_352 FreePDK45_38x28_10R_NP_162NW_34O 20140 1005480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_353 FreePDK45_38x28_10R_NP_162NW_34O 20140 1008280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_354 FreePDK45_38x28_10R_NP_162NW_34O 20140 1011080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_355 FreePDK45_38x28_10R_NP_162NW_34O 20140 1013880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_356 FreePDK45_38x28_10R_NP_162NW_34O 20140 1016680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_357 FreePDK45_38x28_10R_NP_162NW_34O 20140 1019480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_358 FreePDK45_38x28_10R_NP_162NW_34O 20140 1022280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_359 FreePDK45_38x28_10R_NP_162NW_34O 20140 1025080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_360 FreePDK45_38x28_10R_NP_162NW_34O 20140 1027880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_361 FreePDK45_38x28_10R_NP_162NW_34O 20140 1030680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_362 FreePDK45_38x28_10R_NP_162NW_34O 20140 1033480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_363 FreePDK45_38x28_10R_NP_162NW_34O 20140 1036280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_364 FreePDK45_38x28_10R_NP_162NW_34O 20140 1039080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_365 FreePDK45_38x28_10R_NP_162NW_34O 20140 1041880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_366 FreePDK45_38x28_10R_NP_162NW_34O 20140 1044680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_367 FreePDK45_38x28_10R_NP_162NW_34O 20140 1047480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_368 FreePDK45_38x28_10R_NP_162NW_34O 20140 1050280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_369 FreePDK45_38x28_10R_NP_162NW_34O 20140 1053080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_370 FreePDK45_38x28_10R_NP_162NW_34O 20140 1055880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_371 FreePDK45_38x28_10R_NP_162NW_34O 20140 1058680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_372 FreePDK45_38x28_10R_NP_162NW_34O 20140 1061480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_373 FreePDK45_38x28_10R_NP_162NW_34O 20140 1064280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_374 FreePDK45_38x28_10R_NP_162NW_34O 20140 1067080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_375 FreePDK45_38x28_10R_NP_162NW_34O 20140 1069880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_376 FreePDK45_38x28_10R_NP_162NW_34O 20140 1072680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_377 FreePDK45_38x28_10R_NP_162NW_34O 20140 1075480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_378 FreePDK45_38x28_10R_NP_162NW_34O 20140 1078280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_379 FreePDK45_38x28_10R_NP_162NW_34O 20140 1081080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_380 FreePDK45_38x28_10R_NP_162NW_34O 20140 1083880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_381 FreePDK45_38x28_10R_NP_162NW_34O 20140 1086680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_382 FreePDK45_38x28_10R_NP_162NW_34O 20140 1089480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_383 FreePDK45_38x28_10R_NP_162NW_34O 20140 1092280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_384 FreePDK45_38x28_10R_NP_162NW_34O 20140 1095080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_385 FreePDK45_38x28_10R_NP_162NW_34O 20140 1097880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_386 FreePDK45_38x28_10R_NP_162NW_34O 20140 1100680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_387 FreePDK45_38x28_10R_NP_162NW_34O 20140 1103480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_388 FreePDK45_38x28_10R_NP_162NW_34O 20140 1106280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_389 FreePDK45_38x28_10R_NP_162NW_34O 20140 1109080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_390 FreePDK45_38x28_10R_NP_162NW_34O 20140 1111880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_391 FreePDK45_38x28_10R_NP_162NW_34O 20140 1114680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_392 FreePDK45_38x28_10R_NP_162NW_34O 20140 1117480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_393 FreePDK45_38x28_10R_NP_162NW_34O 20140 1120280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_394 FreePDK45_38x28_10R_NP_162NW_34O 20140 1123080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_395 FreePDK45_38x28_10R_NP_162NW_34O 20140 1125880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_396 FreePDK45_38x28_10R_NP_162NW_34O 20140 1128680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_397 FreePDK45_38x28_10R_NP_162NW_34O 20140 1131480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_398 FreePDK45_38x28_10R_NP_162NW_34O 20140 1134280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_399 FreePDK45_38x28_10R_NP_162NW_34O 20140 1137080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_400 FreePDK45_38x28_10R_NP_162NW_34O 20140 1139880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_401 FreePDK45_38x28_10R_NP_162NW_34O 20140 1142680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_402 FreePDK45_38x28_10R_NP_162NW_34O 20140 1145480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_403 FreePDK45_38x28_10R_NP_162NW_34O 20140 1148280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_404 FreePDK45_38x28_10R_NP_162NW_34O 20140 1151080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_405 FreePDK45_38x28_10R_NP_162NW_34O 20140 1153880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_406 FreePDK45_38x28_10R_NP_162NW_34O 20140 1156680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_407 FreePDK45_38x28_10R_NP_162NW_34O 20140 1159480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_408 FreePDK45_38x28_10R_NP_162NW_34O 20140 1162280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_409 FreePDK45_38x28_10R_NP_162NW_34O 20140 1165080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_410 FreePDK45_38x28_10R_NP_162NW_34O 20140 1167880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_411 FreePDK45_38x28_10R_NP_162NW_34O 20140 1170680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_412 FreePDK45_38x28_10R_NP_162NW_34O 20140 1173480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_413 FreePDK45_38x28_10R_NP_162NW_34O 20140 1176280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_414 FreePDK45_38x28_10R_NP_162NW_34O 20140 1179080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_415 FreePDK45_38x28_10R_NP_162NW_34O 20140 1181880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_416 FreePDK45_38x28_10R_NP_162NW_34O 20140 1184680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_417 FreePDK45_38x28_10R_NP_162NW_34O 20140 1187480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_418 FreePDK45_38x28_10R_NP_162NW_34O 20140 1190280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_419 FreePDK45_38x28_10R_NP_162NW_34O 20140 1193080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_420 FreePDK45_38x28_10R_NP_162NW_34O 20140 1195880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_421 FreePDK45_38x28_10R_NP_162NW_34O 20140 1198680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_422 FreePDK45_38x28_10R_NP_162NW_34O 20140 1201480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_423 FreePDK45_38x28_10R_NP_162NW_34O 20140 1204280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_424 FreePDK45_38x28_10R_NP_162NW_34O 20140 1207080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_425 FreePDK45_38x28_10R_NP_162NW_34O 20140 1209880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_426 FreePDK45_38x28_10R_NP_162NW_34O 20140 1212680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_427 FreePDK45_38x28_10R_NP_162NW_34O 20140 1215480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_428 FreePDK45_38x28_10R_NP_162NW_34O 20140 1218280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_429 FreePDK45_38x28_10R_NP_162NW_34O 20140 1221080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_430 FreePDK45_38x28_10R_NP_162NW_34O 20140 1223880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_431 FreePDK45_38x28_10R_NP_162NW_34O 20140 1226680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_432 FreePDK45_38x28_10R_NP_162NW_34O 20140 1229480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_433 FreePDK45_38x28_10R_NP_162NW_34O 20140 1232280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_434 FreePDK45_38x28_10R_NP_162NW_34O 20140 1235080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_435 FreePDK45_38x28_10R_NP_162NW_34O 20140 1237880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_436 FreePDK45_38x28_10R_NP_162NW_34O 20140 1240680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_437 FreePDK45_38x28_10R_NP_162NW_34O 20140 1243480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_438 FreePDK45_38x28_10R_NP_162NW_34O 20140 1246280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_439 FreePDK45_38x28_10R_NP_162NW_34O 20140 1249080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_440 FreePDK45_38x28_10R_NP_162NW_34O 20140 1251880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_441 FreePDK45_38x28_10R_NP_162NW_34O 20140 1254680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_442 FreePDK45_38x28_10R_NP_162NW_34O 20140 1257480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_443 FreePDK45_38x28_10R_NP_162NW_34O 20140 1260280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_444 FreePDK45_38x28_10R_NP_162NW_34O 20140 1263080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_445 FreePDK45_38x28_10R_NP_162NW_34O 20140 1265880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_446 FreePDK45_38x28_10R_NP_162NW_34O 20140 1268680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_447 FreePDK45_38x28_10R_NP_162NW_34O 20140 1271480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_448 FreePDK45_38x28_10R_NP_162NW_34O 20140 1274280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_449 FreePDK45_38x28_10R_NP_162NW_34O 20140 1277080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_450 FreePDK45_38x28_10R_NP_162NW_34O 20140 1279880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_451 FreePDK45_38x28_10R_NP_162NW_34O 20140 1282680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_452 FreePDK45_38x28_10R_NP_162NW_34O 20140 1285480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_453 FreePDK45_38x28_10R_NP_162NW_34O 20140 1288280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_454 FreePDK45_38x28_10R_NP_162NW_34O 20140 1291080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_455 FreePDK45_38x28_10R_NP_162NW_34O 20140 1293880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_456 FreePDK45_38x28_10R_NP_162NW_34O 20140 1296680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_457 FreePDK45_38x28_10R_NP_162NW_34O 20140 1299480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_458 FreePDK45_38x28_10R_NP_162NW_34O 20140 1302280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_459 FreePDK45_38x28_10R_NP_162NW_34O 20140 1305080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_460 FreePDK45_38x28_10R_NP_162NW_34O 20140 1307880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_461 FreePDK45_38x28_10R_NP_162NW_34O 20140 1310680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_462 FreePDK45_38x28_10R_NP_162NW_34O 20140 1313480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_463 FreePDK45_38x28_10R_NP_162NW_34O 20140 1316280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_464 FreePDK45_38x28_10R_NP_162NW_34O 20140 1319080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_465 FreePDK45_38x28_10R_NP_162NW_34O 20140 1321880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_466 FreePDK45_38x28_10R_NP_162NW_34O 20140 1324680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_467 FreePDK45_38x28_10R_NP_162NW_34O 20140 1327480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_468 FreePDK45_38x28_10R_NP_162NW_34O 20140 1330280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_469 FreePDK45_38x28_10R_NP_162NW_34O 20140 1333080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_470 FreePDK45_38x28_10R_NP_162NW_34O 20140 1335880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_471 FreePDK45_38x28_10R_NP_162NW_34O 20140 1338680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_472 FreePDK45_38x28_10R_NP_162NW_34O 20140 1341480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_473 FreePDK45_38x28_10R_NP_162NW_34O 20140 1344280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_474 FreePDK45_38x28_10R_NP_162NW_34O 20140 1347080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_475 FreePDK45_38x28_10R_NP_162NW_34O 20140 1349880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_476 FreePDK45_38x28_10R_NP_162NW_34O 20140 1352680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_477 FreePDK45_38x28_10R_NP_162NW_34O 20140 1355480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_478 FreePDK45_38x28_10R_NP_162NW_34O 20140 1358280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_479 FreePDK45_38x28_10R_NP_162NW_34O 20140 1361080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_480 FreePDK45_38x28_10R_NP_162NW_34O 20140 1363880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_481 FreePDK45_38x28_10R_NP_162NW_34O 20140 1366680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_482 FreePDK45_38x28_10R_NP_162NW_34O 20140 1369480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_483 FreePDK45_38x28_10R_NP_162NW_34O 20140 1372280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_484 FreePDK45_38x28_10R_NP_162NW_34O 20140 1375080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_485 FreePDK45_38x28_10R_NP_162NW_34O 20140 1377880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_486 FreePDK45_38x28_10R_NP_162NW_34O 20140 1380680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_487 FreePDK45_38x28_10R_NP_162NW_34O 20140 1383480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_488 FreePDK45_38x28_10R_NP_162NW_34O 20140 1386280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_489 FreePDK45_38x28_10R_NP_162NW_34O 20140 1389080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_490 FreePDK45_38x28_10R_NP_162NW_34O 20140 1391880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_491 FreePDK45_38x28_10R_NP_162NW_34O 20140 1394680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_492 FreePDK45_38x28_10R_NP_162NW_34O 20140 1397480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_493 FreePDK45_38x28_10R_NP_162NW_34O 20140 1400280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_494 FreePDK45_38x28_10R_NP_162NW_34O 20140 1403080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_495 FreePDK45_38x28_10R_NP_162NW_34O 20140 1405880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_496 FreePDK45_38x28_10R_NP_162NW_34O 20140 1408680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_497 FreePDK45_38x28_10R_NP_162NW_34O 20140 1411480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_498 FreePDK45_38x28_10R_NP_162NW_34O 20140 1414280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_499 FreePDK45_38x28_10R_NP_162NW_34O 20140 1417080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_500 FreePDK45_38x28_10R_NP_162NW_34O 20140 1419880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_501 FreePDK45_38x28_10R_NP_162NW_34O 20140 1422680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_502 FreePDK45_38x28_10R_NP_162NW_34O 20140 1425480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_503 FreePDK45_38x28_10R_NP_162NW_34O 20140 1428280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_504 FreePDK45_38x28_10R_NP_162NW_34O 20140 1431080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_505 FreePDK45_38x28_10R_NP_162NW_34O 20140 1433880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_506 FreePDK45_38x28_10R_NP_162NW_34O 20140 1436680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_507 FreePDK45_38x28_10R_NP_162NW_34O 20140 1439480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_508 FreePDK45_38x28_10R_NP_162NW_34O 20140 1442280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_509 FreePDK45_38x28_10R_NP_162NW_34O 20140 1445080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_510 FreePDK45_38x28_10R_NP_162NW_34O 20140 1447880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_511 FreePDK45_38x28_10R_NP_162NW_34O 20140 1450680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_512 FreePDK45_38x28_10R_NP_162NW_34O 20140 1453480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_513 FreePDK45_38x28_10R_NP_162NW_34O 20140 1456280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_514 FreePDK45_38x28_10R_NP_162NW_34O 20140 1459080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_515 FreePDK45_38x28_10R_NP_162NW_34O 20140 1461880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_516 FreePDK45_38x28_10R_NP_162NW_34O 20140 1464680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_517 FreePDK45_38x28_10R_NP_162NW_34O 20140 1467480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_518 FreePDK45_38x28_10R_NP_162NW_34O 20140 1470280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_519 FreePDK45_38x28_10R_NP_162NW_34O 20140 1473080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_520 FreePDK45_38x28_10R_NP_162NW_34O 20140 1475880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_521 FreePDK45_38x28_10R_NP_162NW_34O 20140 1478680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_522 FreePDK45_38x28_10R_NP_162NW_34O 20140 1481480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_523 FreePDK45_38x28_10R_NP_162NW_34O 20140 1484280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_524 FreePDK45_38x28_10R_NP_162NW_34O 20140 1487080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_525 FreePDK45_38x28_10R_NP_162NW_34O 20140 1489880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_526 FreePDK45_38x28_10R_NP_162NW_34O 20140 1492680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_527 FreePDK45_38x28_10R_NP_162NW_34O 20140 1495480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_528 FreePDK45_38x28_10R_NP_162NW_34O 20140 1498280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_529 FreePDK45_38x28_10R_NP_162NW_34O 20140 1501080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_530 FreePDK45_38x28_10R_NP_162NW_34O 20140 1503880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_531 FreePDK45_38x28_10R_NP_162NW_34O 20140 1506680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_532 FreePDK45_38x28_10R_NP_162NW_34O 20140 1509480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_533 FreePDK45_38x28_10R_NP_162NW_34O 20140 1512280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_534 FreePDK45_38x28_10R_NP_162NW_34O 20140 1515080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_535 FreePDK45_38x28_10R_NP_162NW_34O 20140 1517880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_536 FreePDK45_38x28_10R_NP_162NW_34O 20140 1520680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_537 FreePDK45_38x28_10R_NP_162NW_34O 20140 1523480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_538 FreePDK45_38x28_10R_NP_162NW_34O 20140 1526280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_539 FreePDK45_38x28_10R_NP_162NW_34O 20140 1529080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_540 FreePDK45_38x28_10R_NP_162NW_34O 20140 1531880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_541 FreePDK45_38x28_10R_NP_162NW_34O 20140 1534680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_542 FreePDK45_38x28_10R_NP_162NW_34O 20140 1537480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_543 FreePDK45_38x28_10R_NP_162NW_34O 20140 1540280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_544 FreePDK45_38x28_10R_NP_162NW_34O 20140 1543080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_545 FreePDK45_38x28_10R_NP_162NW_34O 20140 1545880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_546 FreePDK45_38x28_10R_NP_162NW_34O 20140 1548680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_547 FreePDK45_38x28_10R_NP_162NW_34O 20140 1551480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_548 FreePDK45_38x28_10R_NP_162NW_34O 20140 1554280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_549 FreePDK45_38x28_10R_NP_162NW_34O 20140 1557080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_550 FreePDK45_38x28_10R_NP_162NW_34O 20140 1559880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_551 FreePDK45_38x28_10R_NP_162NW_34O 20140 1562680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_552 FreePDK45_38x28_10R_NP_162NW_34O 20140 1565480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_553 FreePDK45_38x28_10R_NP_162NW_34O 20140 1568280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_554 FreePDK45_38x28_10R_NP_162NW_34O 20140 1571080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_555 FreePDK45_38x28_10R_NP_162NW_34O 20140 1573880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_556 FreePDK45_38x28_10R_NP_162NW_34O 20140 1576680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_557 FreePDK45_38x28_10R_NP_162NW_34O 20140 1579480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_558 FreePDK45_38x28_10R_NP_162NW_34O 20140 1582280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_559 FreePDK45_38x28_10R_NP_162NW_34O 20140 1585080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_560 FreePDK45_38x28_10R_NP_162NW_34O 20140 1587880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_561 FreePDK45_38x28_10R_NP_162NW_34O 20140 1590680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_562 FreePDK45_38x28_10R_NP_162NW_34O 20140 1593480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_563 FreePDK45_38x28_10R_NP_162NW_34O 20140 1596280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_564 FreePDK45_38x28_10R_NP_162NW_34O 20140 1599080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_565 FreePDK45_38x28_10R_NP_162NW_34O 20140 1601880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_566 FreePDK45_38x28_10R_NP_162NW_34O 20140 1604680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_567 FreePDK45_38x28_10R_NP_162NW_34O 20140 1607480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_568 FreePDK45_38x28_10R_NP_162NW_34O 20140 1610280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_569 FreePDK45_38x28_10R_NP_162NW_34O 20140 1613080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_570 FreePDK45_38x28_10R_NP_162NW_34O 20140 1615880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_571 FreePDK45_38x28_10R_NP_162NW_34O 20140 1618680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_572 FreePDK45_38x28_10R_NP_162NW_34O 20140 1621480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_573 FreePDK45_38x28_10R_NP_162NW_34O 20140 1624280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_574 FreePDK45_38x28_10R_NP_162NW_34O 20140 1627080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_575 FreePDK45_38x28_10R_NP_162NW_34O 20140 1629880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_576 FreePDK45_38x28_10R_NP_162NW_34O 20140 1632680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_577 FreePDK45_38x28_10R_NP_162NW_34O 20140 1635480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_578 FreePDK45_38x28_10R_NP_162NW_34O 20140 1638280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_579 FreePDK45_38x28_10R_NP_162NW_34O 20140 1641080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_580 FreePDK45_38x28_10R_NP_162NW_34O 20140 1643880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_581 FreePDK45_38x28_10R_NP_162NW_34O 20140 1646680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_582 FreePDK45_38x28_10R_NP_162NW_34O 20140 1649480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_583 FreePDK45_38x28_10R_NP_162NW_34O 20140 1652280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_584 FreePDK45_38x28_10R_NP_162NW_34O 20140 1655080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_585 FreePDK45_38x28_10R_NP_162NW_34O 20140 1657880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_586 FreePDK45_38x28_10R_NP_162NW_34O 20140 1660680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_587 FreePDK45_38x28_10R_NP_162NW_34O 20140 1663480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_588 FreePDK45_38x28_10R_NP_162NW_34O 20140 1666280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_589 FreePDK45_38x28_10R_NP_162NW_34O 20140 1669080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_590 FreePDK45_38x28_10R_NP_162NW_34O 20140 1671880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_591 FreePDK45_38x28_10R_NP_162NW_34O 20140 1674680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_592 FreePDK45_38x28_10R_NP_162NW_34O 20140 1677480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_593 FreePDK45_38x28_10R_NP_162NW_34O 20140 1680280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_594 FreePDK45_38x28_10R_NP_162NW_34O 20140 1683080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_595 FreePDK45_38x28_10R_NP_162NW_34O 20140 1685880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_596 FreePDK45_38x28_10R_NP_162NW_34O 20140 1688680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_597 FreePDK45_38x28_10R_NP_162NW_34O 20140 1691480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_598 FreePDK45_38x28_10R_NP_162NW_34O 20140 1694280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_599 FreePDK45_38x28_10R_NP_162NW_34O 20140 1697080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_600 FreePDK45_38x28_10R_NP_162NW_34O 20140 1699880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_601 FreePDK45_38x28_10R_NP_162NW_34O 20140 1702680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_602 FreePDK45_38x28_10R_NP_162NW_34O 20140 1705480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_603 FreePDK45_38x28_10R_NP_162NW_34O 20140 1708280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_604 FreePDK45_38x28_10R_NP_162NW_34O 20140 1711080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_605 FreePDK45_38x28_10R_NP_162NW_34O 20140 1713880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_606 FreePDK45_38x28_10R_NP_162NW_34O 20140 1716680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_607 FreePDK45_38x28_10R_NP_162NW_34O 20140 1719480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_608 FreePDK45_38x28_10R_NP_162NW_34O 20140 1722280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_609 FreePDK45_38x28_10R_NP_162NW_34O 20140 1725080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_610 FreePDK45_38x28_10R_NP_162NW_34O 20140 1727880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_611 FreePDK45_38x28_10R_NP_162NW_34O 20140 1730680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_612 FreePDK45_38x28_10R_NP_162NW_34O 20140 1733480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_613 FreePDK45_38x28_10R_NP_162NW_34O 20140 1736280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_614 FreePDK45_38x28_10R_NP_162NW_34O 20140 1739080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_615 FreePDK45_38x28_10R_NP_162NW_34O 20140 1741880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_616 FreePDK45_38x28_10R_NP_162NW_34O 20140 1744680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_617 FreePDK45_38x28_10R_NP_162NW_34O 20140 1747480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_618 FreePDK45_38x28_10R_NP_162NW_34O 20140 1750280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_619 FreePDK45_38x28_10R_NP_162NW_34O 20140 1753080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_620 FreePDK45_38x28_10R_NP_162NW_34O 20140 1755880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_621 FreePDK45_38x28_10R_NP_162NW_34O 20140 1758680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_622 FreePDK45_38x28_10R_NP_162NW_34O 20140 1761480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_623 FreePDK45_38x28_10R_NP_162NW_34O 20140 1764280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_624 FreePDK45_38x28_10R_NP_162NW_34O 20140 1767080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_625 FreePDK45_38x28_10R_NP_162NW_34O 20140 1769880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_626 FreePDK45_38x28_10R_NP_162NW_34O 20140 1772680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_627 FreePDK45_38x28_10R_NP_162NW_34O 20140 1775480 N DO 4631 BY 1 STEP 380 0
;
TRACKS Y 4020 DO 562 STEP 3200 LAYER metal10 ;
TRACKS X 3530 DO 535 STEP 3360 LAYER metal10 ;
TRACKS X 1850 DO 1071 STEP 1680 LAYER metal9 ;
TRACKS Y 4020 DO 562 STEP 3200 LAYER metal9 ;
TRACKS Y 1540 DO 1071 STEP 1680 LAYER metal8 ;
TRACKS X 1850 DO 1071 STEP 1680 LAYER metal8 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal7 ;
TRACKS Y 1540 DO 1071 STEP 1680 LAYER metal7 ;
TRACKS Y 420 DO 3214 STEP 560 LAYER metal6 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal6 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal5 ;
TRACKS Y 420 DO 3214 STEP 560 LAYER metal5 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal4 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal4 ;
TRACKS X 190 DO 4737 STEP 380 LAYER metal3 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal3 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal2 ;
TRACKS X 190 DO 4737 STEP 380 LAYER metal2 ;
TRACKS X 190 DO 4737 STEP 380 LAYER metal1 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal1 ;
GCELLGRID X 1797590 DO 2 STEP 2470 ;
GCELLGRID X 190 DO 474 STEP 3800 ;
GCELLGRID X 0 DO 2 STEP 190 ;
GCELLGRID Y 1797740 DO 2 STEP 2380 ;
GCELLGRID Y 140 DO 643 STEP 2800 ;
GCELLGRID Y 0 DO 2 STEP 140 ;
COMPONENTS 20 ;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance0 fakeram45_64x64
;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance1 fakeram45_64x64
;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance2 fakeram45_64x64
;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance3 fakeram45_64x64
;
- i_tile/gen_banks_0__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_1__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_2__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_3__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_4__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_5__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_6__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_7__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_8__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_9__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_10__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_11__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_12__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_13__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_14__mem_bank/genblk1_sram_instance fakeram45_256x32
;
- i_tile/gen_banks_15__mem_bank/genblk1_sram_instance fakeram45_256x32
;
END COMPONENTS
PINS 1272 ;
- clk_i + NET clk_i + DIRECTION INPUT + USE SIGNAL
+ LAYER metal3 ( -70 0 ) ( 70 140 )
......@@ -3833,4 +5168,13 @@ PINS 1272 ;
+ FIXED ( 0 1254540 ) E ;
END PINS
SPECIALNETS 2 ;
- VDD ( * VDD )
+ USE POWER
;
- VSS ( * VSS )
+ USE GROUND
;
END SPECIALNETS
END DESIGN
Flows/NanGate45/mempool_tile/def/mempool_tile_wrap_mp_fp.def → Flows/NanGate45/mempool_tile/def/mempool_tile_wrap_fp_placed_macros.def
......@@ -14,6 +14,1291 @@ END PROPERTYDEFINITIONS
DIEAREA ( 0 0 ) ( 1800060 1800120 ) ;
ROW CORE_ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 20140 19880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 20140 22680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 20140 25480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 20140 28280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 20140 31080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 20140 33880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 20140 36680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 20140 39480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 20140 42280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 20140 45080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 20140 47880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 20140 50680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 20140 53480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 20140 56280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 20140 59080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 20140 61880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 20140 64680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 20140 67480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 20140 70280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 20140 73080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 20140 75880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 20140 78680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 20140 81480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 20140 84280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 20140 87080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 20140 89880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 20140 92680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 20140 95480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 20140 98280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 20140 101080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 20140 103880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 20140 106680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 20140 109480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 20140 112280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 20140 115080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 20140 117880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 20140 120680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 20140 123480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 20140 126280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 20140 129080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 20140 131880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 20140 134680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 20140 137480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 20140 140280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 20140 143080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 20140 145880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 20140 148680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 20140 151480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 20140 154280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 20140 157080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 20140 159880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 20140 162680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 20140 165480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 20140 168280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 20140 171080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 20140 173880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 20140 176680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 20140 179480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 20140 182280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 20140 185080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 20140 187880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 20140 190680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 20140 193480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 20140 196280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 20140 199080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 20140 201880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 20140 204680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 20140 207480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 20140 210280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 20140 213080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 20140 215880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 20140 218680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 20140 221480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 20140 224280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 20140 227080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 20140 229880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 20140 232680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 20140 235480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 20140 238280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 20140 241080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 20140 243880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 20140 246680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 20140 249480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 20140 252280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 20140 255080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 20140 257880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 20140 260680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 20140 263480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 20140 266280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_89 FreePDK45_38x28_10R_NP_162NW_34O 20140 269080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_90 FreePDK45_38x28_10R_NP_162NW_34O 20140 271880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_91 FreePDK45_38x28_10R_NP_162NW_34O 20140 274680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_92 FreePDK45_38x28_10R_NP_162NW_34O 20140 277480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_93 FreePDK45_38x28_10R_NP_162NW_34O 20140 280280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_94 FreePDK45_38x28_10R_NP_162NW_34O 20140 283080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_95 FreePDK45_38x28_10R_NP_162NW_34O 20140 285880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_96 FreePDK45_38x28_10R_NP_162NW_34O 20140 288680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_97 FreePDK45_38x28_10R_NP_162NW_34O 20140 291480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_98 FreePDK45_38x28_10R_NP_162NW_34O 20140 294280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_99 FreePDK45_38x28_10R_NP_162NW_34O 20140 297080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_100 FreePDK45_38x28_10R_NP_162NW_34O 20140 299880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_101 FreePDK45_38x28_10R_NP_162NW_34O 20140 302680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_102 FreePDK45_38x28_10R_NP_162NW_34O 20140 305480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_103 FreePDK45_38x28_10R_NP_162NW_34O 20140 308280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_104 FreePDK45_38x28_10R_NP_162NW_34O 20140 311080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_105 FreePDK45_38x28_10R_NP_162NW_34O 20140 313880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_106 FreePDK45_38x28_10R_NP_162NW_34O 20140 316680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_107 FreePDK45_38x28_10R_NP_162NW_34O 20140 319480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_108 FreePDK45_38x28_10R_NP_162NW_34O 20140 322280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_109 FreePDK45_38x28_10R_NP_162NW_34O 20140 325080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_110 FreePDK45_38x28_10R_NP_162NW_34O 20140 327880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_111 FreePDK45_38x28_10R_NP_162NW_34O 20140 330680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_112 FreePDK45_38x28_10R_NP_162NW_34O 20140 333480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_113 FreePDK45_38x28_10R_NP_162NW_34O 20140 336280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_114 FreePDK45_38x28_10R_NP_162NW_34O 20140 339080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_115 FreePDK45_38x28_10R_NP_162NW_34O 20140 341880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_116 FreePDK45_38x28_10R_NP_162NW_34O 20140 344680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_117 FreePDK45_38x28_10R_NP_162NW_34O 20140 347480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_118 FreePDK45_38x28_10R_NP_162NW_34O 20140 350280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_119 FreePDK45_38x28_10R_NP_162NW_34O 20140 353080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_120 FreePDK45_38x28_10R_NP_162NW_34O 20140 355880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_121 FreePDK45_38x28_10R_NP_162NW_34O 20140 358680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_122 FreePDK45_38x28_10R_NP_162NW_34O 20140 361480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_123 FreePDK45_38x28_10R_NP_162NW_34O 20140 364280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_124 FreePDK45_38x28_10R_NP_162NW_34O 20140 367080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_125 FreePDK45_38x28_10R_NP_162NW_34O 20140 369880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_126 FreePDK45_38x28_10R_NP_162NW_34O 20140 372680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_127 FreePDK45_38x28_10R_NP_162NW_34O 20140 375480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_128 FreePDK45_38x28_10R_NP_162NW_34O 20140 378280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_129 FreePDK45_38x28_10R_NP_162NW_34O 20140 381080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_130 FreePDK45_38x28_10R_NP_162NW_34O 20140 383880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_131 FreePDK45_38x28_10R_NP_162NW_34O 20140 386680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_132 FreePDK45_38x28_10R_NP_162NW_34O 20140 389480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_133 FreePDK45_38x28_10R_NP_162NW_34O 20140 392280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_134 FreePDK45_38x28_10R_NP_162NW_34O 20140 395080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_135 FreePDK45_38x28_10R_NP_162NW_34O 20140 397880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_136 FreePDK45_38x28_10R_NP_162NW_34O 20140 400680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_137 FreePDK45_38x28_10R_NP_162NW_34O 20140 403480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_138 FreePDK45_38x28_10R_NP_162NW_34O 20140 406280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_139 FreePDK45_38x28_10R_NP_162NW_34O 20140 409080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_140 FreePDK45_38x28_10R_NP_162NW_34O 20140 411880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_141 FreePDK45_38x28_10R_NP_162NW_34O 20140 414680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_142 FreePDK45_38x28_10R_NP_162NW_34O 20140 417480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_143 FreePDK45_38x28_10R_NP_162NW_34O 20140 420280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_144 FreePDK45_38x28_10R_NP_162NW_34O 20140 423080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_145 FreePDK45_38x28_10R_NP_162NW_34O 20140 425880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_146 FreePDK45_38x28_10R_NP_162NW_34O 20140 428680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_147 FreePDK45_38x28_10R_NP_162NW_34O 20140 431480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_148 FreePDK45_38x28_10R_NP_162NW_34O 20140 434280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_149 FreePDK45_38x28_10R_NP_162NW_34O 20140 437080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_150 FreePDK45_38x28_10R_NP_162NW_34O 20140 439880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_151 FreePDK45_38x28_10R_NP_162NW_34O 20140 442680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_152 FreePDK45_38x28_10R_NP_162NW_34O 20140 445480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_153 FreePDK45_38x28_10R_NP_162NW_34O 20140 448280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_154 FreePDK45_38x28_10R_NP_162NW_34O 20140 451080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_155 FreePDK45_38x28_10R_NP_162NW_34O 20140 453880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_156 FreePDK45_38x28_10R_NP_162NW_34O 20140 456680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_157 FreePDK45_38x28_10R_NP_162NW_34O 20140 459480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_158 FreePDK45_38x28_10R_NP_162NW_34O 20140 462280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_159 FreePDK45_38x28_10R_NP_162NW_34O 20140 465080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_160 FreePDK45_38x28_10R_NP_162NW_34O 20140 467880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_161 FreePDK45_38x28_10R_NP_162NW_34O 20140 470680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_162 FreePDK45_38x28_10R_NP_162NW_34O 20140 473480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_163 FreePDK45_38x28_10R_NP_162NW_34O 20140 476280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_164 FreePDK45_38x28_10R_NP_162NW_34O 20140 479080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_165 FreePDK45_38x28_10R_NP_162NW_34O 20140 481880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_166 FreePDK45_38x28_10R_NP_162NW_34O 20140 484680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_167 FreePDK45_38x28_10R_NP_162NW_34O 20140 487480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_168 FreePDK45_38x28_10R_NP_162NW_34O 20140 490280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_169 FreePDK45_38x28_10R_NP_162NW_34O 20140 493080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_170 FreePDK45_38x28_10R_NP_162NW_34O 20140 495880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_171 FreePDK45_38x28_10R_NP_162NW_34O 20140 498680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_172 FreePDK45_38x28_10R_NP_162NW_34O 20140 501480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_173 FreePDK45_38x28_10R_NP_162NW_34O 20140 504280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_174 FreePDK45_38x28_10R_NP_162NW_34O 20140 507080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_175 FreePDK45_38x28_10R_NP_162NW_34O 20140 509880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_176 FreePDK45_38x28_10R_NP_162NW_34O 20140 512680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_177 FreePDK45_38x28_10R_NP_162NW_34O 20140 515480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_178 FreePDK45_38x28_10R_NP_162NW_34O 20140 518280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_179 FreePDK45_38x28_10R_NP_162NW_34O 20140 521080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_180 FreePDK45_38x28_10R_NP_162NW_34O 20140 523880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_181 FreePDK45_38x28_10R_NP_162NW_34O 20140 526680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_182 FreePDK45_38x28_10R_NP_162NW_34O 20140 529480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_183 FreePDK45_38x28_10R_NP_162NW_34O 20140 532280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_184 FreePDK45_38x28_10R_NP_162NW_34O 20140 535080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_185 FreePDK45_38x28_10R_NP_162NW_34O 20140 537880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_186 FreePDK45_38x28_10R_NP_162NW_34O 20140 540680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_187 FreePDK45_38x28_10R_NP_162NW_34O 20140 543480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_188 FreePDK45_38x28_10R_NP_162NW_34O 20140 546280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_189 FreePDK45_38x28_10R_NP_162NW_34O 20140 549080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_190 FreePDK45_38x28_10R_NP_162NW_34O 20140 551880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_191 FreePDK45_38x28_10R_NP_162NW_34O 20140 554680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_192 FreePDK45_38x28_10R_NP_162NW_34O 20140 557480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_193 FreePDK45_38x28_10R_NP_162NW_34O 20140 560280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_194 FreePDK45_38x28_10R_NP_162NW_34O 20140 563080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_195 FreePDK45_38x28_10R_NP_162NW_34O 20140 565880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_196 FreePDK45_38x28_10R_NP_162NW_34O 20140 568680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_197 FreePDK45_38x28_10R_NP_162NW_34O 20140 571480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_198 FreePDK45_38x28_10R_NP_162NW_34O 20140 574280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_199 FreePDK45_38x28_10R_NP_162NW_34O 20140 577080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_200 FreePDK45_38x28_10R_NP_162NW_34O 20140 579880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_201 FreePDK45_38x28_10R_NP_162NW_34O 20140 582680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_202 FreePDK45_38x28_10R_NP_162NW_34O 20140 585480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_203 FreePDK45_38x28_10R_NP_162NW_34O 20140 588280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_204 FreePDK45_38x28_10R_NP_162NW_34O 20140 591080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_205 FreePDK45_38x28_10R_NP_162NW_34O 20140 593880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_206 FreePDK45_38x28_10R_NP_162NW_34O 20140 596680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_207 FreePDK45_38x28_10R_NP_162NW_34O 20140 599480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_208 FreePDK45_38x28_10R_NP_162NW_34O 20140 602280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_209 FreePDK45_38x28_10R_NP_162NW_34O 20140 605080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_210 FreePDK45_38x28_10R_NP_162NW_34O 20140 607880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_211 FreePDK45_38x28_10R_NP_162NW_34O 20140 610680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_212 FreePDK45_38x28_10R_NP_162NW_34O 20140 613480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_213 FreePDK45_38x28_10R_NP_162NW_34O 20140 616280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_214 FreePDK45_38x28_10R_NP_162NW_34O 20140 619080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_215 FreePDK45_38x28_10R_NP_162NW_34O 20140 621880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_216 FreePDK45_38x28_10R_NP_162NW_34O 20140 624680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_217 FreePDK45_38x28_10R_NP_162NW_34O 20140 627480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_218 FreePDK45_38x28_10R_NP_162NW_34O 20140 630280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_219 FreePDK45_38x28_10R_NP_162NW_34O 20140 633080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_220 FreePDK45_38x28_10R_NP_162NW_34O 20140 635880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_221 FreePDK45_38x28_10R_NP_162NW_34O 20140 638680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_222 FreePDK45_38x28_10R_NP_162NW_34O 20140 641480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_223 FreePDK45_38x28_10R_NP_162NW_34O 20140 644280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_224 FreePDK45_38x28_10R_NP_162NW_34O 20140 647080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_225 FreePDK45_38x28_10R_NP_162NW_34O 20140 649880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_226 FreePDK45_38x28_10R_NP_162NW_34O 20140 652680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_227 FreePDK45_38x28_10R_NP_162NW_34O 20140 655480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_228 FreePDK45_38x28_10R_NP_162NW_34O 20140 658280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_229 FreePDK45_38x28_10R_NP_162NW_34O 20140 661080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_230 FreePDK45_38x28_10R_NP_162NW_34O 20140 663880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_231 FreePDK45_38x28_10R_NP_162NW_34O 20140 666680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_232 FreePDK45_38x28_10R_NP_162NW_34O 20140 669480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_233 FreePDK45_38x28_10R_NP_162NW_34O 20140 672280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_234 FreePDK45_38x28_10R_NP_162NW_34O 20140 675080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_235 FreePDK45_38x28_10R_NP_162NW_34O 20140 677880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_236 FreePDK45_38x28_10R_NP_162NW_34O 20140 680680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_237 FreePDK45_38x28_10R_NP_162NW_34O 20140 683480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_238 FreePDK45_38x28_10R_NP_162NW_34O 20140 686280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_239 FreePDK45_38x28_10R_NP_162NW_34O 20140 689080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_240 FreePDK45_38x28_10R_NP_162NW_34O 20140 691880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_241 FreePDK45_38x28_10R_NP_162NW_34O 20140 694680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_242 FreePDK45_38x28_10R_NP_162NW_34O 20140 697480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_243 FreePDK45_38x28_10R_NP_162NW_34O 20140 700280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_244 FreePDK45_38x28_10R_NP_162NW_34O 20140 703080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_245 FreePDK45_38x28_10R_NP_162NW_34O 20140 705880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_246 FreePDK45_38x28_10R_NP_162NW_34O 20140 708680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_247 FreePDK45_38x28_10R_NP_162NW_34O 20140 711480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_248 FreePDK45_38x28_10R_NP_162NW_34O 20140 714280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_249 FreePDK45_38x28_10R_NP_162NW_34O 20140 717080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_250 FreePDK45_38x28_10R_NP_162NW_34O 20140 719880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_251 FreePDK45_38x28_10R_NP_162NW_34O 20140 722680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_252 FreePDK45_38x28_10R_NP_162NW_34O 20140 725480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_253 FreePDK45_38x28_10R_NP_162NW_34O 20140 728280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_254 FreePDK45_38x28_10R_NP_162NW_34O 20140 731080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_255 FreePDK45_38x28_10R_NP_162NW_34O 20140 733880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_256 FreePDK45_38x28_10R_NP_162NW_34O 20140 736680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_257 FreePDK45_38x28_10R_NP_162NW_34O 20140 739480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_258 FreePDK45_38x28_10R_NP_162NW_34O 20140 742280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_259 FreePDK45_38x28_10R_NP_162NW_34O 20140 745080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_260 FreePDK45_38x28_10R_NP_162NW_34O 20140 747880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_261 FreePDK45_38x28_10R_NP_162NW_34O 20140 750680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_262 FreePDK45_38x28_10R_NP_162NW_34O 20140 753480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_263 FreePDK45_38x28_10R_NP_162NW_34O 20140 756280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_264 FreePDK45_38x28_10R_NP_162NW_34O 20140 759080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_265 FreePDK45_38x28_10R_NP_162NW_34O 20140 761880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_266 FreePDK45_38x28_10R_NP_162NW_34O 20140 764680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_267 FreePDK45_38x28_10R_NP_162NW_34O 20140 767480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_268 FreePDK45_38x28_10R_NP_162NW_34O 20140 770280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_269 FreePDK45_38x28_10R_NP_162NW_34O 20140 773080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_270 FreePDK45_38x28_10R_NP_162NW_34O 20140 775880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_271 FreePDK45_38x28_10R_NP_162NW_34O 20140 778680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_272 FreePDK45_38x28_10R_NP_162NW_34O 20140 781480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_273 FreePDK45_38x28_10R_NP_162NW_34O 20140 784280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_274 FreePDK45_38x28_10R_NP_162NW_34O 20140 787080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_275 FreePDK45_38x28_10R_NP_162NW_34O 20140 789880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_276 FreePDK45_38x28_10R_NP_162NW_34O 20140 792680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_277 FreePDK45_38x28_10R_NP_162NW_34O 20140 795480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_278 FreePDK45_38x28_10R_NP_162NW_34O 20140 798280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_279 FreePDK45_38x28_10R_NP_162NW_34O 20140 801080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_280 FreePDK45_38x28_10R_NP_162NW_34O 20140 803880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_281 FreePDK45_38x28_10R_NP_162NW_34O 20140 806680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_282 FreePDK45_38x28_10R_NP_162NW_34O 20140 809480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_283 FreePDK45_38x28_10R_NP_162NW_34O 20140 812280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_284 FreePDK45_38x28_10R_NP_162NW_34O 20140 815080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_285 FreePDK45_38x28_10R_NP_162NW_34O 20140 817880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_286 FreePDK45_38x28_10R_NP_162NW_34O 20140 820680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_287 FreePDK45_38x28_10R_NP_162NW_34O 20140 823480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_288 FreePDK45_38x28_10R_NP_162NW_34O 20140 826280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_289 FreePDK45_38x28_10R_NP_162NW_34O 20140 829080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_290 FreePDK45_38x28_10R_NP_162NW_34O 20140 831880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_291 FreePDK45_38x28_10R_NP_162NW_34O 20140 834680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_292 FreePDK45_38x28_10R_NP_162NW_34O 20140 837480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_293 FreePDK45_38x28_10R_NP_162NW_34O 20140 840280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_294 FreePDK45_38x28_10R_NP_162NW_34O 20140 843080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_295 FreePDK45_38x28_10R_NP_162NW_34O 20140 845880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_296 FreePDK45_38x28_10R_NP_162NW_34O 20140 848680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_297 FreePDK45_38x28_10R_NP_162NW_34O 20140 851480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_298 FreePDK45_38x28_10R_NP_162NW_34O 20140 854280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_299 FreePDK45_38x28_10R_NP_162NW_34O 20140 857080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_300 FreePDK45_38x28_10R_NP_162NW_34O 20140 859880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_301 FreePDK45_38x28_10R_NP_162NW_34O 20140 862680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_302 FreePDK45_38x28_10R_NP_162NW_34O 20140 865480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_303 FreePDK45_38x28_10R_NP_162NW_34O 20140 868280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_304 FreePDK45_38x28_10R_NP_162NW_34O 20140 871080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_305 FreePDK45_38x28_10R_NP_162NW_34O 20140 873880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_306 FreePDK45_38x28_10R_NP_162NW_34O 20140 876680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_307 FreePDK45_38x28_10R_NP_162NW_34O 20140 879480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_308 FreePDK45_38x28_10R_NP_162NW_34O 20140 882280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_309 FreePDK45_38x28_10R_NP_162NW_34O 20140 885080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_310 FreePDK45_38x28_10R_NP_162NW_34O 20140 887880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_311 FreePDK45_38x28_10R_NP_162NW_34O 20140 890680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_312 FreePDK45_38x28_10R_NP_162NW_34O 20140 893480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_313 FreePDK45_38x28_10R_NP_162NW_34O 20140 896280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_314 FreePDK45_38x28_10R_NP_162NW_34O 20140 899080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_315 FreePDK45_38x28_10R_NP_162NW_34O 20140 901880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_316 FreePDK45_38x28_10R_NP_162NW_34O 20140 904680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_317 FreePDK45_38x28_10R_NP_162NW_34O 20140 907480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_318 FreePDK45_38x28_10R_NP_162NW_34O 20140 910280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_319 FreePDK45_38x28_10R_NP_162NW_34O 20140 913080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_320 FreePDK45_38x28_10R_NP_162NW_34O 20140 915880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_321 FreePDK45_38x28_10R_NP_162NW_34O 20140 918680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_322 FreePDK45_38x28_10R_NP_162NW_34O 20140 921480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_323 FreePDK45_38x28_10R_NP_162NW_34O 20140 924280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_324 FreePDK45_38x28_10R_NP_162NW_34O 20140 927080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_325 FreePDK45_38x28_10R_NP_162NW_34O 20140 929880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_326 FreePDK45_38x28_10R_NP_162NW_34O 20140 932680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_327 FreePDK45_38x28_10R_NP_162NW_34O 20140 935480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_328 FreePDK45_38x28_10R_NP_162NW_34O 20140 938280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_329 FreePDK45_38x28_10R_NP_162NW_34O 20140 941080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_330 FreePDK45_38x28_10R_NP_162NW_34O 20140 943880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_331 FreePDK45_38x28_10R_NP_162NW_34O 20140 946680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_332 FreePDK45_38x28_10R_NP_162NW_34O 20140 949480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_333 FreePDK45_38x28_10R_NP_162NW_34O 20140 952280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_334 FreePDK45_38x28_10R_NP_162NW_34O 20140 955080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_335 FreePDK45_38x28_10R_NP_162NW_34O 20140 957880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_336 FreePDK45_38x28_10R_NP_162NW_34O 20140 960680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_337 FreePDK45_38x28_10R_NP_162NW_34O 20140 963480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_338 FreePDK45_38x28_10R_NP_162NW_34O 20140 966280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_339 FreePDK45_38x28_10R_NP_162NW_34O 20140 969080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_340 FreePDK45_38x28_10R_NP_162NW_34O 20140 971880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_341 FreePDK45_38x28_10R_NP_162NW_34O 20140 974680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_342 FreePDK45_38x28_10R_NP_162NW_34O 20140 977480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_343 FreePDK45_38x28_10R_NP_162NW_34O 20140 980280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_344 FreePDK45_38x28_10R_NP_162NW_34O 20140 983080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_345 FreePDK45_38x28_10R_NP_162NW_34O 20140 985880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_346 FreePDK45_38x28_10R_NP_162NW_34O 20140 988680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_347 FreePDK45_38x28_10R_NP_162NW_34O 20140 991480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_348 FreePDK45_38x28_10R_NP_162NW_34O 20140 994280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_349 FreePDK45_38x28_10R_NP_162NW_34O 20140 997080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_350 FreePDK45_38x28_10R_NP_162NW_34O 20140 999880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_351 FreePDK45_38x28_10R_NP_162NW_34O 20140 1002680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_352 FreePDK45_38x28_10R_NP_162NW_34O 20140 1005480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_353 FreePDK45_38x28_10R_NP_162NW_34O 20140 1008280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_354 FreePDK45_38x28_10R_NP_162NW_34O 20140 1011080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_355 FreePDK45_38x28_10R_NP_162NW_34O 20140 1013880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_356 FreePDK45_38x28_10R_NP_162NW_34O 20140 1016680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_357 FreePDK45_38x28_10R_NP_162NW_34O 20140 1019480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_358 FreePDK45_38x28_10R_NP_162NW_34O 20140 1022280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_359 FreePDK45_38x28_10R_NP_162NW_34O 20140 1025080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_360 FreePDK45_38x28_10R_NP_162NW_34O 20140 1027880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_361 FreePDK45_38x28_10R_NP_162NW_34O 20140 1030680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_362 FreePDK45_38x28_10R_NP_162NW_34O 20140 1033480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_363 FreePDK45_38x28_10R_NP_162NW_34O 20140 1036280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_364 FreePDK45_38x28_10R_NP_162NW_34O 20140 1039080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_365 FreePDK45_38x28_10R_NP_162NW_34O 20140 1041880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_366 FreePDK45_38x28_10R_NP_162NW_34O 20140 1044680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_367 FreePDK45_38x28_10R_NP_162NW_34O 20140 1047480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_368 FreePDK45_38x28_10R_NP_162NW_34O 20140 1050280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_369 FreePDK45_38x28_10R_NP_162NW_34O 20140 1053080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_370 FreePDK45_38x28_10R_NP_162NW_34O 20140 1055880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_371 FreePDK45_38x28_10R_NP_162NW_34O 20140 1058680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_372 FreePDK45_38x28_10R_NP_162NW_34O 20140 1061480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_373 FreePDK45_38x28_10R_NP_162NW_34O 20140 1064280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_374 FreePDK45_38x28_10R_NP_162NW_34O 20140 1067080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_375 FreePDK45_38x28_10R_NP_162NW_34O 20140 1069880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_376 FreePDK45_38x28_10R_NP_162NW_34O 20140 1072680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_377 FreePDK45_38x28_10R_NP_162NW_34O 20140 1075480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_378 FreePDK45_38x28_10R_NP_162NW_34O 20140 1078280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_379 FreePDK45_38x28_10R_NP_162NW_34O 20140 1081080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_380 FreePDK45_38x28_10R_NP_162NW_34O 20140 1083880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_381 FreePDK45_38x28_10R_NP_162NW_34O 20140 1086680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_382 FreePDK45_38x28_10R_NP_162NW_34O 20140 1089480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_383 FreePDK45_38x28_10R_NP_162NW_34O 20140 1092280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_384 FreePDK45_38x28_10R_NP_162NW_34O 20140 1095080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_385 FreePDK45_38x28_10R_NP_162NW_34O 20140 1097880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_386 FreePDK45_38x28_10R_NP_162NW_34O 20140 1100680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_387 FreePDK45_38x28_10R_NP_162NW_34O 20140 1103480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_388 FreePDK45_38x28_10R_NP_162NW_34O 20140 1106280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_389 FreePDK45_38x28_10R_NP_162NW_34O 20140 1109080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_390 FreePDK45_38x28_10R_NP_162NW_34O 20140 1111880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_391 FreePDK45_38x28_10R_NP_162NW_34O 20140 1114680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_392 FreePDK45_38x28_10R_NP_162NW_34O 20140 1117480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_393 FreePDK45_38x28_10R_NP_162NW_34O 20140 1120280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_394 FreePDK45_38x28_10R_NP_162NW_34O 20140 1123080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_395 FreePDK45_38x28_10R_NP_162NW_34O 20140 1125880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_396 FreePDK45_38x28_10R_NP_162NW_34O 20140 1128680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_397 FreePDK45_38x28_10R_NP_162NW_34O 20140 1131480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_398 FreePDK45_38x28_10R_NP_162NW_34O 20140 1134280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_399 FreePDK45_38x28_10R_NP_162NW_34O 20140 1137080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_400 FreePDK45_38x28_10R_NP_162NW_34O 20140 1139880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_401 FreePDK45_38x28_10R_NP_162NW_34O 20140 1142680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_402 FreePDK45_38x28_10R_NP_162NW_34O 20140 1145480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_403 FreePDK45_38x28_10R_NP_162NW_34O 20140 1148280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_404 FreePDK45_38x28_10R_NP_162NW_34O 20140 1151080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_405 FreePDK45_38x28_10R_NP_162NW_34O 20140 1153880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_406 FreePDK45_38x28_10R_NP_162NW_34O 20140 1156680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_407 FreePDK45_38x28_10R_NP_162NW_34O 20140 1159480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_408 FreePDK45_38x28_10R_NP_162NW_34O 20140 1162280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_409 FreePDK45_38x28_10R_NP_162NW_34O 20140 1165080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_410 FreePDK45_38x28_10R_NP_162NW_34O 20140 1167880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_411 FreePDK45_38x28_10R_NP_162NW_34O 20140 1170680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_412 FreePDK45_38x28_10R_NP_162NW_34O 20140 1173480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_413 FreePDK45_38x28_10R_NP_162NW_34O 20140 1176280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_414 FreePDK45_38x28_10R_NP_162NW_34O 20140 1179080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_415 FreePDK45_38x28_10R_NP_162NW_34O 20140 1181880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_416 FreePDK45_38x28_10R_NP_162NW_34O 20140 1184680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_417 FreePDK45_38x28_10R_NP_162NW_34O 20140 1187480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_418 FreePDK45_38x28_10R_NP_162NW_34O 20140 1190280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_419 FreePDK45_38x28_10R_NP_162NW_34O 20140 1193080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_420 FreePDK45_38x28_10R_NP_162NW_34O 20140 1195880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_421 FreePDK45_38x28_10R_NP_162NW_34O 20140 1198680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_422 FreePDK45_38x28_10R_NP_162NW_34O 20140 1201480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_423 FreePDK45_38x28_10R_NP_162NW_34O 20140 1204280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_424 FreePDK45_38x28_10R_NP_162NW_34O 20140 1207080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_425 FreePDK45_38x28_10R_NP_162NW_34O 20140 1209880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_426 FreePDK45_38x28_10R_NP_162NW_34O 20140 1212680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_427 FreePDK45_38x28_10R_NP_162NW_34O 20140 1215480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_428 FreePDK45_38x28_10R_NP_162NW_34O 20140 1218280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_429 FreePDK45_38x28_10R_NP_162NW_34O 20140 1221080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_430 FreePDK45_38x28_10R_NP_162NW_34O 20140 1223880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_431 FreePDK45_38x28_10R_NP_162NW_34O 20140 1226680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_432 FreePDK45_38x28_10R_NP_162NW_34O 20140 1229480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_433 FreePDK45_38x28_10R_NP_162NW_34O 20140 1232280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_434 FreePDK45_38x28_10R_NP_162NW_34O 20140 1235080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_435 FreePDK45_38x28_10R_NP_162NW_34O 20140 1237880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_436 FreePDK45_38x28_10R_NP_162NW_34O 20140 1240680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_437 FreePDK45_38x28_10R_NP_162NW_34O 20140 1243480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_438 FreePDK45_38x28_10R_NP_162NW_34O 20140 1246280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_439 FreePDK45_38x28_10R_NP_162NW_34O 20140 1249080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_440 FreePDK45_38x28_10R_NP_162NW_34O 20140 1251880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_441 FreePDK45_38x28_10R_NP_162NW_34O 20140 1254680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_442 FreePDK45_38x28_10R_NP_162NW_34O 20140 1257480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_443 FreePDK45_38x28_10R_NP_162NW_34O 20140 1260280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_444 FreePDK45_38x28_10R_NP_162NW_34O 20140 1263080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_445 FreePDK45_38x28_10R_NP_162NW_34O 20140 1265880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_446 FreePDK45_38x28_10R_NP_162NW_34O 20140 1268680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_447 FreePDK45_38x28_10R_NP_162NW_34O 20140 1271480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_448 FreePDK45_38x28_10R_NP_162NW_34O 20140 1274280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_449 FreePDK45_38x28_10R_NP_162NW_34O 20140 1277080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_450 FreePDK45_38x28_10R_NP_162NW_34O 20140 1279880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_451 FreePDK45_38x28_10R_NP_162NW_34O 20140 1282680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_452 FreePDK45_38x28_10R_NP_162NW_34O 20140 1285480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_453 FreePDK45_38x28_10R_NP_162NW_34O 20140 1288280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_454 FreePDK45_38x28_10R_NP_162NW_34O 20140 1291080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_455 FreePDK45_38x28_10R_NP_162NW_34O 20140 1293880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_456 FreePDK45_38x28_10R_NP_162NW_34O 20140 1296680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_457 FreePDK45_38x28_10R_NP_162NW_34O 20140 1299480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_458 FreePDK45_38x28_10R_NP_162NW_34O 20140 1302280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_459 FreePDK45_38x28_10R_NP_162NW_34O 20140 1305080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_460 FreePDK45_38x28_10R_NP_162NW_34O 20140 1307880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_461 FreePDK45_38x28_10R_NP_162NW_34O 20140 1310680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_462 FreePDK45_38x28_10R_NP_162NW_34O 20140 1313480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_463 FreePDK45_38x28_10R_NP_162NW_34O 20140 1316280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_464 FreePDK45_38x28_10R_NP_162NW_34O 20140 1319080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_465 FreePDK45_38x28_10R_NP_162NW_34O 20140 1321880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_466 FreePDK45_38x28_10R_NP_162NW_34O 20140 1324680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_467 FreePDK45_38x28_10R_NP_162NW_34O 20140 1327480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_468 FreePDK45_38x28_10R_NP_162NW_34O 20140 1330280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_469 FreePDK45_38x28_10R_NP_162NW_34O 20140 1333080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_470 FreePDK45_38x28_10R_NP_162NW_34O 20140 1335880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_471 FreePDK45_38x28_10R_NP_162NW_34O 20140 1338680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_472 FreePDK45_38x28_10R_NP_162NW_34O 20140 1341480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_473 FreePDK45_38x28_10R_NP_162NW_34O 20140 1344280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_474 FreePDK45_38x28_10R_NP_162NW_34O 20140 1347080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_475 FreePDK45_38x28_10R_NP_162NW_34O 20140 1349880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_476 FreePDK45_38x28_10R_NP_162NW_34O 20140 1352680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_477 FreePDK45_38x28_10R_NP_162NW_34O 20140 1355480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_478 FreePDK45_38x28_10R_NP_162NW_34O 20140 1358280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_479 FreePDK45_38x28_10R_NP_162NW_34O 20140 1361080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_480 FreePDK45_38x28_10R_NP_162NW_34O 20140 1363880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_481 FreePDK45_38x28_10R_NP_162NW_34O 20140 1366680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_482 FreePDK45_38x28_10R_NP_162NW_34O 20140 1369480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_483 FreePDK45_38x28_10R_NP_162NW_34O 20140 1372280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_484 FreePDK45_38x28_10R_NP_162NW_34O 20140 1375080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_485 FreePDK45_38x28_10R_NP_162NW_34O 20140 1377880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_486 FreePDK45_38x28_10R_NP_162NW_34O 20140 1380680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_487 FreePDK45_38x28_10R_NP_162NW_34O 20140 1383480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_488 FreePDK45_38x28_10R_NP_162NW_34O 20140 1386280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_489 FreePDK45_38x28_10R_NP_162NW_34O 20140 1389080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_490 FreePDK45_38x28_10R_NP_162NW_34O 20140 1391880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_491 FreePDK45_38x28_10R_NP_162NW_34O 20140 1394680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_492 FreePDK45_38x28_10R_NP_162NW_34O 20140 1397480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_493 FreePDK45_38x28_10R_NP_162NW_34O 20140 1400280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_494 FreePDK45_38x28_10R_NP_162NW_34O 20140 1403080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_495 FreePDK45_38x28_10R_NP_162NW_34O 20140 1405880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_496 FreePDK45_38x28_10R_NP_162NW_34O 20140 1408680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_497 FreePDK45_38x28_10R_NP_162NW_34O 20140 1411480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_498 FreePDK45_38x28_10R_NP_162NW_34O 20140 1414280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_499 FreePDK45_38x28_10R_NP_162NW_34O 20140 1417080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_500 FreePDK45_38x28_10R_NP_162NW_34O 20140 1419880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_501 FreePDK45_38x28_10R_NP_162NW_34O 20140 1422680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_502 FreePDK45_38x28_10R_NP_162NW_34O 20140 1425480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_503 FreePDK45_38x28_10R_NP_162NW_34O 20140 1428280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_504 FreePDK45_38x28_10R_NP_162NW_34O 20140 1431080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_505 FreePDK45_38x28_10R_NP_162NW_34O 20140 1433880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_506 FreePDK45_38x28_10R_NP_162NW_34O 20140 1436680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_507 FreePDK45_38x28_10R_NP_162NW_34O 20140 1439480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_508 FreePDK45_38x28_10R_NP_162NW_34O 20140 1442280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_509 FreePDK45_38x28_10R_NP_162NW_34O 20140 1445080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_510 FreePDK45_38x28_10R_NP_162NW_34O 20140 1447880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_511 FreePDK45_38x28_10R_NP_162NW_34O 20140 1450680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_512 FreePDK45_38x28_10R_NP_162NW_34O 20140 1453480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_513 FreePDK45_38x28_10R_NP_162NW_34O 20140 1456280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_514 FreePDK45_38x28_10R_NP_162NW_34O 20140 1459080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_515 FreePDK45_38x28_10R_NP_162NW_34O 20140 1461880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_516 FreePDK45_38x28_10R_NP_162NW_34O 20140 1464680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_517 FreePDK45_38x28_10R_NP_162NW_34O 20140 1467480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_518 FreePDK45_38x28_10R_NP_162NW_34O 20140 1470280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_519 FreePDK45_38x28_10R_NP_162NW_34O 20140 1473080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_520 FreePDK45_38x28_10R_NP_162NW_34O 20140 1475880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_521 FreePDK45_38x28_10R_NP_162NW_34O 20140 1478680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_522 FreePDK45_38x28_10R_NP_162NW_34O 20140 1481480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_523 FreePDK45_38x28_10R_NP_162NW_34O 20140 1484280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_524 FreePDK45_38x28_10R_NP_162NW_34O 20140 1487080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_525 FreePDK45_38x28_10R_NP_162NW_34O 20140 1489880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_526 FreePDK45_38x28_10R_NP_162NW_34O 20140 1492680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_527 FreePDK45_38x28_10R_NP_162NW_34O 20140 1495480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_528 FreePDK45_38x28_10R_NP_162NW_34O 20140 1498280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_529 FreePDK45_38x28_10R_NP_162NW_34O 20140 1501080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_530 FreePDK45_38x28_10R_NP_162NW_34O 20140 1503880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_531 FreePDK45_38x28_10R_NP_162NW_34O 20140 1506680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_532 FreePDK45_38x28_10R_NP_162NW_34O 20140 1509480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_533 FreePDK45_38x28_10R_NP_162NW_34O 20140 1512280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_534 FreePDK45_38x28_10R_NP_162NW_34O 20140 1515080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_535 FreePDK45_38x28_10R_NP_162NW_34O 20140 1517880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_536 FreePDK45_38x28_10R_NP_162NW_34O 20140 1520680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_537 FreePDK45_38x28_10R_NP_162NW_34O 20140 1523480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_538 FreePDK45_38x28_10R_NP_162NW_34O 20140 1526280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_539 FreePDK45_38x28_10R_NP_162NW_34O 20140 1529080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_540 FreePDK45_38x28_10R_NP_162NW_34O 20140 1531880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_541 FreePDK45_38x28_10R_NP_162NW_34O 20140 1534680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_542 FreePDK45_38x28_10R_NP_162NW_34O 20140 1537480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_543 FreePDK45_38x28_10R_NP_162NW_34O 20140 1540280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_544 FreePDK45_38x28_10R_NP_162NW_34O 20140 1543080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_545 FreePDK45_38x28_10R_NP_162NW_34O 20140 1545880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_546 FreePDK45_38x28_10R_NP_162NW_34O 20140 1548680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_547 FreePDK45_38x28_10R_NP_162NW_34O 20140 1551480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_548 FreePDK45_38x28_10R_NP_162NW_34O 20140 1554280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_549 FreePDK45_38x28_10R_NP_162NW_34O 20140 1557080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_550 FreePDK45_38x28_10R_NP_162NW_34O 20140 1559880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_551 FreePDK45_38x28_10R_NP_162NW_34O 20140 1562680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_552 FreePDK45_38x28_10R_NP_162NW_34O 20140 1565480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_553 FreePDK45_38x28_10R_NP_162NW_34O 20140 1568280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_554 FreePDK45_38x28_10R_NP_162NW_34O 20140 1571080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_555 FreePDK45_38x28_10R_NP_162NW_34O 20140 1573880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_556 FreePDK45_38x28_10R_NP_162NW_34O 20140 1576680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_557 FreePDK45_38x28_10R_NP_162NW_34O 20140 1579480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_558 FreePDK45_38x28_10R_NP_162NW_34O 20140 1582280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_559 FreePDK45_38x28_10R_NP_162NW_34O 20140 1585080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_560 FreePDK45_38x28_10R_NP_162NW_34O 20140 1587880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_561 FreePDK45_38x28_10R_NP_162NW_34O 20140 1590680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_562 FreePDK45_38x28_10R_NP_162NW_34O 20140 1593480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_563 FreePDK45_38x28_10R_NP_162NW_34O 20140 1596280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_564 FreePDK45_38x28_10R_NP_162NW_34O 20140 1599080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_565 FreePDK45_38x28_10R_NP_162NW_34O 20140 1601880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_566 FreePDK45_38x28_10R_NP_162NW_34O 20140 1604680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_567 FreePDK45_38x28_10R_NP_162NW_34O 20140 1607480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_568 FreePDK45_38x28_10R_NP_162NW_34O 20140 1610280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_569 FreePDK45_38x28_10R_NP_162NW_34O 20140 1613080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_570 FreePDK45_38x28_10R_NP_162NW_34O 20140 1615880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_571 FreePDK45_38x28_10R_NP_162NW_34O 20140 1618680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_572 FreePDK45_38x28_10R_NP_162NW_34O 20140 1621480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_573 FreePDK45_38x28_10R_NP_162NW_34O 20140 1624280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_574 FreePDK45_38x28_10R_NP_162NW_34O 20140 1627080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_575 FreePDK45_38x28_10R_NP_162NW_34O 20140 1629880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_576 FreePDK45_38x28_10R_NP_162NW_34O 20140 1632680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_577 FreePDK45_38x28_10R_NP_162NW_34O 20140 1635480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_578 FreePDK45_38x28_10R_NP_162NW_34O 20140 1638280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_579 FreePDK45_38x28_10R_NP_162NW_34O 20140 1641080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_580 FreePDK45_38x28_10R_NP_162NW_34O 20140 1643880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_581 FreePDK45_38x28_10R_NP_162NW_34O 20140 1646680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_582 FreePDK45_38x28_10R_NP_162NW_34O 20140 1649480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_583 FreePDK45_38x28_10R_NP_162NW_34O 20140 1652280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_584 FreePDK45_38x28_10R_NP_162NW_34O 20140 1655080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_585 FreePDK45_38x28_10R_NP_162NW_34O 20140 1657880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_586 FreePDK45_38x28_10R_NP_162NW_34O 20140 1660680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_587 FreePDK45_38x28_10R_NP_162NW_34O 20140 1663480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_588 FreePDK45_38x28_10R_NP_162NW_34O 20140 1666280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_589 FreePDK45_38x28_10R_NP_162NW_34O 20140 1669080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_590 FreePDK45_38x28_10R_NP_162NW_34O 20140 1671880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_591 FreePDK45_38x28_10R_NP_162NW_34O 20140 1674680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_592 FreePDK45_38x28_10R_NP_162NW_34O 20140 1677480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_593 FreePDK45_38x28_10R_NP_162NW_34O 20140 1680280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_594 FreePDK45_38x28_10R_NP_162NW_34O 20140 1683080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_595 FreePDK45_38x28_10R_NP_162NW_34O 20140 1685880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_596 FreePDK45_38x28_10R_NP_162NW_34O 20140 1688680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_597 FreePDK45_38x28_10R_NP_162NW_34O 20140 1691480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_598 FreePDK45_38x28_10R_NP_162NW_34O 20140 1694280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_599 FreePDK45_38x28_10R_NP_162NW_34O 20140 1697080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_600 FreePDK45_38x28_10R_NP_162NW_34O 20140 1699880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_601 FreePDK45_38x28_10R_NP_162NW_34O 20140 1702680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_602 FreePDK45_38x28_10R_NP_162NW_34O 20140 1705480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_603 FreePDK45_38x28_10R_NP_162NW_34O 20140 1708280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_604 FreePDK45_38x28_10R_NP_162NW_34O 20140 1711080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_605 FreePDK45_38x28_10R_NP_162NW_34O 20140 1713880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_606 FreePDK45_38x28_10R_NP_162NW_34O 20140 1716680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_607 FreePDK45_38x28_10R_NP_162NW_34O 20140 1719480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_608 FreePDK45_38x28_10R_NP_162NW_34O 20140 1722280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_609 FreePDK45_38x28_10R_NP_162NW_34O 20140 1725080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_610 FreePDK45_38x28_10R_NP_162NW_34O 20140 1727880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_611 FreePDK45_38x28_10R_NP_162NW_34O 20140 1730680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_612 FreePDK45_38x28_10R_NP_162NW_34O 20140 1733480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_613 FreePDK45_38x28_10R_NP_162NW_34O 20140 1736280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_614 FreePDK45_38x28_10R_NP_162NW_34O 20140 1739080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_615 FreePDK45_38x28_10R_NP_162NW_34O 20140 1741880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_616 FreePDK45_38x28_10R_NP_162NW_34O 20140 1744680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_617 FreePDK45_38x28_10R_NP_162NW_34O 20140 1747480 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_618 FreePDK45_38x28_10R_NP_162NW_34O 20140 1750280 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_619 FreePDK45_38x28_10R_NP_162NW_34O 20140 1753080 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_620 FreePDK45_38x28_10R_NP_162NW_34O 20140 1755880 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_621 FreePDK45_38x28_10R_NP_162NW_34O 20140 1758680 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_622 FreePDK45_38x28_10R_NP_162NW_34O 20140 1761480 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_623 FreePDK45_38x28_10R_NP_162NW_34O 20140 1764280 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_624 FreePDK45_38x28_10R_NP_162NW_34O 20140 1767080 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_625 FreePDK45_38x28_10R_NP_162NW_34O 20140 1769880 N DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_626 FreePDK45_38x28_10R_NP_162NW_34O 20140 1772680 FS DO 4631 BY 1 STEP 380 0
;
ROW CORE_ROW_627 FreePDK45_38x28_10R_NP_162NW_34O 20140 1775480 N DO 4631 BY 1 STEP 380 0
;
TRACKS Y 4020 DO 562 STEP 3200 LAYER metal10 ;
TRACKS X 3530 DO 535 STEP 3360 LAYER metal10 ;
TRACKS X 1850 DO 1071 STEP 1680 LAYER metal9 ;
TRACKS Y 4020 DO 562 STEP 3200 LAYER metal9 ;
TRACKS Y 1540 DO 1071 STEP 1680 LAYER metal8 ;
TRACKS X 1850 DO 1071 STEP 1680 LAYER metal8 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal7 ;
TRACKS Y 1540 DO 1071 STEP 1680 LAYER metal7 ;
TRACKS Y 420 DO 3214 STEP 560 LAYER metal6 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal6 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal5 ;
TRACKS Y 420 DO 3214 STEP 560 LAYER metal5 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal4 ;
TRACKS X 730 DO 3214 STEP 560 LAYER metal4 ;
TRACKS X 190 DO 4737 STEP 380 LAYER metal3 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal3 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal2 ;
TRACKS X 190 DO 4737 STEP 380 LAYER metal2 ;
TRACKS X 190 DO 4737 STEP 380 LAYER metal1 ;
TRACKS Y 140 DO 6429 STEP 280 LAYER metal1 ;
GCELLGRID X 1797590 DO 2 STEP 2470 ;
GCELLGRID X 190 DO 474 STEP 3800 ;
GCELLGRID X 0 DO 2 STEP 190 ;
GCELLGRID Y 1797740 DO 2 STEP 2380 ;
GCELLGRID Y 140 DO 643 STEP 2800 ;
GCELLGRID Y 0 DO 2 STEP 140 ;
COMPONENTS 20 ;
- i_tile/gen_caches_0__i_snitch_icache/i_lookup/i_data/genblk1_fr_sp_instance0 fakeram45_64x64 + PLACED ( 472980 29880 ) FN
+ HALO 10000 10000 10000 10000
......
Flows/NanGate45/mempool_tile/scripts/cadence/run_genus_hybrid.tcl 0 → 100644
# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence.
# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
source lib_setup.tcl
source design_setup.tcl
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_mmmc mmmc_iSpatial_setup.tcl
}
# set the output directories
set OUTPUTS_PATH syn_output
set REPORTS_PATH syn_rpt
set HANDOFF_PATH syn_handoff
if {![file exists ${OUTPUTS_PATH}]} {
file mkdir ${OUTPUTS_PATH}
}
if {![file exists ${REPORTS_PATH}]} {
file mkdir ${REPORTS_PATH}
}
if {![file exists ${HANDOFF_PATH}]} {
file mkdir ${HANDOFF_PATH}
}
#
# set threads
set_db max_cpus_per_server 16
set_db super_thread_servers "localhost"
#
set list_lib "$libworst"
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
read_physical -lefs $lefs
}
# Target library
set link_library $list_lib
set target_library $list_lib
# set pathi
set_db hdl_flatten_complex_port true
set_db hdl_record_naming_style %s_%s
set_db auto_ungroup none
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
set_db library $list_lib
}
#################################################
# Load Design and Initialize
#################################################
source rtl_list.tcl
foreach rtl_file $rtl_all {
read_hdl -sv $rtl_file
}
elaborate $DESIGN
time_info Elaboration
if {![info exist ::env(PHY_SYNTH)] || $::env(PHY_SYNTH) == 0} {
read_sdc $sdc
}
init_design
check_design -unresolved
check_timing_intent
# reports the physical layout estimation report from lef and QRC tech file
report_ple > ${REPORTS_PATH}/ple.rpt
###############################################
# Read DEF
###############################################
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
read_def $floorplan_def
check_floorplan -detailed
}
# keep hierarchy during synthesis
set_db auto_ungroup none
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_generic -physical
} else {
syn_generic
}
time_info GENERIC
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag generic
write_db ${OUTPUTS_PATH}/${DESIGN}_generic.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_map -physical
} else {
syn_map
}
time_info MAPPED
# generate a summary for the current stage of synthesis
write_reports -directory ${REPORTS_PATH} -tag map
write_db ${OUTPUTS_PATH}/${DESIGN}_map.db
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
syn_opt -spatial
} else {
syn_opt
}
time_info OPT
write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
##############################################################################
# Write reports
##############################################################################
# summarizes the information, warnings and errors
report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
# generate PPA reports
report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
write_reports -directory ${REPORTS_PATH} -tag final
if {[info exist ::env(PHY_SYNTH)] && $::env(PHY_SYNTH) == 1} {
write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
} else {
write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
}
exit
Flows/NanGate45/nvdla/README.md 0 → 100644
# **Synthesis, Place \& Route (SP\&R):**
Here we provide the setup to run SP&R of NVDLA design with 128 macros on NanGate45 using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
## **SP\&R Flow:**
We implement [NVDLA](../../../Testcases/nvdla/) on the NanGate45 platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/nangate45). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the NanGate45 platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/NanGate45*](../../../Enablements/NanGate45/) directory.
### **Using Cadence Genus and Innovus:**
All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.
**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
```
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
```
We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow.
<img src="./screenshots/nvdla_Innovus_ng45.png" alt="nvdla_cadence" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
<!--
### **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:
1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the below command
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
```
4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.
<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
-->
\ No newline at end of file
Flows/SKY130HD/ariane136/README.md
......@@ -2,10 +2,9 @@
Here we provide the setup to run SP&R of Ariane design with 136 macros on SKY130HD using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
- [**OpenROAD tools**](#using-openroad-flow-scripts)
## **SP\&R Flow:**
We implement Ariane design with [136 macros](../../../Testcases/ariane136/) on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.
We implement Ariane design with [136 macros](../../../Testcases/ariane136/) on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.
### **Using Cadence Genus and Innovus:**
......@@ -19,10 +18,7 @@ We also generate a synthesized netlist, which is available in the [*./netlist/*]
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Innovus requires a configuration file to run the macro placement flow. For this we use *proto_design -constraints mp_config.tcl* command. The configuration file [*mp_config.tcl*](./scripts/cadence/mp_config.tcl) is available in the *./scripts/cadence/* directory. Some details of the configuration files are as follows.
1. Provide the memory hierarchy name under the **SEED** section. If you do not provide the memory hierarchy here, then the macro placement constraints (e.g., cell orientation, spacing, etc.) related to that memory may be overlooked.
2. For each macro, valid orientation and spacing rules can be provided under the **MACRO** section. For example, we set valid macro orientation as *R0* for our run, horizontal spacing as *10um*, and vertical spacing as *5um*. Also, when you provide the cell name (ref name, not instance name) add the *isCell=true* option.
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using Cadence flow.
<img src="./screenshots/Ariane136_Innovus_Genus.png" alt="ariane136_cadence" width="400"/>
......
Flows/SKY130HD/nvdla/README.md 0 → 100644
# **Synthesis, Place \& Route (SP\&R):**
Here we provide the setup to run SP&R of NVDLA design with 128 macros on SKY130HD using commercial and open-source tools.
- [**SP\&R Flow**](#spr-flow)
- [**Cadence tools**](#using-cadence-genus-and-innovus)
## **SP\&R Flow:**
We implement [NVDLA](../../../Testcases/nvdla/) on the SKY130HD platform using the proprietary (commercial) tools **Cadence Genus** (Synthesis) and **Cadence Innovus** (P&R), and the open-source tools **Yosys** (Synthesis) and **OpenROAD** (P&R) (Soon, we will update the OpenROAD flow details). The required *.lef* and *.lib* files are downloaded from the OpenROAD-flow-scripts (ORFS) [GitHub](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms/sky130hd). We use the [fakeram](https://github.com/jjcherry56/bsg_fakeram) generator for the SKY130HD platform to generate the 16-bit (256x16, single-ported SRAM) memory. All the required *.lib* and *.lef* files are available in the [*Enablements/SKY130HD*](../../../Enablements/SKY130HD/) directory.
### **Using Cadence Genus and Innovus:**
All the required scripts are available in the [*./scripts/cadence/*](./scripts/cadence/) directory.
**Synthesis:** [run_genus.tcl](./scripts/cadence/run_genus.tcl) contains the setup for synthesis using Genus. It reads the .v files based on the list in [*./scripts/cadence/rtl_list.tcl*](./scripts/cadence/rtl_list.tcl) (changing the order of the file may cause errors). The timing constraints are provided in [*./constrains/NV_NVDLA_partition_c.sdc*](./constraints/NV_NVDLA_partition_c.sdc) file. To launch the synthesis run please use the below command
```
genus -overwrite -log log/genus.log -no_gui -files run_genus.tcl
```
We also generate a synthesized netlist, which is available in the [*./netlist/*](./netlist/) directory.
**P\&R:** [run_innovus.tcl](./scripts/cadence/run_invs.tcl) contains the setup for the P&R run using Innvous. It reads the netlist provided in [*./netlist/*](./netlist/) directory. To launch the P\&R run please use the below command.
```
innovus -64 -init run_invs.tcl -log log/run.log
```
Below is the screenshot of the NVDLA SP\&R database with 128 memory macros using Cadence flow. The 256x64 SRAM memory dimension is weird. This is the memory we have generated using the [bsg_fakeram](https://github.com/jjcherry56/bsg_fakeram) memory compiler.
<img src="./screenshots/nvdla_Innovus_sky130hd.png" alt="nvdla_cadence" width="400"/>
This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
<!--
### **Using OpenROAD-flow-scripts:**
Clone ORFS and build OpenROAD tools following the steps given [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). To run SP&R using OpenROAD tools follow the below mentioned steps:
1. Copy [*./scripts/OpenROAD/ariane.tar.gz*](./scripts/OpenROAD/ariane.tar.gz) file to *{ORFS Clone Directory}/OpenROAD-flow-scripts/flow/designs/nangate45* area.
2. Use command *tar -xvf ariane.tar.gz* to untar *ariane.tar.gz*. This will generate *ariane136* directory which contains all the files required to run SP&R using ORFS.
3. To launch the SP&R job go to the flow directory and use the below command
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config_hier.mk
```
4. config_hier.mk uses the **RTL-MP** (RTL Macro Placer) for macro placement. If you wish to run macro placement using the older **Triton Macro Placer**, please use the below command:
```
make DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
```
Below is the screenshot of the Ariane SP\&R database with 136 memory macros using the ORFS (RTL-MP) flow.
<img src="./screenshots/Ariane136_ORFS_SPNR.png" alt="ariane136_orfs" width="400"/>
-->
\ No newline at end of file
Testcases/nvdla/README.md
# Netlist preparation of NVDLA
We generate the RTL of NVDLA testcase using the steps given in [NVDLA/hw](https://github.com/nvdla/hw/tree/nv_small) GitHub repo. First we clone the **nv_small** branch and then we follow the steps givne in the [Integrator's Manual](http://nvdla.org/hw/v1/integration_guide.html). The [nv_small.spec](https://github.com/nvdla/hw/blob/nv_small/spec/defs/nv_small.spec) is used as the configuration file to generate the testcase.
We generate the RTL of the NVDLA testcase using the steps given in the [NVDLA/hw](https://github.com/nvdla/hw/tree/nv_small) GitHub repo. First, we clone the **nv_small** branch and then we follow the steps givne in the [Integrator's Manual](http://nvdla.org/hw/v1/integration_guide.html). The [nv_small.spec](https://github.com/nvdla/hw/blob/nv_small/spec/defs/nv_small.spec) is used as the configuration file to generate the testcase. As NVDLA partition *c* has macros, our testcase only includes the partition *c*.
All the generated verilogs are copied to the [*rtl*](./rtl/) directory. NVDLA design uses dual port 256x64 bit SRAM. All our enablements currently support only single port SRAMS so we use two single port 256x64 SRAMs (One for reading from the read address and another for writing to the write address. We understand this do not replicated the actual functionality). We added fakeram_256x64_dp wrapper module to replace the dual port SRAMS with two single port SRAM and instantiate this wrapper in the [nv_ram_rws_256x64.v](./rtl/nv_ram_rws_256x64.v) file in the placeof behavioral model of the dual port ram (*nv_ram_rws_256x64_logic*).
All the generated verilogs are copied to the [*rtl*](./rtl/) directory. NVDLA design uses dual-port 256x64 bit SRAM. All our enablements currently support only single-port SRAM. So we use two single-port 256x64 bit SRAMs (One for reading from the read address and another for writing to the write address. We understand this does not replicate the actual functionality). We added the *fakeram_256x64_dp* wrapper module to replace the dual-port SRAM with two single-port SRAMs and instantiate this wrapper in the [nv_ram_rws_256x64.v](./rtl/nv_ram_rws_256x64.v) file in place of the behavioral model of the dual-port SRAM (*nv_ram_rws_256x64_logic*). The *fakeram_256x64_dp* wrapper module is available in the *fakeram<7|45|130>_256x64_dp.v*.
During synthesis stageg if one of the memory output is not connected to anything then during optimization it will be removed. So we add this below logic for reading from the memory:
During the synthesis stage if the memory outputs are not connected to anything then they will be removed during optimization. So we add the following logic for the reading operation.
```
genvar k;
generate
......@@ -14,6 +14,6 @@ endgenerate
```
Problem faced:
Note:
- Clone the **nv_small** branch. For the default branch, generated RTL will have more than million instances.
- To fix the problem of missing perl package use the *cpan* command.
\ No newline at end of file
- To install the missing perl packages use the *cpan* command.
\ No newline at end of file
Testcases/nvdla/rtl/a deleted 100644 → 0
./nv_ram_rws_256x64.v:rf_2p_hsc_256x64_nogating rmod (
./rf_2p_hsc_256x64_nogating.v:// Instance Name: rf_2p_hsc_256x64_nogating
./rf_2p_hsc_256x64_nogating.v:module datapath_latch_rf_2p_hsc_256x64_nogating (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ,Q);
./rf_2p_hsc_256x64_nogating.v:endmodule // datapath_latch_rf_2p_hsc_256x64_nogating
./rf_2p_hsc_256x64_nogating.v:module rf_2p_hsc_256x64_nogating (VDDCE, VDDPE, VSSE, QA, CLKA, CENA, AA, CLKB, CENB,
./rf_2p_hsc_256x64_nogating.v:module rf_2p_hsc_256x64_nogating (QA, CLKA, CENA, AA, CLKB, CENB, AB, DB, STOV, EMAA,
./rf_2p_hsc_256x64_nogating.v: rf_2p_hsc_256x64_nogating_error_injection u1(.CLK(CLKA_), .Q_out(QA_), .A(AA_int), .CEN(CENA_int), .Q_in(QA_int));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA0 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[1]), .D(QA_int[1]), .DFTRAMBYP(1'b0), .mem_path(mem_path[0]), .XQ(XQA), .Q(QA_int[0]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA1 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[2]), .D(QA_int[2]), .DFTRAMBYP(1'b0), .mem_path(mem_path[1]), .XQ(XQA), .Q(QA_int[1]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA2 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[3]), .D(QA_int[3]), .DFTRAMBYP(1'b0), .mem_path(mem_path[2]), .XQ(XQA), .Q(QA_int[2]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA3 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[4]), .D(QA_int[4]), .DFTRAMBYP(1'b0), .mem_path(mem_path[3]), .XQ(XQA), .Q(QA_int[3]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA4 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[5]), .D(QA_int[5]), .DFTRAMBYP(1'b0), .mem_path(mem_path[4]), .XQ(XQA), .Q(QA_int[4]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA5 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[6]), .D(QA_int[6]), .DFTRAMBYP(1'b0), .mem_path(mem_path[5]), .XQ(XQA), .Q(QA_int[5]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA6 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[7]), .D(QA_int[7]), .DFTRAMBYP(1'b0), .mem_path(mem_path[6]), .XQ(XQA), .Q(QA_int[6]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA7 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[8]), .D(QA_int[8]), .DFTRAMBYP(1'b0), .mem_path(mem_path[7]), .XQ(XQA), .Q(QA_int[7]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA8 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[9]), .D(QA_int[9]), .DFTRAMBYP(1'b0), .mem_path(mem_path[8]), .XQ(XQA), .Q(QA_int[8]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA9 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[10]), .D(QA_int[10]), .DFTRAMBYP(1'b0), .mem_path(mem_path[9]), .XQ(XQA), .Q(QA_int[9]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA10 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[11]), .D(QA_int[11]), .DFTRAMBYP(1'b0), .mem_path(mem_path[10]), .XQ(XQA), .Q(QA_int[10]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA11 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[12]), .D(QA_int[12]), .DFTRAMBYP(1'b0), .mem_path(mem_path[11]), .XQ(XQA), .Q(QA_int[11]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA12 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[13]), .D(QA_int[13]), .DFTRAMBYP(1'b0), .mem_path(mem_path[12]), .XQ(XQA), .Q(QA_int[12]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA13 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[14]), .D(QA_int[14]), .DFTRAMBYP(1'b0), .mem_path(mem_path[13]), .XQ(XQA), .Q(QA_int[13]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA14 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[15]), .D(QA_int[15]), .DFTRAMBYP(1'b0), .mem_path(mem_path[14]), .XQ(XQA), .Q(QA_int[14]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA15 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[16]), .D(QA_int[16]), .DFTRAMBYP(1'b0), .mem_path(mem_path[15]), .XQ(XQA), .Q(QA_int[15]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA16 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[17]), .D(QA_int[17]), .DFTRAMBYP(1'b0), .mem_path(mem_path[16]), .XQ(XQA), .Q(QA_int[16]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA17 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[18]), .D(QA_int[18]), .DFTRAMBYP(1'b0), .mem_path(mem_path[17]), .XQ(XQA), .Q(QA_int[17]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA18 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[19]), .D(QA_int[19]), .DFTRAMBYP(1'b0), .mem_path(mem_path[18]), .XQ(XQA), .Q(QA_int[18]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA19 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[20]), .D(QA_int[20]), .DFTRAMBYP(1'b0), .mem_path(mem_path[19]), .XQ(XQA), .Q(QA_int[19]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA20 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[21]), .D(QA_int[21]), .DFTRAMBYP(1'b0), .mem_path(mem_path[20]), .XQ(XQA), .Q(QA_int[20]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA21 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[22]), .D(QA_int[22]), .DFTRAMBYP(1'b0), .mem_path(mem_path[21]), .XQ(XQA), .Q(QA_int[21]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA22 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[23]), .D(QA_int[23]), .DFTRAMBYP(1'b0), .mem_path(mem_path[22]), .XQ(XQA), .Q(QA_int[22]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA23 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[24]), .D(QA_int[24]), .DFTRAMBYP(1'b0), .mem_path(mem_path[23]), .XQ(XQA), .Q(QA_int[23]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA24 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[25]), .D(QA_int[25]), .DFTRAMBYP(1'b0), .mem_path(mem_path[24]), .XQ(XQA), .Q(QA_int[24]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA25 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[26]), .D(QA_int[26]), .DFTRAMBYP(1'b0), .mem_path(mem_path[25]), .XQ(XQA), .Q(QA_int[25]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA26 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[27]), .D(QA_int[27]), .DFTRAMBYP(1'b0), .mem_path(mem_path[26]), .XQ(XQA), .Q(QA_int[26]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA27 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[28]), .D(QA_int[28]), .DFTRAMBYP(1'b0), .mem_path(mem_path[27]), .XQ(XQA), .Q(QA_int[27]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA28 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[29]), .D(QA_int[29]), .DFTRAMBYP(1'b0), .mem_path(mem_path[28]), .XQ(XQA), .Q(QA_int[28]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA29 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[30]), .D(QA_int[30]), .DFTRAMBYP(1'b0), .mem_path(mem_path[29]), .XQ(XQA), .Q(QA_int[29]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA30 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[31]), .D(QA_int[31]), .DFTRAMBYP(1'b0), .mem_path(mem_path[30]), .XQ(XQA), .Q(QA_int[30]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA31 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(1'b0), .D(1'b0), .DFTRAMBYP(1'b0), .mem_path(mem_path[31]), .XQ(XQA|1'b0), .Q(QA_int[31]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA32 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(1'b0), .D(1'b0), .DFTRAMBYP(1'b0), .mem_path(mem_path[32]), .XQ(XQA|1'b0), .Q(QA_int[32]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA33 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[32]), .D(QA_int[32]), .DFTRAMBYP(1'b0), .mem_path(mem_path[33]), .XQ(XQA), .Q(QA_int[33]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA34 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[33]), .D(QA_int[33]), .DFTRAMBYP(1'b0), .mem_path(mem_path[34]), .XQ(XQA), .Q(QA_int[34]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA35 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[34]), .D(QA_int[34]), .DFTRAMBYP(1'b0), .mem_path(mem_path[35]), .XQ(XQA), .Q(QA_int[35]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA36 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[35]), .D(QA_int[35]), .DFTRAMBYP(1'b0), .mem_path(mem_path[36]), .XQ(XQA), .Q(QA_int[36]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA37 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[36]), .D(QA_int[36]), .DFTRAMBYP(1'b0), .mem_path(mem_path[37]), .XQ(XQA), .Q(QA_int[37]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA38 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[37]), .D(QA_int[37]), .DFTRAMBYP(1'b0), .mem_path(mem_path[38]), .XQ(XQA), .Q(QA_int[38]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA39 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[38]), .D(QA_int[38]), .DFTRAMBYP(1'b0), .mem_path(mem_path[39]), .XQ(XQA), .Q(QA_int[39]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA40 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[39]), .D(QA_int[39]), .DFTRAMBYP(1'b0), .mem_path(mem_path[40]), .XQ(XQA), .Q(QA_int[40]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA41 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[40]), .D(QA_int[40]), .DFTRAMBYP(1'b0), .mem_path(mem_path[41]), .XQ(XQA), .Q(QA_int[41]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA42 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[41]), .D(QA_int[41]), .DFTRAMBYP(1'b0), .mem_path(mem_path[42]), .XQ(XQA), .Q(QA_int[42]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA43 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[42]), .D(QA_int[42]), .DFTRAMBYP(1'b0), .mem_path(mem_path[43]), .XQ(XQA), .Q(QA_int[43]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA44 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[43]), .D(QA_int[43]), .DFTRAMBYP(1'b0), .mem_path(mem_path[44]), .XQ(XQA), .Q(QA_int[44]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA45 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[44]), .D(QA_int[44]), .DFTRAMBYP(1'b0), .mem_path(mem_path[45]), .XQ(XQA), .Q(QA_int[45]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA46 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[45]), .D(QA_int[45]), .DFTRAMBYP(1'b0), .mem_path(mem_path[46]), .XQ(XQA), .Q(QA_int[46]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA47 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[46]), .D(QA_int[46]), .DFTRAMBYP(1'b0), .mem_path(mem_path[47]), .XQ(XQA), .Q(QA_int[47]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA48 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[47]), .D(QA_int[47]), .DFTRAMBYP(1'b0), .mem_path(mem_path[48]), .XQ(XQA), .Q(QA_int[48]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA49 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[48]), .D(QA_int[48]), .DFTRAMBYP(1'b0), .mem_path(mem_path[49]), .XQ(XQA), .Q(QA_int[49]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA50 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[49]), .D(QA_int[49]), .DFTRAMBYP(1'b0), .mem_path(mem_path[50]), .XQ(XQA), .Q(QA_int[50]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA51 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[50]), .D(QA_int[50]), .DFTRAMBYP(1'b0), .mem_path(mem_path[51]), .XQ(XQA), .Q(QA_int[51]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA52 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[51]), .D(QA_int[51]), .DFTRAMBYP(1'b0), .mem_path(mem_path[52]), .XQ(XQA), .Q(QA_int[52]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA53 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[52]), .D(QA_int[52]), .DFTRAMBYP(1'b0), .mem_path(mem_path[53]), .XQ(XQA), .Q(QA_int[53]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA54 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[53]), .D(QA_int[53]), .DFTRAMBYP(1'b0), .mem_path(mem_path[54]), .XQ(XQA), .Q(QA_int[54]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA55 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[54]), .D(QA_int[54]), .DFTRAMBYP(1'b0), .mem_path(mem_path[55]), .XQ(XQA), .Q(QA_int[55]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA56 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[55]), .D(QA_int[55]), .DFTRAMBYP(1'b0), .mem_path(mem_path[56]), .XQ(XQA), .Q(QA_int[56]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA57 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[56]), .D(QA_int[56]), .DFTRAMBYP(1'b0), .mem_path(mem_path[57]), .XQ(XQA), .Q(QA_int[57]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA58 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[57]), .D(QA_int[57]), .DFTRAMBYP(1'b0), .mem_path(mem_path[58]), .XQ(XQA), .Q(QA_int[58]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA59 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[58]), .D(QA_int[58]), .DFTRAMBYP(1'b0), .mem_path(mem_path[59]), .XQ(XQA), .Q(QA_int[59]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA60 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[59]), .D(QA_int[59]), .DFTRAMBYP(1'b0), .mem_path(mem_path[60]), .XQ(XQA), .Q(QA_int[60]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA61 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[60]), .D(QA_int[60]), .DFTRAMBYP(1'b0), .mem_path(mem_path[61]), .XQ(XQA), .Q(QA_int[61]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA62 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[61]), .D(QA_int[61]), .DFTRAMBYP(1'b0), .mem_path(mem_path[62]), .XQ(XQA), .Q(QA_int[62]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA63 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[62]), .D(QA_int[62]), .DFTRAMBYP(1'b0), .mem_path(mem_path[63]), .XQ(XQA), .Q(QA_int[63]));
./rf_2p_hsc_256x64_nogating.v:module rf_2p_hsc_256x64_nogating (VDDCE, VDDPE, VSSE, QA, CLKA, CENA, AA, CLKB, CENB,
./rf_2p_hsc_256x64_nogating.v:module rf_2p_hsc_256x64_nogating (QA, CLKA, CENA, AA, CLKB, CENB, AB, DB, STOV, EMAA,
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA0 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[1]), .D(QA_int[1]), .DFTRAMBYP(1'b0), .mem_path(mem_path[0]), .XQ(XQA), .Q(QA_int[0]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA1 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[2]), .D(QA_int[2]), .DFTRAMBYP(1'b0), .mem_path(mem_path[1]), .XQ(XQA), .Q(QA_int[1]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA2 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[3]), .D(QA_int[3]), .DFTRAMBYP(1'b0), .mem_path(mem_path[2]), .XQ(XQA), .Q(QA_int[2]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA3 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[4]), .D(QA_int[4]), .DFTRAMBYP(1'b0), .mem_path(mem_path[3]), .XQ(XQA), .Q(QA_int[3]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA4 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[5]), .D(QA_int[5]), .DFTRAMBYP(1'b0), .mem_path(mem_path[4]), .XQ(XQA), .Q(QA_int[4]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA5 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[6]), .D(QA_int[6]), .DFTRAMBYP(1'b0), .mem_path(mem_path[5]), .XQ(XQA), .Q(QA_int[5]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA6 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[7]), .D(QA_int[7]), .DFTRAMBYP(1'b0), .mem_path(mem_path[6]), .XQ(XQA), .Q(QA_int[6]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA7 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[8]), .D(QA_int[8]), .DFTRAMBYP(1'b0), .mem_path(mem_path[7]), .XQ(XQA), .Q(QA_int[7]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA8 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[9]), .D(QA_int[9]), .DFTRAMBYP(1'b0), .mem_path(mem_path[8]), .XQ(XQA), .Q(QA_int[8]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA9 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[10]), .D(QA_int[10]), .DFTRAMBYP(1'b0), .mem_path(mem_path[9]), .XQ(XQA), .Q(QA_int[9]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA10 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[11]), .D(QA_int[11]), .DFTRAMBYP(1'b0), .mem_path(mem_path[10]), .XQ(XQA), .Q(QA_int[10]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA11 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[12]), .D(QA_int[12]), .DFTRAMBYP(1'b0), .mem_path(mem_path[11]), .XQ(XQA), .Q(QA_int[11]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA12 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[13]), .D(QA_int[13]), .DFTRAMBYP(1'b0), .mem_path(mem_path[12]), .XQ(XQA), .Q(QA_int[12]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA13 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[14]), .D(QA_int[14]), .DFTRAMBYP(1'b0), .mem_path(mem_path[13]), .XQ(XQA), .Q(QA_int[13]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA14 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[15]), .D(QA_int[15]), .DFTRAMBYP(1'b0), .mem_path(mem_path[14]), .XQ(XQA), .Q(QA_int[14]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA15 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[16]), .D(QA_int[16]), .DFTRAMBYP(1'b0), .mem_path(mem_path[15]), .XQ(XQA), .Q(QA_int[15]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA16 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[17]), .D(QA_int[17]), .DFTRAMBYP(1'b0), .mem_path(mem_path[16]), .XQ(XQA), .Q(QA_int[16]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA17 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[18]), .D(QA_int[18]), .DFTRAMBYP(1'b0), .mem_path(mem_path[17]), .XQ(XQA), .Q(QA_int[17]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA18 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[19]), .D(QA_int[19]), .DFTRAMBYP(1'b0), .mem_path(mem_path[18]), .XQ(XQA), .Q(QA_int[18]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA19 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[20]), .D(QA_int[20]), .DFTRAMBYP(1'b0), .mem_path(mem_path[19]), .XQ(XQA), .Q(QA_int[19]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA20 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[21]), .D(QA_int[21]), .DFTRAMBYP(1'b0), .mem_path(mem_path[20]), .XQ(XQA), .Q(QA_int[20]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA21 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[22]), .D(QA_int[22]), .DFTRAMBYP(1'b0), .mem_path(mem_path[21]), .XQ(XQA), .Q(QA_int[21]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA22 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[23]), .D(QA_int[23]), .DFTRAMBYP(1'b0), .mem_path(mem_path[22]), .XQ(XQA), .Q(QA_int[22]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA23 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[24]), .D(QA_int[24]), .DFTRAMBYP(1'b0), .mem_path(mem_path[23]), .XQ(XQA), .Q(QA_int[23]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA24 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[25]), .D(QA_int[25]), .DFTRAMBYP(1'b0), .mem_path(mem_path[24]), .XQ(XQA), .Q(QA_int[24]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA25 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[26]), .D(QA_int[26]), .DFTRAMBYP(1'b0), .mem_path(mem_path[25]), .XQ(XQA), .Q(QA_int[25]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA26 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[27]), .D(QA_int[27]), .DFTRAMBYP(1'b0), .mem_path(mem_path[26]), .XQ(XQA), .Q(QA_int[26]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA27 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[28]), .D(QA_int[28]), .DFTRAMBYP(1'b0), .mem_path(mem_path[27]), .XQ(XQA), .Q(QA_int[27]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA28 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[29]), .D(QA_int[29]), .DFTRAMBYP(1'b0), .mem_path(mem_path[28]), .XQ(XQA), .Q(QA_int[28]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA29 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[30]), .D(QA_int[30]), .DFTRAMBYP(1'b0), .mem_path(mem_path[29]), .XQ(XQA), .Q(QA_int[29]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA30 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[31]), .D(QA_int[31]), .DFTRAMBYP(1'b0), .mem_path(mem_path[30]), .XQ(XQA), .Q(QA_int[30]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA31 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(1'b0), .D(1'b0), .DFTRAMBYP(1'b0), .mem_path(mem_path[31]), .XQ(XQA|1'b0), .Q(QA_int[31]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA32 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(1'b0), .D(1'b0), .DFTRAMBYP(1'b0), .mem_path(mem_path[32]), .XQ(XQA|1'b0), .Q(QA_int[32]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA33 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[32]), .D(QA_int[32]), .DFTRAMBYP(1'b0), .mem_path(mem_path[33]), .XQ(XQA), .Q(QA_int[33]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA34 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[33]), .D(QA_int[33]), .DFTRAMBYP(1'b0), .mem_path(mem_path[34]), .XQ(XQA), .Q(QA_int[34]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA35 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[34]), .D(QA_int[34]), .DFTRAMBYP(1'b0), .mem_path(mem_path[35]), .XQ(XQA), .Q(QA_int[35]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA36 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[35]), .D(QA_int[35]), .DFTRAMBYP(1'b0), .mem_path(mem_path[36]), .XQ(XQA), .Q(QA_int[36]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA37 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[36]), .D(QA_int[36]), .DFTRAMBYP(1'b0), .mem_path(mem_path[37]), .XQ(XQA), .Q(QA_int[37]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA38 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[37]), .D(QA_int[37]), .DFTRAMBYP(1'b0), .mem_path(mem_path[38]), .XQ(XQA), .Q(QA_int[38]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA39 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[38]), .D(QA_int[38]), .DFTRAMBYP(1'b0), .mem_path(mem_path[39]), .XQ(XQA), .Q(QA_int[39]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA40 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[39]), .D(QA_int[39]), .DFTRAMBYP(1'b0), .mem_path(mem_path[40]), .XQ(XQA), .Q(QA_int[40]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA41 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[40]), .D(QA_int[40]), .DFTRAMBYP(1'b0), .mem_path(mem_path[41]), .XQ(XQA), .Q(QA_int[41]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA42 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[41]), .D(QA_int[41]), .DFTRAMBYP(1'b0), .mem_path(mem_path[42]), .XQ(XQA), .Q(QA_int[42]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA43 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[42]), .D(QA_int[42]), .DFTRAMBYP(1'b0), .mem_path(mem_path[43]), .XQ(XQA), .Q(QA_int[43]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA44 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[43]), .D(QA_int[43]), .DFTRAMBYP(1'b0), .mem_path(mem_path[44]), .XQ(XQA), .Q(QA_int[44]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA45 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[44]), .D(QA_int[44]), .DFTRAMBYP(1'b0), .mem_path(mem_path[45]), .XQ(XQA), .Q(QA_int[45]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA46 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[45]), .D(QA_int[45]), .DFTRAMBYP(1'b0), .mem_path(mem_path[46]), .XQ(XQA), .Q(QA_int[46]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA47 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[46]), .D(QA_int[46]), .DFTRAMBYP(1'b0), .mem_path(mem_path[47]), .XQ(XQA), .Q(QA_int[47]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA48 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[47]), .D(QA_int[47]), .DFTRAMBYP(1'b0), .mem_path(mem_path[48]), .XQ(XQA), .Q(QA_int[48]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA49 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[48]), .D(QA_int[48]), .DFTRAMBYP(1'b0), .mem_path(mem_path[49]), .XQ(XQA), .Q(QA_int[49]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA50 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[49]), .D(QA_int[49]), .DFTRAMBYP(1'b0), .mem_path(mem_path[50]), .XQ(XQA), .Q(QA_int[50]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA51 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[50]), .D(QA_int[50]), .DFTRAMBYP(1'b0), .mem_path(mem_path[51]), .XQ(XQA), .Q(QA_int[51]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA52 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[51]), .D(QA_int[51]), .DFTRAMBYP(1'b0), .mem_path(mem_path[52]), .XQ(XQA), .Q(QA_int[52]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA53 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[52]), .D(QA_int[52]), .DFTRAMBYP(1'b0), .mem_path(mem_path[53]), .XQ(XQA), .Q(QA_int[53]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA54 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[53]), .D(QA_int[53]), .DFTRAMBYP(1'b0), .mem_path(mem_path[54]), .XQ(XQA), .Q(QA_int[54]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA55 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[54]), .D(QA_int[54]), .DFTRAMBYP(1'b0), .mem_path(mem_path[55]), .XQ(XQA), .Q(QA_int[55]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA56 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[55]), .D(QA_int[55]), .DFTRAMBYP(1'b0), .mem_path(mem_path[56]), .XQ(XQA), .Q(QA_int[56]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA57 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[56]), .D(QA_int[56]), .DFTRAMBYP(1'b0), .mem_path(mem_path[57]), .XQ(XQA), .Q(QA_int[57]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA58 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[57]), .D(QA_int[57]), .DFTRAMBYP(1'b0), .mem_path(mem_path[58]), .XQ(XQA), .Q(QA_int[58]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA59 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[58]), .D(QA_int[58]), .DFTRAMBYP(1'b0), .mem_path(mem_path[59]), .XQ(XQA), .Q(QA_int[59]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA60 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[59]), .D(QA_int[59]), .DFTRAMBYP(1'b0), .mem_path(mem_path[60]), .XQ(XQA), .Q(QA_int[60]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA61 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[60]), .D(QA_int[60]), .DFTRAMBYP(1'b0), .mem_path(mem_path[61]), .XQ(XQA), .Q(QA_int[61]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA62 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[61]), .D(QA_int[61]), .DFTRAMBYP(1'b0), .mem_path(mem_path[62]), .XQ(XQA), .Q(QA_int[62]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA63 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[62]), .D(QA_int[62]), .DFTRAMBYP(1'b0), .mem_path(mem_path[63]), .XQ(XQA), .Q(QA_int[63]));
./rf_2p_hsc_256x64_nogating.v:module rf_2p_hsc_256x64_nogating (VDDCE, VDDPE, VSSE, QA, CLKA, CENA, AA, CLKB, CENB,
./rf_2p_hsc_256x64_nogating.v:module rf_2p_hsc_256x64_nogating (QA, CLKA, CENA, AA, CLKB, CENB, AB, DB, STOV, EMAA,
./rf_2p_hsc_256x64_nogating.v: rf_2p_hsc_256x64_nogating_error_injection u1(.CLK(CLKA_), .Q_out(QA_), .A(AA_int), .CEN(CENA_int), .Q_in(QA_int));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA0 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[1]), .D(QA_int[1]), .DFTRAMBYP(1'b0), .mem_path(mem_path[0]), .XQ(XQA), .Q(QA_int[0]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA1 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[2]), .D(QA_int[2]), .DFTRAMBYP(1'b0), .mem_path(mem_path[1]), .XQ(XQA), .Q(QA_int[1]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA2 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[3]), .D(QA_int[3]), .DFTRAMBYP(1'b0), .mem_path(mem_path[2]), .XQ(XQA), .Q(QA_int[2]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA3 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[4]), .D(QA_int[4]), .DFTRAMBYP(1'b0), .mem_path(mem_path[3]), .XQ(XQA), .Q(QA_int[3]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA4 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[5]), .D(QA_int[5]), .DFTRAMBYP(1'b0), .mem_path(mem_path[4]), .XQ(XQA), .Q(QA_int[4]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA5 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[6]), .D(QA_int[6]), .DFTRAMBYP(1'b0), .mem_path(mem_path[5]), .XQ(XQA), .Q(QA_int[5]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA6 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[7]), .D(QA_int[7]), .DFTRAMBYP(1'b0), .mem_path(mem_path[6]), .XQ(XQA), .Q(QA_int[6]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA7 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[8]), .D(QA_int[8]), .DFTRAMBYP(1'b0), .mem_path(mem_path[7]), .XQ(XQA), .Q(QA_int[7]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA8 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[9]), .D(QA_int[9]), .DFTRAMBYP(1'b0), .mem_path(mem_path[8]), .XQ(XQA), .Q(QA_int[8]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA9 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[10]), .D(QA_int[10]), .DFTRAMBYP(1'b0), .mem_path(mem_path[9]), .XQ(XQA), .Q(QA_int[9]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA10 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[11]), .D(QA_int[11]), .DFTRAMBYP(1'b0), .mem_path(mem_path[10]), .XQ(XQA), .Q(QA_int[10]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA11 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[12]), .D(QA_int[12]), .DFTRAMBYP(1'b0), .mem_path(mem_path[11]), .XQ(XQA), .Q(QA_int[11]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA12 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[13]), .D(QA_int[13]), .DFTRAMBYP(1'b0), .mem_path(mem_path[12]), .XQ(XQA), .Q(QA_int[12]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA13 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[14]), .D(QA_int[14]), .DFTRAMBYP(1'b0), .mem_path(mem_path[13]), .XQ(XQA), .Q(QA_int[13]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA14 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[15]), .D(QA_int[15]), .DFTRAMBYP(1'b0), .mem_path(mem_path[14]), .XQ(XQA), .Q(QA_int[14]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA15 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[16]), .D(QA_int[16]), .DFTRAMBYP(1'b0), .mem_path(mem_path[15]), .XQ(XQA), .Q(QA_int[15]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA16 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[17]), .D(QA_int[17]), .DFTRAMBYP(1'b0), .mem_path(mem_path[16]), .XQ(XQA), .Q(QA_int[16]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA17 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[18]), .D(QA_int[18]), .DFTRAMBYP(1'b0), .mem_path(mem_path[17]), .XQ(XQA), .Q(QA_int[17]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA18 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[19]), .D(QA_int[19]), .DFTRAMBYP(1'b0), .mem_path(mem_path[18]), .XQ(XQA), .Q(QA_int[18]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA19 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[20]), .D(QA_int[20]), .DFTRAMBYP(1'b0), .mem_path(mem_path[19]), .XQ(XQA), .Q(QA_int[19]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA20 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[21]), .D(QA_int[21]), .DFTRAMBYP(1'b0), .mem_path(mem_path[20]), .XQ(XQA), .Q(QA_int[20]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA21 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[22]), .D(QA_int[22]), .DFTRAMBYP(1'b0), .mem_path(mem_path[21]), .XQ(XQA), .Q(QA_int[21]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA22 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[23]), .D(QA_int[23]), .DFTRAMBYP(1'b0), .mem_path(mem_path[22]), .XQ(XQA), .Q(QA_int[22]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA23 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[24]), .D(QA_int[24]), .DFTRAMBYP(1'b0), .mem_path(mem_path[23]), .XQ(XQA), .Q(QA_int[23]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA24 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[25]), .D(QA_int[25]), .DFTRAMBYP(1'b0), .mem_path(mem_path[24]), .XQ(XQA), .Q(QA_int[24]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA25 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[26]), .D(QA_int[26]), .DFTRAMBYP(1'b0), .mem_path(mem_path[25]), .XQ(XQA), .Q(QA_int[25]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA26 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[27]), .D(QA_int[27]), .DFTRAMBYP(1'b0), .mem_path(mem_path[26]), .XQ(XQA), .Q(QA_int[26]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA27 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[28]), .D(QA_int[28]), .DFTRAMBYP(1'b0), .mem_path(mem_path[27]), .XQ(XQA), .Q(QA_int[27]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA28 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[29]), .D(QA_int[29]), .DFTRAMBYP(1'b0), .mem_path(mem_path[28]), .XQ(XQA), .Q(QA_int[28]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA29 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[30]), .D(QA_int[30]), .DFTRAMBYP(1'b0), .mem_path(mem_path[29]), .XQ(XQA), .Q(QA_int[29]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA30 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[31]), .D(QA_int[31]), .DFTRAMBYP(1'b0), .mem_path(mem_path[30]), .XQ(XQA), .Q(QA_int[30]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA31 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(1'b0), .D(1'b0), .DFTRAMBYP(1'b0), .mem_path(mem_path[31]), .XQ(XQA|1'b0), .Q(QA_int[31]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA32 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(1'b0), .D(1'b0), .DFTRAMBYP(1'b0), .mem_path(mem_path[32]), .XQ(XQA|1'b0), .Q(QA_int[32]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA33 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[32]), .D(QA_int[32]), .DFTRAMBYP(1'b0), .mem_path(mem_path[33]), .XQ(XQA), .Q(QA_int[33]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA34 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[33]), .D(QA_int[33]), .DFTRAMBYP(1'b0), .mem_path(mem_path[34]), .XQ(XQA), .Q(QA_int[34]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA35 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[34]), .D(QA_int[34]), .DFTRAMBYP(1'b0), .mem_path(mem_path[35]), .XQ(XQA), .Q(QA_int[35]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA36 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[35]), .D(QA_int[35]), .DFTRAMBYP(1'b0), .mem_path(mem_path[36]), .XQ(XQA), .Q(QA_int[36]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA37 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[36]), .D(QA_int[36]), .DFTRAMBYP(1'b0), .mem_path(mem_path[37]), .XQ(XQA), .Q(QA_int[37]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA38 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[37]), .D(QA_int[37]), .DFTRAMBYP(1'b0), .mem_path(mem_path[38]), .XQ(XQA), .Q(QA_int[38]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA39 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[38]), .D(QA_int[38]), .DFTRAMBYP(1'b0), .mem_path(mem_path[39]), .XQ(XQA), .Q(QA_int[39]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA40 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[39]), .D(QA_int[39]), .DFTRAMBYP(1'b0), .mem_path(mem_path[40]), .XQ(XQA), .Q(QA_int[40]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA41 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[40]), .D(QA_int[40]), .DFTRAMBYP(1'b0), .mem_path(mem_path[41]), .XQ(XQA), .Q(QA_int[41]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA42 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[41]), .D(QA_int[41]), .DFTRAMBYP(1'b0), .mem_path(mem_path[42]), .XQ(XQA), .Q(QA_int[42]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA43 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[42]), .D(QA_int[42]), .DFTRAMBYP(1'b0), .mem_path(mem_path[43]), .XQ(XQA), .Q(QA_int[43]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA44 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[43]), .D(QA_int[43]), .DFTRAMBYP(1'b0), .mem_path(mem_path[44]), .XQ(XQA), .Q(QA_int[44]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA45 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[44]), .D(QA_int[44]), .DFTRAMBYP(1'b0), .mem_path(mem_path[45]), .XQ(XQA), .Q(QA_int[45]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA46 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[45]), .D(QA_int[45]), .DFTRAMBYP(1'b0), .mem_path(mem_path[46]), .XQ(XQA), .Q(QA_int[46]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA47 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[46]), .D(QA_int[46]), .DFTRAMBYP(1'b0), .mem_path(mem_path[47]), .XQ(XQA), .Q(QA_int[47]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA48 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[47]), .D(QA_int[47]), .DFTRAMBYP(1'b0), .mem_path(mem_path[48]), .XQ(XQA), .Q(QA_int[48]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA49 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[48]), .D(QA_int[48]), .DFTRAMBYP(1'b0), .mem_path(mem_path[49]), .XQ(XQA), .Q(QA_int[49]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA50 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[49]), .D(QA_int[49]), .DFTRAMBYP(1'b0), .mem_path(mem_path[50]), .XQ(XQA), .Q(QA_int[50]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA51 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[50]), .D(QA_int[50]), .DFTRAMBYP(1'b0), .mem_path(mem_path[51]), .XQ(XQA), .Q(QA_int[51]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA52 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[51]), .D(QA_int[51]), .DFTRAMBYP(1'b0), .mem_path(mem_path[52]), .XQ(XQA), .Q(QA_int[52]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA53 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[52]), .D(QA_int[52]), .DFTRAMBYP(1'b0), .mem_path(mem_path[53]), .XQ(XQA), .Q(QA_int[53]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA54 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[53]), .D(QA_int[53]), .DFTRAMBYP(1'b0), .mem_path(mem_path[54]), .XQ(XQA), .Q(QA_int[54]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA55 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[54]), .D(QA_int[54]), .DFTRAMBYP(1'b0), .mem_path(mem_path[55]), .XQ(XQA), .Q(QA_int[55]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA56 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[55]), .D(QA_int[55]), .DFTRAMBYP(1'b0), .mem_path(mem_path[56]), .XQ(XQA), .Q(QA_int[56]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA57 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[56]), .D(QA_int[56]), .DFTRAMBYP(1'b0), .mem_path(mem_path[57]), .XQ(XQA), .Q(QA_int[57]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA58 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[57]), .D(QA_int[57]), .DFTRAMBYP(1'b0), .mem_path(mem_path[58]), .XQ(XQA), .Q(QA_int[58]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA59 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[58]), .D(QA_int[58]), .DFTRAMBYP(1'b0), .mem_path(mem_path[59]), .XQ(XQA), .Q(QA_int[59]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA60 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[59]), .D(QA_int[59]), .DFTRAMBYP(1'b0), .mem_path(mem_path[60]), .XQ(XQA), .Q(QA_int[60]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA61 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[60]), .D(QA_int[60]), .DFTRAMBYP(1'b0), .mem_path(mem_path[61]), .XQ(XQA), .Q(QA_int[61]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA62 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[61]), .D(QA_int[61]), .DFTRAMBYP(1'b0), .mem_path(mem_path[62]), .XQ(XQA), .Q(QA_int[62]));
./rf_2p_hsc_256x64_nogating.v: datapath_latch_rf_2p_hsc_256x64_nogating uDQA63 (.CLK(CLKA), .Q_update(QA_update), .SE(1'b0), .SI(QA_int[62]), .D(QA_int[62]), .DFTRAMBYP(1'b0), .mem_path(mem_path[63]), .XQ(XQA), .Q(QA_int[63]));
./rf_2p_hsc_256x64_nogating.v:module rf_2p_hsc_256x64_nogating_error_injection (Q_out, Q_in, CLK, A, CEN);
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